Page MenuHomePhabricator

kbsmith1 (Kevin B. Smith)
User

Projects

User does not belong to any projects.

User Details

User Since
Apr 22 2015, 3:01 PM (221 w, 2 d)

Recent Activity

Jul 8 2016

kbsmith1 accepted D22083: X86FixupBWInsts: Forward liveness analysis is no longer necessary..

LGTM

Jul 8 2016, 9:18 PM

Jul 7 2016

kbsmith1 added a comment to D22083: X86FixupBWInsts: Forward liveness analysis is no longer necessary..

OK, sounds reasonable.

Jul 7 2016, 5:23 PM

Jul 6 2016

kbsmith1 added a comment to D22083: X86FixupBWInsts: Forward liveness analysis is no longer necessary..

What have you done to prove to yourself that this code is no longer necessary?
If unnecessary, then both before and after the change, the code for 401.bzip2 from spec20006 ought to
be identical.

Jul 6 2016, 9:38 PM

Jun 15 2016

kbsmith1 committed rL272835: [X86]: Fix for uninitialized access introduced in r272797..
[X86]: Fix for uninitialized access introduced in r272797.
Jun 15 2016, 1:59 PM
kbsmith1 committed rL272814: [X86]: Updated r272801 to promote 16 bit compares with immediate operand.
[X86]: Updated r272801 to promote 16 bit compares with immediate operand
Jun 15 2016, 11:25 AM
kbsmith1 committed rL272801: [X86]: Quit promoting 8 and 16 bit compares to 32 bit..
[X86]: Quit promoting 8 and 16 bit compares to 32 bit.
Jun 15 2016, 9:44 AM
kbsmith1 closed D21144: [X86]: Quit promoting 8 and 16 bit compares to 32 bit. by committing rL272801: [X86]: Quit promoting 8 and 16 bit compares to 32 bit..
Jun 15 2016, 9:44 AM
kbsmith1 committed rL272797: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp.
[X86]: Improve Liveness checking for X86FixupBWInsts.cpp
Jun 15 2016, 9:10 AM
kbsmith1 closed D21085: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp by committing rL272797: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp.
Jun 15 2016, 9:10 AM

Jun 14 2016

kbsmith1 added a comment to D21085: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp.

Ping. I believe I have addressed all comments.

Jun 14 2016, 2:28 PM

Jun 10 2016

kbsmith1 updated the diff for D21085: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp.

Addressed comments from Ahmed. Got rid of typedef, and created MIR based test.

Jun 10 2016, 10:08 AM

Jun 9 2016

kbsmith1 updated the diff for D21144: [X86]: Quit promoting 8 and 16 bit compares to 32 bit..

Updated changes so this will continue to promote 16 bit compares to 32 bits if one of the compare
operands is a constant. This addresses Eli Friedman's comment.

Jun 9 2016, 2:51 PM

Jun 8 2016

kbsmith1 added inline comments to D21144: [X86]: Quit promoting 8 and 16 bit compares to 32 bit..
Jun 8 2016, 3:48 PM
kbsmith1 updated the diff for D21085: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp.

Updated the comment in the test.

Jun 8 2016, 1:37 PM
kbsmith1 retitled D21144: [X86]: Quit promoting 8 and 16 bit compares to 32 bit. from to [X86]: Quit promoting 8 and 16 bit compares to 32 bit..
Jun 8 2016, 10:48 AM

Jun 7 2016

kbsmith1 updated the diff for D21085: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp.

Added minimalist (as possible) test, and changed to use auto as suggested.

Jun 7 2016, 3:42 PM
kbsmith1 added a comment to D21085: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp.

I'd love to add a test case. Of the spec2000 in tests, 175, 176, 252, 254, 256, and 300 all hit instances where
this new code finds new opportunities when going forward, that are missed when going backwards.

Jun 7 2016, 12:43 PM
kbsmith1 retitled D21085: [X86]: Improve Liveness checking for X86FixupBWInsts.cpp from to [X86]: Improve Liveness checking for X86FixupBWInsts.cpp.
Jun 7 2016, 10:35 AM

May 31 2016

kbsmith1 committed rL271341: [X86]: Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid….
[X86]: Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid…
May 31 2016, 3:07 PM
kbsmith1 closed D20649: [X86] Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live. by committing rL271341: [X86]: Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid….
May 31 2016, 3:07 PM

May 27 2016

kbsmith1 added a comment to D20649: [X86] Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live..

Addressed comments from Dave & Quentin.

May 27 2016, 3:25 PM
kbsmith1 updated the diff for D20649: [X86] Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live..

Updated test to use MIR output, and fixed Dave's minor comments on 32-bit and 16-bit.

May 27 2016, 3:24 PM

May 26 2016

kbsmith1 added a comment to D20649: [X86] Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live..

Great, I'll fix the small things Dave pointed out and get this committed.

May 26 2016, 2:45 PM

May 25 2016

kbsmith1 retitled D20649: [X86] Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live. from to [X86] Add a pattern that uses GR16_ABCD rather than GR32_ABCD to avoid falsely marking whole 32 bit register as live..
May 25 2016, 4:04 PM

May 9 2016

kbsmith1 accepted D20050: [TargetLowering] make helper function for SetCC + and optimizations (NFC).

LGTM.

May 9 2016, 9:31 AM

May 6 2016

kbsmith1 accepted D19999: [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr..

LGTM.

May 6 2016, 10:47 AM
kbsmith1 accepted D20006: [X86] Simplify FixupBW sub_8bit_hi-related logic. NFC..

Nice changes. I think those greatly improve the readability.

May 6 2016, 9:11 AM
kbsmith1 accepted D19087: [x86] prefer comparisons against zero for and+cmp sequences.

Did you add tests to check that lt/gt conditions don't get transformed?

Oops - let me add those and update the patch. The EQ/NE check is hopefully more obvious in the code now.

May 6 2016, 9:09 AM

May 5 2016

kbsmith1 added a comment to D19087: [x86] prefer comparisons against zero for and+cmp sequences.

Did you add tests to check that lt/gt conditions don't get transformed?

May 5 2016, 3:37 PM
kbsmith1 added a comment to D19999: [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr..

The code generally looks good. I don't see any tests that explicitly test this code though:

May 5 2016, 3:18 PM

Apr 27 2016

kbsmith1 committed rL267773: [X86]: Quit promoting 16 bit loads to 32 bit..
[X86]: Quit promoting 16 bit loads to 32 bit.
Apr 27 2016, 1:04 PM
kbsmith1 closed D19592: [X86]: Quit promoting 16 bit loads to 32 bit. by committing rL267773: [X86]: Quit promoting 16 bit loads to 32 bit..
Apr 27 2016, 1:04 PM
kbsmith1 retitled D19592: [X86]: Quit promoting 16 bit loads to 32 bit. from to [X86]: Quit promoting 16 bit loads to 32 bit..
Apr 27 2016, 7:10 AM

Apr 25 2016

kbsmith1 accepted D19488: [CodeGenPrepare] use branch weight metadata to decide if a select should be turned into a branch.

LGTM

Apr 25 2016, 1:14 PM
kbsmith1 accepted D19472: [X86] Use LivePhysRegs in X86FixupBWInsts..

LGTM

Apr 25 2016, 9:43 AM

Apr 14 2016

kbsmith1 added a comment to D19087: [x86] prefer comparisons against zero for and+cmp sequences.

Replied to inline comments.

Apr 14 2016, 12:56 PM

Apr 13 2016

kbsmith1 added a comment to D19087: [x86] prefer comparisons against zero for and+cmp sequences.

See inline comments.

Apr 13 2016, 6:12 PM

Apr 8 2016

kbsmith1 accepted D18910: [x86] use BMI 'andn' for logic + compare ops .

LGTM. One nit, fix or not at your discretion.

Apr 8 2016, 3:09 PM
kbsmith1 added a comment to D18802: Improve support for i386 and i486 CPUs..

Added inline comment.

Apr 8 2016, 1:49 PM
kbsmith1 updated subscribers of D18802: Improve support for i386 and i486 CPUs..
Apr 8 2016, 1:37 PM
kbsmith1 committed rL265830: [X86] Fix PR23155 by turning on X86FixupBWInsts by default..
[X86] Fix PR23155 by turning on X86FixupBWInsts by default.
Apr 8 2016, 12:04 PM
kbsmith1 closed D18866: [X86] Fix PR23155 by turning on X86FixupBWInsts by default by committing rL265830: [X86] Fix PR23155 by turning on X86FixupBWInsts by default..
Apr 8 2016, 12:04 PM
kbsmith1 added a comment to D18866: [X86] Fix PR23155 by turning on X86FixupBWInsts by default.

Yes, I have run perf results locally on a number of different kinds of boxes. As stated this does generate exactly the code desired
for PR23155 (modulo the alignment differences noted as having some performance effect in that PR).

Apr 8 2016, 9:56 AM

Apr 7 2016

kbsmith1 retitled D18866: [X86] Fix PR23155 by turning on X86FixupBWInsts by default from to [X86] Fix PR23155 by turning on X86FixupBWInsts by default.
Apr 7 2016, 1:52 PM
kbsmith1 added a comment to D18850: [X86]: Fix for PR27251.

-----Original Message-----
From: Simon Pilgrim [mailto:llvm-dev@redking.me.uk]
Sent: Thursday, April 07, 2016 11:03 AM
To: Smith, Kevin B <kevin.b.smith@intel.com>; Kreitzer, David L
<david.l.kreitzer@intel.com>; ahmed.bougacha@gmail.com
Cc: llvm-dev@redking.me.uk; llvm-commits@lists.llvm.org
Subject: Re: [PATCH] D18850: [X86]: Fix for PR27251

RKSimon added a subscriber: RKSimon.
RKSimon added a comment.

>

>

>

> Comment at: test/CodeGen/X86/vector-blend.ll:1011

> @@ -1010,3 +1010,3 @@

> ; SSE2-NEXT: pslld $31, %xmm1

> ; SSE2-NEXT: psrad $31, %xmm1

>

> ; SSE2-NEXT: pxor %xmm1, %xmm0

> ---------------------------------

>

> I know this isn't related to your change, but the redundant shifts here are

> pretty gross.

Why are the shifts redundant? One is a shift left by 31, and the other is a

arithmetic shift right by 31.

This has the effect of propagating bit 0 through all 32 bits of the vector

element.

For the pre-SSE41 cases its doing ashr( shl( lshr( v, 31 ), 31 ), 31) which
should be combined to ashr( v, 31 ) - this isn't that difficult.

For the SSE41 cases we don't need the shifts at all as (v)blendvps will select
elements based on the sign bit alone, but the vselect/blendv relationship is
rather nasty (change in input type behaviour after legalization) and I can
imagine a number of problems getting it to work cleanly - I've hit some of
these before trying to do late constant folding of vselect.

Apr 7 2016, 11:21 AM
kbsmith1 committed rL265690: [X86]: Fix for PR27251..
[X86]: Fix for PR27251.
Apr 7 2016, 9:21 AM
kbsmith1 closed D18850: [X86]: Fix for PR27251 by committing rL265690: [X86]: Fix for PR27251..
Apr 7 2016, 9:21 AM
kbsmith1 added a comment to D18850: [X86]: Fix for PR27251.

-----Original Message-----
From: David Kreitzer [mailto:david.l.kreitzer@intel.com]
Sent: Thursday, April 07, 2016 8:22 AM
To: Smith, Kevin B <kevin.b.smith@intel.com>;
ahmed.bougacha@gmail.com; Kreitzer, David L <david.l.kreitzer@intel.com>
Cc: llvm-commits@lists.llvm.org
Subject: Re: [PATCH] D18850: [X86]: Fix for PR27251

DavidKreitzer added a comment.

LGTM, Kevin.

Comment at: test/CodeGen/X86/vector-blend.ll:1011
@@ -1010,3 +1010,3 @@
; SSE2-NEXT: pslld $31, %xmm1
; SSE2-NEXT: psrad $31, %xmm1

; SSE2-NEXT: pxor %xmm1, %xmm0

I know this isn't related to your change, but the redundant shifts here are
pretty gross.

Apr 7 2016, 8:41 AM
kbsmith1 added a comment to D18850: [X86]: Fix for PR27251.

Thank you for the quick review Ahmed. I addressed both your comments.

Apr 7 2016, 8:37 AM
kbsmith1 updated the diff for D18850: [X86]: Fix for PR27251.

Addressed Ahmed's review comments.

Apr 7 2016, 8:35 AM

Apr 6 2016

kbsmith1 retitled D18850: [X86]: Fix for PR27251 from to [X86]: Fix for PR27251.
Apr 6 2016, 5:16 PM

Mar 28 2016

kbsmith1 accepted D18353: Release notes update.

LGTM

Mar 28 2016, 2:11 PM

Feb 21 2016

kbsmith1 closed D17458: [X86] More test updates to support fixup-byte-word-insts optimization either on or off..
Feb 21 2016, 8:47 PM
kbsmith1 committed rL261505: [X86] More test updates to support fixup-byte-word-insts optimization.
[X86] More test updates to support fixup-byte-word-insts optimization
Feb 21 2016, 5:32 PM

Feb 19 2016

kbsmith1 retitled D17458: [X86] More test updates to support fixup-byte-word-insts optimization either on or off. from to [X86] More test updates to support fixup-byte-word-insts optimization either on or off..
Feb 19 2016, 10:51 AM
kbsmith1 committed rL261332: [X86] Change fixup-bw-inst.ll to test output with this optimization on and off..
[X86] Change fixup-bw-inst.ll to test output with this optimization on and off.
Feb 19 2016, 8:25 AM
kbsmith1 closed D17415: [X86}: Change fixup-bw-inst.ll to test output with this optimization on and off. by committing rL261332: [X86] Change fixup-bw-inst.ll to test output with this optimization on and off..
Feb 19 2016, 8:25 AM
kbsmith1 added a comment to D17415: [X86}: Change fixup-bw-inst.ll to test output with this optimization on and off..

Thanks for the tips Sanjay.

Feb 19 2016, 8:23 AM

Feb 18 2016

kbsmith1 updated the diff for D17415: [X86}: Change fixup-bw-inst.ll to test output with this optimization on and off..

Doh - missed one instance. Now fixed.

Feb 18 2016, 5:16 PM
kbsmith1 added a comment to D17415: [X86}: Change fixup-bw-inst.ll to test output with this optimization on and off..
Feb 18 2016, 5:14 PM
kbsmith1 updated the diff for D17415: [X86}: Change fixup-bw-inst.ll to test output with this optimization on and off..

Fixes problem that Quentin pointed out.

Feb 18 2016, 5:13 PM
kbsmith1 added a comment to D17415: [X86}: Change fixup-bw-inst.ll to test output with this optimization on and off..

Sanjay - See if you like this form for testing with fixup-byte-word-insts both on and off. If you prefer this, then I
could make similar changes to the few other tests that are also affected when fixup-byte-word-insts would change
to be turned on by default.

Feb 18 2016, 2:17 PM
kbsmith1 retitled D17415: [X86}: Change fixup-bw-inst.ll to test output with this optimization on and off. from to [X86}: Change fixup-bw-inst.ll to test output with this optimization on and off..
Feb 18 2016, 2:15 PM
kbsmith1 abandoned D17173: [X86] Update test cases that would be affected when X86FixupBWInsts is turned on..
Feb 18 2016, 8:30 AM

Feb 12 2016

kbsmith1 added a comment to D17173: [X86] Update test cases that would be affected when X86FixupBWInsts is turned on..

This feels similar to D12656, and I don't think it's the right choice for the same reasons that were cited in that review.

I'd prefer that we just change the checks in these tests as part of flipping/removing the "-fixup-byte-word-insts" switch. Alternatively, we could add another RUN to these tests to show the exact codegen difference produced by -fixup-byte-word-insts for these cases.

Masking the default output could hide codegen differences that we would actually like to observe. As an example, we may want to limit the FixupBW pass based on micro-arch (should an in-order CPU get the same set of transforms as as OoO?). If that happens, then these tests become more important as verification that the default behavior is not changing.

Feb 12 2016, 11:21 AM

Feb 11 2016

kbsmith1 retitled D17173: [X86] Update test cases that would be affected when X86FixupBWInsts is turned on. from to [X86] Update test cases that would be affected when X86FixupBWInsts is turned on..
Feb 11 2016, 3:32 PM
kbsmith1 committed rL260572: [X86] New pass to change byte and word instructions to zero-extending versions..
[X86] New pass to change byte and word instructions to zero-extending versions.
Feb 11 2016, 11:47 AM
kbsmith1 closed D17032: [X86] Add a pass to change byte and word instructions to zero-extending versions. by committing rL260572: [X86] New pass to change byte and word instructions to zero-extending versions..
Feb 11 2016, 11:47 AM
kbsmith1 added a comment to D17032: [X86] Add a pass to change byte and word instructions to zero-extending versions..

Addressed inline comments.

Feb 11 2016, 9:38 AM
kbsmith1 updated the diff for D17032: [X86] Add a pass to change byte and word instructions to zero-extending versions..

New revision should address most of the comments.

Feb 11 2016, 9:33 AM

Feb 10 2016

kbsmith1 added a comment to D17032: [X86] Add a pass to change byte and word instructions to zero-extending versions..

Thanks for the comments. I'll work on fixing all those, and have a new version early tomorrow.

Feb 10 2016, 5:40 PM
kbsmith1 added a comment to D17032: [X86] Add a pass to change byte and word instructions to zero-extending versions..

Naming is hard and shouldn't block anything here. That said, what do you think about using this to get rid of some of the reg stall code that was listed? :)

Feb 10 2016, 4:05 PM
kbsmith1 added a comment to D17032: [X86] Add a pass to change byte and word instructions to zero-extending versions..

Eric - My expectation is this could be used both to get rid or partial stall code in other places, but I really don't know where those other places are at this time. If you have suggestions for places to look at for that, I'd like to look into fixing them using this.

There are a few spots that I know of:

  1. X86TargetLowering::EmitCmp() has the change introduced with http://reviews.llvm.org/rL195496 .
  2. The ExecutionDepsFix pass uses getPartialRegUpdateClearance() and getUndefRegClearance() to insert xor insts ( https://llvm.org/bugs/show_bug.cgi?id=22024 ).
  3. PerformTargetShuffleCombine() has a comment about movsd vs. blendpd.

    There are probably other cases in X86ISelLowering. It would be good to consolidate those kinds of transforms in a machine pass. So it may be worth renaming this to something more general (FixupPartialRegStalls?) before checking it in just to save on some naming churn.
Feb 10 2016, 3:32 PM
kbsmith1 added a comment to D17032: [X86] Add a pass to change byte and word instructions to zero-extending versions..

Sanjay - Thanks for the encouraging words. I'll be happy to commit whenever folks think that is appropriate.

Feb 10 2016, 2:27 PM
kbsmith1 added a comment to D17041: [X86] Don't assume that a shuffle operand is #0: it isn't for VPERMV..

-----Original Message-----
From: llvm-commits [mailto:llvm-commits-bounces@lists.llvm.org] On Behalf
Of Sanjay Patel via llvm-commits
Sent: Wednesday, February 10, 2016 10:58 AM
To: ahmed.bougacha@gmail.com; llvm-dev@redking.me.uk;
spatel@rotateright.com
Cc: llvm-commits@lists.llvm.org
Subject: Re: [PATCH] D17041: [X86] Don't assume that a shuffle operand is
#0: it isn't for VPERMV.

spatel added a comment.

In http://reviews.llvm.org/D17041#348716, @ab wrote:

..but now that I look it up, the AVX-512 intrinsics use the instruction order

*sigh*

Back to square one.

Wow. Is it too late for Intel to fix/deprecate/rename those intrinsics? If the
argument is that the intrinsics should match the asm, then what happened
with the AVX2 vperm variants?

Feb 10 2016, 11:06 AM

Feb 9 2016

kbsmith1 retitled D17032: [X86] Add a pass to change byte and word instructions to zero-extending versions. from to [X86] Add a pass to change byte and word instructions to zero-extending versions..
Feb 9 2016, 9:16 AM

Jan 21 2016

kbsmith1 accepted D16357: X86 processors and features.
Jan 21 2016, 3:09 PM
kbsmith1 added a comment to D16357: X86 processors and features.

Two nits. Up to you whether they are worth changing. Either way LGTM.

Jan 21 2016, 3:09 PM

Jan 15 2016

kbsmith1 committed rL257965: [X86]: Make param names in header and body match for isCalleePop..
[X86]: Make param names in header and body match for isCalleePop.
Jan 15 2016, 4:12 PM
kbsmith1 closed D16246: [X86]: Make param names in header and body match for isCalleePop by committing rL257965: [X86]: Make param names in header and body match for isCalleePop..
Jan 15 2016, 4:12 PM
kbsmith1 retitled D16246: [X86]: Make param names in header and body match for isCalleePop from to [X86]: Make param names in header and body match for isCalleePop.
Jan 15 2016, 3:48 PM

Dec 15 2015

kbsmith1 accepted D15294: [x86] inline calls to fmaxf / llvm.maxnum.f32 using maxss (PR24475).

LGTM

Dec 15 2015, 12:40 PM

Dec 3 2015

kbsmith1 committed rL254668: [CodeGen] Minor correction to comment on PhysRegInfo..
[CodeGen] Minor correction to comment on PhysRegInfo.
Dec 3 2015, 4:03 PM
kbsmith1 closed D15216: [CodeGen] Minor correction to comment on PhysRegInfo. by committing rL254668: [CodeGen] Minor correction to comment on PhysRegInfo..
Dec 3 2015, 4:03 PM
kbsmith1 retitled D15216: [CodeGen] Minor correction to comment on PhysRegInfo. from to [CodeGen] Minor correction to comment on PhysRegInfo. .
Dec 3 2015, 3:57 PM

Nov 9 2015

kbsmith1 accepted D13956: [x86] try harder to match bitwise 'or' into an LEA.

LGTM

Nov 9 2015, 11:29 AM

Oct 21 2015

kbsmith1 added a comment to D13767: [X86] Fix more -Os + EH issues.

I would still have preferred that in the "only correct for call-site" case that the cfi_adjust occurred after the pushes rather than before. But I don't feel strongly about that, and so, am good with the changes now.

Oct 21 2015, 12:39 PM

Oct 15 2015

kbsmith1 added a comment to D13767: [X86] Fix more -Os + EH issues.

Please see inline comments.

Oct 15 2015, 3:55 PM
kbsmith1 closed D13521: [X86]Update test to use FileCheck.
Oct 15 2015, 10:09 AM
kbsmith1 committed rL250431: Change test to use FileCheck rather than grep..
Change test to use FileCheck rather than grep.
Oct 15 2015, 10:07 AM
kbsmith1 closed D13751: Change test to use FileCheck rather than grep. by committing rL250431: Change test to use FileCheck rather than grep..
Oct 15 2015, 10:07 AM

Oct 14 2015

kbsmith1 retitled D13751: Change test to use FileCheck rather than grep. from to Change test to use FileCheck rather than grep..
Oct 14 2015, 3:28 PM

Oct 7 2015

kbsmith1 committed rL249583: [X86]Update test to use FileCheck..
[X86]Update test to use FileCheck.
Oct 7 2015, 11:23 AM
kbsmith1 retitled D13521: [X86]Update test to use FileCheck from to [X86]Update test to use FileCheck.
Oct 7 2015, 10:54 AM
kbsmith1 committed rL249571: Test commit access. Fixed comment to have correct input parameter name and.
Test commit access. Fixed comment to have correct input parameter name and
Oct 7 2015, 10:26 AM

Sep 9 2015

kbsmith1 abandoned D12656: PR 23155: Change test to allow movzbl,movzwl in place of movb,movw instructions.

Abandoned changes due to Quentin's opposition.

Sep 9 2015, 1:02 PM

Sep 8 2015

kbsmith1 added a comment to D12656: PR 23155: Change test to allow movzbl,movzwl in place of movb,movw instructions.

There are a handful (6-8) tests that currently are checking for movw, where either movzwl or movw would be legal choices. There are quite a few more that specifically expect movb where movzbl would also be legal. My intent was to add a test that tested for the specific movb vs movzbl or movw vs movzwl when the transformations to change these opcodes got added.

Sep 8 2015, 8:25 PM
kbsmith1 added a comment to D12656: PR 23155: Change test to allow movzbl,movzwl in place of movb,movw instructions.

Changed title, and explanation as Sanjay suggested. My expectation is that these tests should allow either the zero-extending
loads, or the plain byte/short instructions, as either are correct for the cpus specified.

Sep 8 2015, 9:33 AM
kbsmith1 retitled D12656: PR 23155: Change test to allow movzbl,movzwl in place of movb,movw instructions from Change test to allow movzbl,movzwl in place of movb,movw instructions to PR 23155: Change test to allow movzbl,movzwl in place of movb,movw instructions.
Sep 8 2015, 9:32 AM

Sep 4 2015

kbsmith1 retitled D12656: PR 23155: Change test to allow movzbl,movzwl in place of movb,movw instructions from to Change test to allow movzbl,movzwl in place of movb,movw instructions.
Sep 4 2015, 4:46 PM