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Differential D20385

[x86] avoid printing unnecessary sign bits of hex immediates in asm comments (PR20347)
ClosedPublic

Authored by spatel on May 18 2016, 2:22 PM.

Details

Reviewers
RKSimon
enderby
craig.topper
Commits
rG97c2c108fd23: [x86] avoid printing unnecessary sign bits of hex immediates in asm comments…
rL271114: [x86] avoid printing unnecessary sign bits of hex immediates in asm comments…
Summary

It would probably be better to check the valid/expected size of the immediate operand, but I don't see a way to do that.

Diff Detail

Event Timeline

spatel updated this revision to Diff 57676.May 18 2016, 2:22 PM
spatel retitled this revision from to [x86] avoid printing unnecessary sign bits of hex immediates in asm comments (PR20347).
spatel updated this object.
spatel added reviewers: craig.topper, enderby, RKSimon.
spatel added a subscriber: llvm-commits.
Herald added a subscriber: mcrosier. · View Herald TranscriptMay 18 2016, 2:22 PM
spatel mentioned this in D20434: [MCExpr] avoid UB via negation of INT_MIN.May 19 2016, 2:16 PM
spatel added a comment.May 26 2016, 2:57 PM

Ping.

RKSimon edited edge metadata.May 27 2016, 5:12 AM

Do we have a similar issue with Intel syntax?

spatel added a comment.May 27 2016, 6:42 AM
In D20385#442104, @RKSimon wrote:

Do we have a similar issue with Intel syntax?

We would, except that we don't print any comments at all for Intel syntax. :)
I can make that a TODO / follow-up.

RKSimon accepted this revision.May 27 2016, 7:08 AM
RKSimon edited edge metadata.
In D20385#442168, @spatel wrote:
In D20385#442104, @RKSimon wrote:

Do we have a similar issue with Intel syntax?

We would, except that we don't print any comments at all for Intel syntax. :)
I can make that a TODO / follow-up.

OK - please can you raise a bugzilla about improving intel assembly comments (and reference this patch)?

LGTM.

This revision is now accepted and ready to land.May 27 2016, 7:08 AM
spatel added a comment.May 27 2016, 2:30 PM
In D20385#442194, @RKSimon wrote:

OK - please can you raise a bugzilla about improving intel assembly comments (and reference this patch)?

https://llvm.org/bugs/show_bug.cgi?id=27916

Closed by commit rL271114: [x86] avoid printing unnecessary sign bits of hex immediates in asm comments… (authored by spatel). · Explain WhyMay 28 2016, 8:05 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
X86/
InstPrinter/
12 lines
test/
CodeGen/
X86/
2 lines
2 lines
2 lines
2 lines
4 lines
4 lines
4 lines
64 lines
MC/
X86/
4 lines

Diff 57676

lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Linesvoid X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
} else if (Op.isImm()) { } else if (Op.isImm()) {
// Print X86 immediates as signed values. // Print X86 immediates as signed values.
int64_t Imm = Op.getImm(); int64_t Imm = Op.getImm();
O << markup("<imm:") << '$' << formatImm(Imm) << markup(">"); O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
// If there are no instruction-specific comments, add a comment clarifying // If there are no instruction-specific comments, add a comment clarifying
// the hex value of the immediate operand when it isn't in the range // the hex value of the immediate operand when it isn't in the range
// [-256,255]. // [-256,255].
if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
// Don't print unnecessary hex sign bits.
if (Imm == (int16_t)(Imm))
*CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
else if (Imm == (int32_t)(Imm))
*CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
else
*CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm); *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
}
} else { } else {
assert(Op.isExpr() && "unknown operand kind in printOperand"); assert(Op.isExpr() && "unknown operand kind in printOperand");
O << markup("<imm:") << '$'; O << markup("<imm:") << '$';
Op.getExpr()->print(O, &MAI); Op.getExpr()->print(O, &MAI);
O << markup(">"); O << markup(">");
} }
} }
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

test/CodeGen/X86/2011-10-21-widen-cmp.ll

Show All 36 Linesentry:
%1 = select <2 x i1> %0, <2 x double> undef, <2 x double> undef %1 = select <2 x i1> %0, <2 x double> undef, <2 x double> undef
store <2 x double> %1, <2 x double>* undef store <2 x double> %1, <2 x double>* undef
ret void ret void
} }
define void @mp_11193(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET) nounwind { define void @mp_11193(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET) nounwind {
; CHECK-LABEL: mp_11193: ; CHECK-LABEL: mp_11193:
; CHECK: # BB#0: # %allocas ; CHECK: # BB#0: # %allocas
; CHECK-NEXT: movl $-1082130432, (%rsi) # imm = 0xFFFFFFFFBF800000 ; CHECK-NEXT: movl $-1082130432, (%rsi) # imm = 0xBF800000
; CHECK-NEXT: retq ; CHECK-NEXT: retq
allocas: allocas:
%bincmp = fcmp olt <8 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 9.000000e+00, float 1.000000e+00, float 9.000000e+00, float 1.000000e+00> , <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00> %bincmp = fcmp olt <8 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 9.000000e+00, float 1.000000e+00, float 9.000000e+00, float 1.000000e+00> , <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
%t = extractelement <8 x i1> %bincmp, i32 0 %t = extractelement <8 x i1> %bincmp, i32 0
%ft = sitofp i1 %t to float %ft = sitofp i1 %t to float
%pp = bitcast <8 x float>* %RET to float* %pp = bitcast <8 x float>* %RET to float*
store float %ft, float* %pp store float %ft, float* %pp
ret void ret void
} }

test/CodeGen/X86/avx512-cmp.ll

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
} }
define i32 @test8(i32 %a1, i32 %a2, i32 %a3) { define i32 @test8(i32 %a1, i32 %a2, i32 %a3) {
; ALL-LABEL: test8: ; ALL-LABEL: test8:
; ALL: ## BB#0: ; ALL: ## BB#0:
; ALL-NEXT: testl %edx, %edx ; ALL-NEXT: testl %edx, %edx
; ALL-NEXT: movl $1, %eax ; ALL-NEXT: movl $1, %eax
; ALL-NEXT: cmovel %eax, %edx ; ALL-NEXT: cmovel %eax, %edx
; ALL-NEXT: cmpl $-2147483648, %esi ## imm = 0xFFFFFFFF80000000 ; ALL-NEXT: cmpl $-2147483648, %esi ## imm = 0x80000000
; ALL-NEXT: cmovnel %edx, %eax ; ALL-NEXT: cmovnel %edx, %eax
; ALL-NEXT: cmpl $-1, %edi ; ALL-NEXT: cmpl $-1, %edi
; ALL-NEXT: cmovnel %edx, %eax ; ALL-NEXT: cmovnel %edx, %eax
; ALL-NEXT: retq ; ALL-NEXT: retq
%tmp1 = icmp eq i32 %a1, -1 %tmp1 = icmp eq i32 %a1, -1
%tmp2 = icmp eq i32 %a2, -2147483648 %tmp2 = icmp eq i32 %a2, -2147483648
%tmp3 = and i1 %tmp1, %tmp2 %tmp3 = and i1 %tmp1, %tmp2
%tmp4 = icmp eq i32 %a3, 0 %tmp4 = icmp eq i32 %a3, 0
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

test/CodeGen/X86/bitreverse.ll

Show All 20 Lines; CHECK: shlb
ret i8 %b ret i8 %b
} }
; These tests check that bitreverse(constant) calls are folded ; These tests check that bitreverse(constant) calls are folded
define <2 x i16> @fold_v2i16() { define <2 x i16> @fold_v2i16() {
; CHECK-LABEL: fold_v2i16: ; CHECK-LABEL: fold_v2i16:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movw $-4096, %ax # imm = 0xFFFFFFFFFFFFF000 ; CHECK-NEXT: movw $-4096, %ax # imm = 0xF000
; CHECK-NEXT: movw $240, %dx ; CHECK-NEXT: movw $240, %dx
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> <i16 15, i16 3840>) %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> <i16 15, i16 3840>)
ret <2 x i16> %b ret <2 x i16> %b
} }
define i8 @fold_i8() { define i8 @fold_i8() {
; CHECK-LABEL: fold_i8: ; CHECK-LABEL: fold_i8:
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

test/CodeGen/X86/pr16360.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s ; RUN: llc < %s -mtriple=i686-pc-linux | FileCheck %s
define i64 @foo(i32 %sum) { define i64 @foo(i32 %sum) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # BB#0: # %entry ; CHECK: # BB#0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: shrl $2, %eax ; CHECK-NEXT: shrl $2, %eax
; CHECK-NEXT: orl $-67108864, %eax # imm = 0xFFFFFFFFFC000000 ; CHECK-NEXT: orl $-67108864, %eax # imm = 0xFC000000
; CHECK-NEXT: movl $1073741823, %edx # imm = 0x3FFFFFFF ; CHECK-NEXT: movl $1073741823, %edx # imm = 0x3FFFFFFF
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%conv = sext i32 %sum to i64 %conv = sext i32 %sum to i64
%shr = lshr i64 %conv, 2 %shr = lshr i64 %conv, 2
%or = or i64 4611686018360279040, %shr %or = or i64 4611686018360279040, %shr
ret i64 %or ret i64 %or
} }

test/CodeGen/X86/rem.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
define i32 @test1(i32 %X) { define i32 @test1(i32 %X) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl $-2139062143, %edx # imm = 0xFFFFFFFF80808081 ; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: imull %edx ; CHECK-NEXT: imull %edx
; CHECK-NEXT: addl %ecx, %edx ; CHECK-NEXT: addl %ecx, %edx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shrl $31, %eax ; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $7, %edx ; CHECK-NEXT: sarl $7, %edx
; CHECK-NEXT: addl %eax, %edx ; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
Show All 22 Lines;
%tmp1 = srem i32 %X, 256 %tmp1 = srem i32 %X, 256
ret i32 %tmp1 ret i32 %tmp1
} }
define i32 @test3(i32 %X) { define i32 @test3(i32 %X) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl $-2139062143, %edx # imm = 0xFFFFFFFF80808081 ; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: mull %edx ; CHECK-NEXT: mull %edx
; CHECK-NEXT: shrl $7, %edx ; CHECK-NEXT: shrl $7, %edx
; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shll $8, %eax ; CHECK-NEXT: shll $8, %eax
; CHECK-NEXT: subl %edx, %eax ; CHECK-NEXT: subl %edx, %eax
; CHECK-NEXT: subl %eax, %ecx ; CHECK-NEXT: subl %eax, %ecx
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
Show All 29 Lines

test/CodeGen/X86/vec_fneg.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
define <2 x float> @fneg_bitcast(i64 %i) nounwind { define <2 x float> @fneg_bitcast(i64 %i) nounwind {
; X32-SSE1-LABEL: fneg_bitcast: ; X32-SSE1-LABEL: fneg_bitcast:
; X32-SSE1: # BB#0: ; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: pushl %ebp ; X32-SSE1-NEXT: pushl %ebp
; X32-SSE1-NEXT: movl %esp, %ebp ; X32-SSE1-NEXT: movl %esp, %ebp
; X32-SSE1-NEXT: andl $-16, %esp ; X32-SSE1-NEXT: andl $-16, %esp
; X32-SSE1-NEXT: subl $32, %esp ; X32-SSE1-NEXT: subl $32, %esp
; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0xFFFFFFFF80000000 ; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X32-SSE1-NEXT: movl 12(%ebp), %ecx ; X32-SSE1-NEXT: movl 12(%ebp), %ecx
; X32-SSE1-NEXT: xorl %eax, %ecx ; X32-SSE1-NEXT: xorl %eax, %ecx
; X32-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X32-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X32-SSE1-NEXT: xorl 8(%ebp), %eax ; X32-SSE1-NEXT: xorl 8(%ebp), %eax
; X32-SSE1-NEXT: movl %eax, (%esp) ; X32-SSE1-NEXT: movl %eax, (%esp)
; X32-SSE1-NEXT: movaps (%esp), %xmm0 ; X32-SSE1-NEXT: movaps (%esp), %xmm0
; X32-SSE1-NEXT: movl %ebp, %esp ; X32-SSE1-NEXT: movl %ebp, %esp
; X32-SSE1-NEXT: popl %ebp ; X32-SSE1-NEXT: popl %ebp
; X32-SSE1-NEXT: retl ; X32-SSE1-NEXT: retl
; ;
; X32-SSE2-LABEL: fneg_bitcast: ; X32-SSE2-LABEL: fneg_bitcast:
; X32-SSE2: # BB#0: ; X32-SSE2: # BB#0:
; X32-SSE2-NEXT: movl $-2147483648, %eax # imm = 0xFFFFFFFF80000000 ; X32-SSE2-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-SSE2-NEXT: xorl %eax, %ecx ; X32-SSE2-NEXT: xorl %eax, %ecx
; X32-SSE2-NEXT: xorl {{[0-9]+}}(%esp), %eax ; X32-SSE2-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X32-SSE2-NEXT: movd %eax, %xmm1 ; X32-SSE2-NEXT: movd %eax, %xmm1
; X32-SSE2-NEXT: movd %ecx, %xmm0 ; X32-SSE2-NEXT: movd %ecx, %xmm0
; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X32-SSE2-NEXT: retl ; X32-SSE2-NEXT: retl
; ;
Show All 18 Lines

test/CodeGen/X86/vector-bitreverse.ll

Show First 20 Lines • Show All 609 Lines • ▼ Show 20 Lines
; SSE-NEXT: orq %rdx, %rsi ; SSE-NEXT: orq %rdx, %rsi
; SSE-NEXT: movq %rdi, %rdx ; SSE-NEXT: movq %rdi, %rdx
; SSE-NEXT: andq $1073741824, %rdx # imm = 0x40000000 ; SSE-NEXT: andq $1073741824, %rdx # imm = 0x40000000
; SSE-NEXT: shlq $3, %rdx ; SSE-NEXT: shlq $3, %rdx
; SSE-NEXT: orq %rsi, %rdx ; SSE-NEXT: orq %rsi, %rdx
; SSE-NEXT: orq %rcx, %rdx ; SSE-NEXT: orq %rcx, %rdx
; SSE-NEXT: movq %rdi, %rcx ; SSE-NEXT: movq %rdi, %rcx
; SSE-NEXT: shrq %rcx ; SSE-NEXT: shrq %rcx
; SSE-NEXT: andl $-2147483648, %ecx # imm = 0xFFFFFFFF80000000 ; SSE-NEXT: andl $-2147483648, %ecx # imm = 0x80000000
; SSE-NEXT: orq %rdx, %rcx ; SSE-NEXT: orq %rdx, %rcx
; SSE-NEXT: movq %rdi, %rdx ; SSE-NEXT: movq %rdi, %rdx
; SSE-NEXT: shrq $3, %rdx ; SSE-NEXT: shrq $3, %rdx
; SSE-NEXT: andl $1073741824, %edx # imm = 0x40000000 ; SSE-NEXT: andl $1073741824, %edx # imm = 0x40000000
; SSE-NEXT: orq %rcx, %rdx ; SSE-NEXT: orq %rcx, %rdx
; SSE-NEXT: movq %rdi, %rcx ; SSE-NEXT: movq %rdi, %rcx
; SSE-NEXT: shrq $5, %rcx ; SSE-NEXT: shrq $5, %rcx
; SSE-NEXT: andl $536870912, %ecx # imm = 0x20000000 ; SSE-NEXT: andl $536870912, %ecx # imm = 0x20000000
▲ Show 20 Lines • Show All 239 Lines • ▼ Show 20 Lines
; AVX-NEXT: orq %rdx, %rsi ; AVX-NEXT: orq %rdx, %rsi
; AVX-NEXT: movq %rdi, %rdx ; AVX-NEXT: movq %rdi, %rdx
; AVX-NEXT: andq $1073741824, %rdx # imm = 0x40000000 ; AVX-NEXT: andq $1073741824, %rdx # imm = 0x40000000
; AVX-NEXT: shlq $3, %rdx ; AVX-NEXT: shlq $3, %rdx
; AVX-NEXT: orq %rsi, %rdx ; AVX-NEXT: orq %rsi, %rdx
; AVX-NEXT: orq %rcx, %rdx ; AVX-NEXT: orq %rcx, %rdx
; AVX-NEXT: movq %rdi, %rcx ; AVX-NEXT: movq %rdi, %rcx
; AVX-NEXT: shrq %rcx ; AVX-NEXT: shrq %rcx
; AVX-NEXT: andl $-2147483648, %ecx # imm = 0xFFFFFFFF80000000 ; AVX-NEXT: andl $-2147483648, %ecx # imm = 0x80000000
; AVX-NEXT: orq %rdx, %rcx ; AVX-NEXT: orq %rdx, %rcx
; AVX-NEXT: movq %rdi, %rdx ; AVX-NEXT: movq %rdi, %rdx
; AVX-NEXT: shrq $3, %rdx ; AVX-NEXT: shrq $3, %rdx
; AVX-NEXT: andl $1073741824, %edx # imm = 0x40000000 ; AVX-NEXT: andl $1073741824, %edx # imm = 0x40000000
; AVX-NEXT: orq %rcx, %rdx ; AVX-NEXT: orq %rcx, %rdx
; AVX-NEXT: movq %rdi, %rcx ; AVX-NEXT: movq %rdi, %rcx
; AVX-NEXT: shrq $5, %rcx ; AVX-NEXT: shrq $5, %rcx
; AVX-NEXT: andl $536870912, %ecx # imm = 0x20000000 ; AVX-NEXT: andl $536870912, %ecx # imm = 0x20000000
▲ Show 20 Lines • Show All 1,779 Lines • Show Last 20 Lines

test/CodeGen/X86/vector-idiv-sdiv-512.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
} }
define <16 x i32> @test_div7_16i32(<16 x i32> %a) nounwind { define <16 x i32> @test_div7_16i32(<16 x i32> %a) nounwind {
; AVX-LABEL: test_div7_16i32: ; AVX-LABEL: test_div7_16i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; AVX-NEXT: vpextrd $1, %xmm1, %eax ; AVX-NEXT: vpextrd $1, %xmm1, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vmovd %xmm1, %ecx ; AVX-NEXT: vmovd %xmm1, %ecx
; AVX-NEXT: movslq %ecx, %rcx ; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm2 ; AVX-NEXT: vmovd %ecx, %xmm2
; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 ; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $2, %xmm1, %eax ; AVX-NEXT: vpextrd $2, %xmm1, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 ; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $3, %xmm1, %eax ; AVX-NEXT: vpextrd $3, %xmm1, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1 ; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2 ; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax ; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx ; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: movslq %ecx, %rcx ; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3 ; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax ; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax ; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2 ; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti32x4 $1, %zmm0, %xmm2 ; AVX-NEXT: vextracti32x4 $1, %zmm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax ; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx ; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: movslq %ecx, %rcx ; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3 ; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax ; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax ; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2 ; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vpextrd $1, %xmm0, %eax ; AVX-NEXT: vpextrd $1, %xmm0, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vmovd %xmm0, %ecx ; AVX-NEXT: vmovd %xmm0, %ecx
; AVX-NEXT: movslq %ecx, %rcx ; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3 ; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm0, %eax ; AVX-NEXT: vpextrd $2, %xmm0, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm0, %eax ; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0 ; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 ; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
▲ Show 20 Lines • Show All 905 Lines • ▼ Show 20 Lines
} }
define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind { define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind {
; AVX-LABEL: test_rem7_16i32: ; AVX-LABEL: test_rem7_16i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1
; AVX-NEXT: vpextrd $1, %xmm1, %eax ; AVX-NEXT: vpextrd $1, %xmm1, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vmovd %xmm1, %ecx ; AVX-NEXT: vmovd %xmm1, %ecx
; AVX-NEXT: movslq %ecx, %rcx ; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %ecx, %edx ; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: movl %edx, %esi ; AVX-NEXT: movl %edx, %esi
; AVX-NEXT: shrl $31, %esi ; AVX-NEXT: shrl $31, %esi
; AVX-NEXT: sarl $2, %edx ; AVX-NEXT: sarl $2, %edx
; AVX-NEXT: addl %esi, %edx ; AVX-NEXT: addl %esi, %edx
; AVX-NEXT: leal (,%rdx,8), %esi ; AVX-NEXT: leal (,%rdx,8), %esi
; AVX-NEXT: subl %edx, %esi ; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: subl %esi, %ecx ; AVX-NEXT: subl %esi, %ecx
; AVX-NEXT: vmovd %ecx, %xmm2 ; AVX-NEXT: vmovd %ecx, %xmm2
; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2 ; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $2, %xmm1, %eax ; AVX-NEXT: vpextrd $2, %xmm1, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2 ; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $3, %xmm1, %eax ; AVX-NEXT: vpextrd $3, %xmm1, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1 ; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2 ; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax ; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx ; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: movslq %ecx, %rcx ; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %ecx, %edx ; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: movl %edx, %esi ; AVX-NEXT: movl %edx, %esi
; AVX-NEXT: shrl $31, %esi ; AVX-NEXT: shrl $31, %esi
; AVX-NEXT: sarl $2, %edx ; AVX-NEXT: sarl $2, %edx
; AVX-NEXT: addl %esi, %edx ; AVX-NEXT: addl %esi, %edx
; AVX-NEXT: leal (,%rdx,8), %esi ; AVX-NEXT: leal (,%rdx,8), %esi
; AVX-NEXT: subl %edx, %esi ; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: subl %esi, %ecx ; AVX-NEXT: subl %esi, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3 ; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax ; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax ; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2 ; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti32x4 $1, %zmm0, %xmm2 ; AVX-NEXT: vextracti32x4 $1, %zmm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax ; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx ; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: movslq %ecx, %rcx ; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %ecx, %edx ; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: movl %edx, %esi ; AVX-NEXT: movl %edx, %esi
; AVX-NEXT: shrl $31, %esi ; AVX-NEXT: shrl $31, %esi
; AVX-NEXT: sarl $2, %edx ; AVX-NEXT: sarl $2, %edx
; AVX-NEXT: addl %esi, %edx ; AVX-NEXT: addl %esi, %edx
; AVX-NEXT: leal (,%rdx,8), %esi ; AVX-NEXT: leal (,%rdx,8), %esi
; AVX-NEXT: subl %edx, %esi ; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: subl %esi, %ecx ; AVX-NEXT: subl %esi, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3 ; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax ; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax ; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2 ; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vpextrd $1, %xmm0, %eax ; AVX-NEXT: vpextrd $1, %xmm0, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vmovd %xmm0, %ecx ; AVX-NEXT: vmovd %xmm0, %ecx
; AVX-NEXT: movslq %ecx, %rcx ; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %ecx, %edx ; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: movl %edx, %esi ; AVX-NEXT: movl %edx, %esi
; AVX-NEXT: shrl $31, %esi ; AVX-NEXT: shrl $31, %esi
; AVX-NEXT: sarl $2, %edx ; AVX-NEXT: sarl $2, %edx
; AVX-NEXT: addl %esi, %edx ; AVX-NEXT: addl %esi, %edx
; AVX-NEXT: leal (,%rdx,8), %esi ; AVX-NEXT: leal (,%rdx,8), %esi
; AVX-NEXT: subl %edx, %esi ; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: subl %esi, %ecx ; AVX-NEXT: subl %esi, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3 ; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm0, %eax ; AVX-NEXT: vpextrd $2, %xmm0, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3 ; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm0, %eax ; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: cltq ; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0xFFFFFFFF92492493 ; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: subl %ecx, %edx
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test/MC/X86/imm-comments.s

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movabsq $9223372036854775807, %rax movabsq $9223372036854775807, %rax
movabsq $-9223372036854775808, %rax movabsq $-9223372036854775808, %rax
# CHECK: movb $127, %al # CHECK: movb $127, %al
# CHECK: movb $-128, %al # CHECK: movb $-128, %al
# CHECK: movw $32767, %ax # imm = 0x7FFF # CHECK: movw $32767, %ax # imm = 0x7FFF
# CHECK: movw $-32768, %ax # imm = 0xFFFFFFFFFFFF8000 # CHECK: movw $-32768, %ax # imm = 0x8000
# CHECK: movl $2147483647, %eax # imm = 0x7FFFFFFF # CHECK: movl $2147483647, %eax # imm = 0x7FFFFFFF
# CHECK: movl $-2147483648, %eax # imm = 0xFFFFFFFF80000000 # CHECK: movl $-2147483648, %eax # imm = 0x80000000
# CHECK: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF # CHECK: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
# CHECK: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 # CHECK: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000