Implement RAS extensions for ARMv8.2-A

[rogfer01]

Summary

RAS extensions are part of ARMv8.2-A. This change enables them by introducing a
new instruction to ARM and AArch64 targets and several system registers.

[t.p.northover]

This mostly looks reasonable, just one consistency niggle with the naming:

include/llvm/Support/ARMTargetParser.def

127 ↗

(On Diff #57330)

I'd just use "+/-ras". The "ext" is a bit redundant.

[rogfer01]

include/llvm/Support/ARMTargetParser.def

127 ↗

(On Diff #57330)

Unfortunately "ras" is already taken for an unrelated thing in the ARM target. And it seems to conflict with this. Doable but I'm afraid the patch will be slightly noisier.

[rogfer01]

Changed +/-rasext to +/-ras. Also rename unrelated existing "ras" feature in ARM target to something more descriptive.

[rogfer01]

Ping?

Thanks

[t.p.northover]

Bother, forgot to hit submit...

Thanks for updating the patch. I think it's an improvement, both are pretty short names but at least the new RAS has documentary support. LGTM!

[rogfer01]

This is just the same patch updated against the current trunk

llvm/trunk/include/llvm/Support/ARMTargetParser.def

ARM_ARCH("armv7-m", AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7,
           FK_NONE, ARM::AEK_HWDIV)
 ARM_ARCH("armv7e-m", AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M,
           FK_NONE, (ARM::AEK_HWDIV | ARM::AEK_DSP))
 ARM_ARCH("armv8-a", AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8_A,
           FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
 ARM_ARCH("armv8.1-a", AK_ARMV8_1A, "8.1-A", "v8.1a", ARMBuildAttrs::CPUArch::v8_A,
           FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                             ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
+                             ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS))
 ARM_ARCH("armv8.2-a", AK_ARMV8_2A, "8.2-A", "v8.2a", ARMBuildAttrs::CPUArch::v8_A,
           FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIV | ARM::AEK_DSP | ARM::AEK_CRC))
 ARM_ARCH("armv8-m.base", AK_ARMV8MBaseline, "8-M.Baseline", "v8m.base",
           ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIV)
 ARM_ARCH("armv8-m.main", AK_ARMV8MMainline, "8-M.Mainline", "v8m.main",
           ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIV)
 // Non-standard Arch names.

 ARM_ARCH_EXT_NAME("dsp",      ARM::AEK_DSP,      "+dsp",   "-dsp")
 ARM_ARCH_EXT_NAME("fp",       ARM::AEK_FP,       nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("idiv",     (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV), nullptr, nullptr)
 ARM_ARCH_EXT_NAME("mp",       ARM::AEK_MP,       nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("simd",     ARM::AEK_SIMD,     nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("sec",      ARM::AEK_SEC,      nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("virt",     ARM::AEK_VIRT,     nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("fp16",     ARM::AEK_FP16,     "+fullfp16",  "-fullfp16")
+ARM_ARCH_EXT_NAME("ras",      ARM::AEK_RAS,      "+ras", "-ras")
 ARM_ARCH_EXT_NAME("os",       ARM::AEK_OS,       nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("iwmmxt",   ARM::AEK_IWMMXT,   nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("iwmmxt2",  ARM::AEK_IWMMXT2,  nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr,  nullptr)
 ARM_ARCH_EXT_NAME("xscale",   ARM::AEK_XSCALE,   nullptr,  nullptr)
 #undef ARM_ARCH_EXT_NAME
 
 #ifndef ARM_HW_DIV_NAME

llvm/trunk/include/llvm/Support/TargetParser.h

enum ArchExtKind : unsigned {
   AEK_HWDIV = 0x10,
   AEK_HWDIVARM = 0x20,
   AEK_MP = 0x40,
   AEK_SIMD = 0x80,
   AEK_SEC = 0x100,
   AEK_VIRT = 0x200,
   AEK_DSP = 0x400,
   AEK_FP16 = 0x800,
+  AEK_RAS = 0x1000,
   // Unsupported extensions.
   AEK_OS = 0x8000000,
   AEK_IWMMXT = 0x10000000,
   AEK_IWMMXT2 = 0x20000000,
   AEK_MAVERICK = 0x40000000,
   AEK_XSCALE = 0x80000000,
 };
 

llvm/trunk/lib/Target/AArch64/AArch64.td

def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
 
 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
   "Enable cryptographic instructions">;
 
 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
   "Enable ARMv8 CRC-32 checksum instructions">;
 
+def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
+  "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
+
 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
   "Enable ARMv8 PMUv3 Performance Monitors extension">;
 
 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
   "Full FP16", [FeatureFPARMv8]>;
 
 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
   "Enable Statistical Profiling extension">;

 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC]>;
 
 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
-  "Support ARM v8.2a instructions", [HasV8_1aOps]>;
+  "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AArch64RegisterInfo.td"
 include "AArch64CallingConvention.td"
 

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

 def HasFPARMv8       : Predicate<"Subtarget->hasFPARMv8()">,
                                AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
 def HasNEON          : Predicate<"Subtarget->hasNEON()">,
                                  AssemblerPredicate<"FeatureNEON", "neon">;
 def HasCrypto        : Predicate<"Subtarget->hasCrypto()">,
                                  AssemblerPredicate<"FeatureCrypto", "crypto">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
                                  AssemblerPredicate<"FeatureCRC", "crc">;
+def HasRAS           : Predicate<"Subtarget->hasRAS()">,
+                                 AssemblerPredicate<"FeatureRAS", "ras">;
 def HasPerfMon       : Predicate<"Subtarget->hasPerfMon()">;
 def HasFullFP16      : Predicate<"Subtarget->hasFullFP16()">,
                                  AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
 def HasSPE           : Predicate<"Subtarget->hasSPE()">,
                                  AssemblerPredicate<"FeatureSPE", "spe">;
 
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;

 
 def HINT : HintI<"hint">;
 def : InstAlias<"nop",  (HINT 0b000)>;
 def : InstAlias<"yield",(HINT 0b001)>;
 def : InstAlias<"wfe",  (HINT 0b010)>;
 def : InstAlias<"wfi",  (HINT 0b011)>;
 def : InstAlias<"sev",  (HINT 0b100)>;
 def : InstAlias<"sevl", (HINT 0b101)>;
+def : InstAlias<"esb",  (HINT 0b10000)>, Requires<[HasRAS]>;
 
 // v8.2a Statistical Profiling extension
 def : InstAlias<"psb $op",  (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
 
 // As far as LLVM is concerned this writes to the system's exclusive monitors.
 let mayLoad = 1, mayStore = 1 in
 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
 

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

protected:
 
   bool HasV8_1aOps = false;
   bool HasV8_2aOps = false;
 
   bool HasFPARMv8 = false;
   bool HasNEON = false;
   bool HasCrypto = false;
   bool HasCRC = false;
+  bool HasRAS = false;
   bool HasPerfMon = false;
   bool HasFullFP16 = false;
   bool HasSPE = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
 
   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
public:
 
   bool requiresStrictAlign() const { return StrictAlign; }
 
   bool isX18Reserved() const { return ReserveX18; }
   bool hasFPARMv8() const { return HasFPARMv8; }
   bool hasNEON() const { return HasNEON; }
   bool hasCrypto() const { return HasCrypto; }
   bool hasCRC() const { return HasCRC; }
+  bool hasRAS() const { return HasRAS; }
   bool mergeNarrowLoads() const { return MergeNarrowLoads; }
   bool balanceFPOps() const { return BalanceFPOps; }
   bool predictableSelectIsExpensive() const {
     return PredictableSelectIsExpensive;
   }
   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
   bool avoidQuadLdStPairs() const { return AvoidQuadLdStPairs; }

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h

enum SysRegROValues {
     // GICv3 registers
     ICC_IAR1_EL1      = 0xc660, // 11  000  1100  1100  000
     ICC_IAR0_EL1      = 0xc640, // 11  000  1100  1000  000
     ICC_HPPIR1_EL1    = 0xc662, // 11  000  1100  1100  010
     ICC_HPPIR0_EL1    = 0xc642, // 11  000  1100  1000  010
     ICC_RPR_EL1       = 0xc65b, // 11  000  1100  1011  011
     ICH_VTR_EL2       = 0xe659, // 11  100  1100  1011  001
     ICH_EISR_EL2      = 0xe65b, // 11  100  1100  1011  011
-    ICH_ELSR_EL2      = 0xe65d  // 11  100  1100  1011  101
+    ICH_ELSR_EL2      = 0xe65d, // 11  100  1100  1011  101
+
+    // RAS extension registers
+    ERRIDR_EL1        = 0xc298, // 11  000  0101  0011  000
+    ERXFR_EL1         = 0xc2a0  // 11  000  0101  0100  000
   };
 
   enum SysRegWOValues {
     DBGDTRTX_EL0      = 0x9828, // 10  011  0000  0101  000
     OSLAR_EL1         = 0x8084, // 10  000  0001  0000  100
     PMSWINC_EL0       = 0xdce4,  // 11  011  1001  1100  100
 
     // Trace Registers
enum SysRegValues {
     CNTP_CTL_EL02     = 0xef11, // 11  101  1110  0010  001
     CNTP_CVAL_EL02    = 0xef12, // 11  101  1110  0010  010
     CNTV_TVAL_EL02    = 0xef18, // 11  101  1110  0011  000
     CNTV_CTL_EL02     = 0xef19, // 11  101  1110  0011  001
     CNTV_CVAL_EL02    = 0xef1a, // 11  101  1110  0011  010
     SPSR_EL12         = 0xea00, // 11  101  0100  0000  000
     ELR_EL12          = 0xea01, // 11  101  0100  0000  001
 
+    // RAS extension registers
+    ERRSELR_EL1       = 0xc299, // 11  000  0101  0011  001
+    ERXCTLR_EL1       = 0xc2a1, // 11  000  0101  0100  001
+    ERXSTATUS_EL1     = 0xc2a2, // 11  000  0101  0100  010
+    ERXADDR_EL1       = 0xc2a3, // 11  000  0101  0100  011
+    ERXMISC0_EL1      = 0xc2a8, // 11  000  0101  0101  000
+    ERXMISC1_EL1      = 0xc2a9, // 11  000  0101  0101  001
+    DISR_EL1          = 0xc609, // 11  000  1100  0001  001
+    VDISR_EL2         = 0xe609, // 11  100  1100  0001  001
+    VSESR_EL2         = 0xe293, // 11  100  0101  0010  011
+
     // v8.2a registers
     UAO               = 0xc214, // 11  000  0100  0010  100
 
     // v8.2a "Statistical Profiling extension" registers
     PMBLIMITR_EL1     = 0xc4d0, // 11  000  1001  1010  000
     PMBPTR_EL1        = 0xc4d1, // 11  000  1001  1010  001
     PMBSR_EL1         = 0xc4d3, // 11  000  1001  1010  011
     PMBIDR_EL1        = 0xc4d7, // 11  000  1001  1010  111

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
   {"icc_hppir0_el1", ICC_HPPIR0_EL1, {}},
   {"icc_rpr_el1", ICC_RPR_EL1, {}},
   {"ich_vtr_el2", ICH_VTR_EL2, {}},
   {"ich_eisr_el2", ICH_EISR_EL2, {}},
   {"ich_elsr_el2", ICH_ELSR_EL2, {}},
 
   // v8.1a "Limited Ordering Regions" extension-specific system registers
   {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}},
+
+  // v8.2a "Reliability, Availability and Serviceability" extensions registers
+  {"erridr_el1", ERRIDR_EL1, {AArch64::FeatureRAS}},
+  {"erxfr_el1", ERXFR_EL1, {AArch64::FeatureRAS}}
 };
 
 AArch64SysReg::MRSMapper::MRSMapper() {
     InstMappings = &MRSMappings[0];
     NumInstMappings = llvm::array_lengthof(MRSMappings);
 }
 
 const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = {
const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
   {"cntv_ctl_el02", CNTV_CTL_EL02, {AArch64::HasV8_1aOps}},
   {"cntv_cval_el02", CNTV_CVAL_EL02, {AArch64::HasV8_1aOps}},
   {"spsr_el12", SPSR_EL12, {AArch64::HasV8_1aOps}},
   {"elr_el12", ELR_EL12, {AArch64::HasV8_1aOps}},
 
   // v8.2a registers
   {"uao",           UAO,           {AArch64::HasV8_2aOps}},
 
+  // v8.2a "Reliability, Availability and Serviceability" extensions registers
+  {"errselr_el1",   ERRSELR_EL1,   {AArch64::FeatureRAS}},
+  {"erxctlr_el1",   ERXCTLR_EL1,   {AArch64::FeatureRAS}},
+  {"erxstatus_el1", ERXSTATUS_EL1, {AArch64::FeatureRAS}},
+  {"erxaddr_el1",   ERXADDR_EL1,   {AArch64::FeatureRAS}},
+  {"erxmisc0_el1",  ERXMISC0_EL1,  {AArch64::FeatureRAS}},
+  {"erxmisc1_el1",  ERXMISC1_EL1,  {AArch64::FeatureRAS}},
+  {"disr_el1",      DISR_EL1,      {AArch64::FeatureRAS}},
+  {"vdisr_el2",     VDISR_EL2,     {AArch64::FeatureRAS}},
+  {"vsesr_el2",     VSESR_EL2,     {AArch64::FeatureRAS}},
+
   // v8.2a "Statistical Profiling extension" registers
   {"pmblimitr_el1", PMBLIMITR_EL1, {AArch64::FeatureSPE}},
   {"pmbptr_el1",    PMBPTR_EL1,    {AArch64::FeatureSPE}},
   {"pmbsr_el1",     PMBSR_EL1,     {AArch64::FeatureSPE}},
   {"pmbidr_el1",    PMBIDR_EL1,    {AArch64::FeatureSPE}},
   {"pmscr_el2",     PMSCR_EL2,     {AArch64::FeatureSPE}},
   {"pmscr_el12",    PMSCR_EL12,    {AArch64::FeatureSPE}},
   {"pmscr_el1",     PMSCR_EL1,     {AArch64::FeatureSPE}},

llvm/trunk/lib/Target/ARM/ARM.td

def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
                           "Enable support for TrustZone security extensions">;
 def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
                           "Enable support for ARMv8-M Security Extensions">;
 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
                           "Enable support for Cryptography extensions",
                           [FeatureNEON]>;
 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
                           "Enable support for CRC instructions">;
+// Not to be confused with FeatureHasRetAddrStack (return address stack)
+def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
+                "Enable Reliability, Availability and Serviceability extensions">;
+
 
 // Cyclone has preferred instructions for zeroing VFP registers, which can
 // execute in 0 cycles.
 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
                                         "Has zero-cycle zeroing instructions">;
 
 // Some processors have FP multiply-accumulate instructions that don't
 // play nicely with other VFP / NEON instructions, and it's generally better
def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
                                  "Avoid CPSR partial update for OOO execution">;
 
 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
                                             "AvoidMOVsShifterOperand", "true",
                                 "Avoid movs instructions with shifter operand">;
 
 // Some processors perform return stack prediction. CodeGen should avoid issue
 // "normal" call instructions to callees which do not return.
-def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
+def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
                                      "Has return address stack">;
 
 /// DSP extension.
 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
                               "Supports DSP instructions in ARM and/or Thumb2">;
 
 // Multiprocessing extension.
 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
                                                        FeatureDB,
                                                        FeatureFPARMv8,
                                                        FeatureNEON,
                                                        FeatureDSP,
                                                        FeatureTrustZone,
                                                        FeatureMP,
                                                        FeatureVirtualization,
                                                        FeatureCrypto,
-                                                       FeatureCRC]>;
+                                                       FeatureCRC,
+                                                       FeatureRAS]>;
 
 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
                                                       [HasV8MBaselineOps,
                                                        FeatureNoARM,
                                                        FeatureDB,
                                                        FeatureHWDiv,
                                                        FeatureV7Clrex,
                                                        Feature8MSecExt,

 
 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
                                                          FeatureVFP2,
                                                          FeatureHasSlowFPVMLx]>;
 
 // FIXME: A5 has currently the same Schedule model as A8
 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureVMLxForwarding,
                                                          FeatureT2XtPk,
                                                          FeatureMP,
                                                          FeatureVFP4]>;
 
 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureVMLxForwarding,
                                                          FeatureT2XtPk,
                                                          FeatureMP,
                                                          FeatureVFP4,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureVirtualization]>;
 
 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureVMLxForwarding,
                                                          FeatureT2XtPk]>;
 
 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureVMLxForwarding,
                                                          FeatureT2XtPk,
                                                          FeatureFP16,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureMP]>;
 
 // FIXME: A12 has currently the same Schedule model as A9
 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureVMLxForwarding,
                                                          FeatureT2XtPk,
                                                          FeatureVFP4,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVirtualization,
                                                          FeatureMP]>;
 
 // FIXME: A15 has currently the same Schedule model as A9.
 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureT2XtPk,
                                                          FeatureVFP4,
                                                          FeatureMP,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVirtualization]>;
 
 // FIXME: A17 has currently the same Schedule model as A9
 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureTrustZone,
                                                          FeatureMP,
                                                          FeatureVMLxForwarding,
                                                          FeatureT2XtPk,
                                                          FeatureVFP4,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVirtualization]>;
 
 // FIXME: krait has currently the same Schedule model as A9
 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
 //        division features.
 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureVMLxForwarding,
                                                          FeatureT2XtPk,
                                                          FeatureFP16,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureVFP4,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM]>;
 
 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureNEONForFP,
                                                          FeatureT2XtPk,
                                                          FeatureVFP4,
                                                          FeatureMP,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureAvoidMOVsShOp,
                                                          FeatureHasSlowFPVMLx]>;
 
 // FIXME: R4 has currently the same ProcessorModel as A8.
 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureT2XtPk]>;
 
 // FIXME: R4F has currently the same ProcessorModel as A8.
 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureVFP3,
                                                          FeatureD16,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureT2XtPk]>;
 
 // FIXME: R5 has currently the same ProcessorModel as A8.
 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureVFP3,
                                                          FeatureD16,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHWDivARM,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureT2XtPk]>;
 
 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureVFP3,
                                                          FeatureD16,
                                                          FeatureFP16,
                                                          FeatureMP,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHWDivARM,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureT2XtPk]>;
 
 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureVFP3,
                                                          FeatureD16,
                                                          FeatureFP16,
                                                          FeatureMP,
                                                          FeatureSlowFPBrcc,
                                                          FeatureHWDivARM,
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureAvoidPartialCPSR,
def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureT2XtPk,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
 // Cyclone is very similar to swift
 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
-                                                         FeatureHasRAS,
+                                                         FeatureHasRetAddrStack,
                                                          FeatureNEONForFP,
                                                          FeatureT2XtPk,
                                                          FeatureVFP4,
                                                          FeatureMP,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureAvoidPartialCPSR,
                                                          FeatureAvoidMOVsShOp,

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   if (Subtarget->isThumb()) {
     if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
       CallOpc = ARMISD::CALL_NOLINK;
     else
       CallOpc = ARMISD::CALL;
   } else {
     if (!isDirect && !Subtarget->hasV5TOps())
       CallOpc = ARMISD::CALL_NOLINK;
-    else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
+    else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
              // Emit regular call when code size is the priority
              !MF.getFunction()->optForMinSize())
       // "mov lr, pc; b _foo" to avoid confusing the RSP
       CallOpc = ARMISD::CALL_NOLINK;
     else
       CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
   }
 

llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

 def HasFPARMv8       : Predicate<"Subtarget->hasFPARMv8()">,
                                  AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
 def HasNEON          : Predicate<"Subtarget->hasNEON()">,
                                  AssemblerPredicate<"FeatureNEON", "NEON">;
 def HasCrypto        : Predicate<"Subtarget->hasCrypto()">,
                                  AssemblerPredicate<"FeatureCrypto", "crypto">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
                                  AssemblerPredicate<"FeatureCRC", "crc">;
+def HasRAS           : Predicate<"Subtarget->hasRAS()">,
+                                 AssemblerPredicate<"FeatureRAS", "ras">;
 def HasFP16          : Predicate<"Subtarget->hasFP16()">,
                                  AssemblerPredicate<"FeatureFP16","half-float conversions">;
 def HasFullFP16      : Predicate<"Subtarget->hasFullFP16()">,
                                  AssemblerPredicate<"FeatureFullFP16","full half-float">;
 def HasDivide        : Predicate<"Subtarget->hasDivide()">,
                                  AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
 def HasDivideInARM   : Predicate<"Subtarget->hasDivideInARMMode()">,
                                  AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;

 }
 
 def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
               "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
            Requires<[IsARM, HasV6]> {
   bits<8> imm;
   let Inst{27-8} = 0b00110010000011110000;
   let Inst{7-0} = imm;
+  let DecoderMethod = "DecodeHINTInstruction";
 }
 
 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>;
 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
+def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>;
 
 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
              "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
   bits<4> Rd;
   bits<4> Rn;
   bits<4> Rm;
   let Inst{3-0} = Rm;
   let Inst{15-12} = Rd;

llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
   let Predicates = [IsThumb2, HasV8];
 }
+def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
+  let Predicates = [IsThumb2, HasRAS];
+}
+def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
+  let Predicates = [IsThumb2, HasRAS];
+}
 
 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
                 [(int_arm_dbg imm0_15:$opt)]> {
   bits<4> opt;
   let Inst{31-20} = 0b111100111010;
   let Inst{19-16} = 0b1111;
   let Inst{15-8} = 0b10000000;
   let Inst{7-4} = 0b1111;

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

protected:
   /// that partially update CPSR and add false dependency on the previous
   /// CPSR setting instruction.
   bool AvoidCPSRPartialUpdate;
 
   /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
   /// movs with shifter operand (i.e. asr, lsl, lsr).
   bool AvoidMOVsShifterOperand;
 
-  /// HasRAS - Some processors perform return stack prediction. CodeGen should
+  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
   /// avoid issue "normal" call instructions to callees which do not return.
-  bool HasRAS;
+  bool HasRetAddrStack;
 
   /// HasMPExtension - True if the subtarget supports Multiprocessing
   /// extension (ARMv7 only).
   bool HasMPExtension;
 
   /// HasVirtualization - True if the subtarget supports the Virtualization
   /// extension.
   bool HasVirtualization;
protected:
   bool Has8MSecExt;
 
   /// HasCrypto - if true, processor supports Cryptography extensions
   bool HasCrypto;
 
   /// HasCRC - if true, processor supports CRC instructions
   bool HasCRC;
 
+  /// HasRAS - if true, the processor supports RAS extensions
+  bool HasRAS;
+
   /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
   /// particularly effective at zeroing a VFP register.
   bool HasZeroCycleZeroing;
 
   /// StrictAlign - If true, the subtarget disallows unaligned memory
   /// accesses for some types.  For details, see
   /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
   bool StrictAlign;
public:
 
   bool hasVFP2() const { return HasVFPv2; }
   bool hasVFP3() const { return HasVFPv3; }
   bool hasVFP4() const { return HasVFPv4; }
   bool hasFPARMv8() const { return HasFPARMv8; }
   bool hasNEON() const { return HasNEON;  }
   bool hasCrypto() const { return HasCrypto; }
   bool hasCRC() const { return HasCRC; }
+  bool hasRAS() const { return HasRAS; }
   bool hasVirtualization() const { return HasVirtualization; }
   bool useNEONForSinglePrecisionFP() const {
     return hasNEON() && UseNEONForSinglePrecisionFP;
   }
 
   bool hasDivide() const { return HasHardwareDivide; }
   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
   bool hasT2ExtractPack() const { return HasT2ExtractPack; }
public:
   bool isFPOnlySP() const { return FPOnlySP; }
   bool hasPerfMon() const { return HasPerfMon; }
   bool hasTrustZone() const { return HasTrustZone; }
   bool has8MSecExt() const { return Has8MSecExt; }
   bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
   bool prefers32BitThumb() const { return Pref32BitThumb; }
   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
   bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
-  bool hasRAS() const { return HasRAS; }
+  bool hasRetAddrStack() const { return HasRetAddrStack; }
   bool hasMPExtension() const { return HasMPExtension; }
   bool hasDSP() const { return HasDSP; }
   bool useNaClTrap() const { return UseNaClTrap; }
   bool useSjLjEH() const { return UseSjLjEH; }
   bool genLongCalls() const { return GenLongCalls; }
 
   bool hasFP16() const { return HasFP16; }
   bool hasD16() const { return HasD16; }

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initializeEnvironment() {
   HasD16 = false;
   HasHardwareDivide = false;
   HasHardwareDivideInARM = false;
   HasT2ExtractPack = false;
   HasDataBarrier = false;
   Pref32BitThumb = false;
   AvoidCPSRPartialUpdate = false;
   AvoidMOVsShifterOperand = false;
-  HasRAS = false;
+  HasRetAddrStack = false;
   HasMPExtension = false;
   HasVirtualization = false;
   FPOnlySP = false;
   HasPerfMon = false;
   HasTrustZone = false;
   Has8MSecExt = false;
   HasCrypto = false;
   HasCRC = false;
+  HasRAS = false;
   HasZeroCycleZeroing = false;
   StrictAlign = false;
   HasDSP = false;
   UseNaClTrap = false;
   GenLongCalls = false;
   UnsafeFPMath = false;
   HasV7Clrex = false;
   HasAcquireRelease = false;

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool hasDSP() const {
     return getSTI().getFeatureBits()[ARM::FeatureDSP];
   }
   bool hasD16() const {
     return getSTI().getFeatureBits()[ARM::FeatureD16];
   }
   bool hasV8_1aOps() const {
     return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
   }
+  bool hasRAS() const {
+    return getSTI().getFeatureBits()[ARM::FeatureRAS];
+  }
 
   void SwitchMode() {
     MCSubtargetInfo &STI = copySTI();
     uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
     setAvailableFeatures(FB);
   }
   void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
   bool isMClass() const {
case ARM::t2MOVTi16:
     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
       return Error(
           Op.getStartLoc(),
           "immediate expression for mov requires :lower16: or :upper16");
     break;
   }
+  case ARM::HINT:
+  case ARM::t2HINT: {
+    if (hasRAS()) {
+      // ESB is not predicable (pred must be AL)
+      unsigned Imm8 = Inst.getOperand(0).getImm();
+      unsigned Pred = Inst.getOperand(1).getImm();
+      if (Imm8 == 0x10 && Pred != ARMCC::AL)
+        return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
+                                                 "predicable, but condition "
+                                                 "code specified");
+    }
+    // Without the RAS extension, this behaves as any other unallocated hint.
+    break;
+  }
   }
 
   return false;
 }
 
 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
   switch(Opc) {
   default: llvm_unreachable("unexpected opcode!");
static const struct {
   { (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
     {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
   { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
   { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
   { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
   // FIXME: Only available in A-class, isel not predicated
   { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
   { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
+  { ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} },
   // FIXME: Unsupported extensions.
   { ARM::AEK_OS, Feature_None, {} },
   { ARM::AEK_IWMMXT, Feature_None, {} },
   { ARM::AEK_IWMMXT2, Feature_None, {} },
   { ARM::AEK_MAVERICK, Feature_None, {} },
   { ARM::AEK_XSCALE, Feature_None, {} },
 };
 

llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
                                                   uint64_t Adddress,
                                                   const void *Decoder);
 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);

 // Most Thumb instructions don't have explicit predicates in the
 // encoding, but rather get their predicates from IT context.  We need
 // to fix up the predicate operands using this context information as a
 // post-pass.
 MCDisassembler::DecodeStatus
 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
   MCDisassembler::DecodeStatus S = Success;
 
+  const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
+
   // A few instructions actually have predicates encoded in them.  Don't
   // try to overwrite it if we're seeing one of those.
   switch (MI.getOpcode()) {
     case ARM::tBcc:
     case ARM::t2Bcc:
     case ARM::tCBZ:
     case ARM::tCBNZ:
     case ARM::tCPS:
     case ARM::t2CPS3p:
     case ARM::t2CPS2p:
     case ARM::t2CPS1p:
     case ARM::tMOVSr:
     case ARM::tSETEND:
       // Some instructions (mostly conditional branches) are not
       // allowed in IT blocks.
       if (ITBlock.instrInITBlock())
         S = SoftFail;
       else
         return Success;
       break;
+    case ARM::t2HINT:
+      if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
+        S = SoftFail;
+      break;
     case ARM::tB:
     case ARM::t2B:
     case ARM::t2TBB:
     case ARM::t2TBH:
       // Some instructions (mostly unconditional branches) can
       // only appears at the end of, or outside of, an IT.
       if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
         S = SoftFail;
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
     return MCDisassembler::Fail;
 
   return S;
 }
 
+// Check for UNPREDICTABLE predicated ESB instruction
+static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
+                                 uint64_t Address, const void *Decoder) {
+  unsigned pred = fieldFromInstruction(Insn, 28, 4);
+  unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
+  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
+  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
+
+  DecodeStatus S = MCDisassembler::Success;
+
+  Inst.addOperand(MCOperand::createImm(imm8));
+
+  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
+  // so all predicates should be allowed.
+  if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
+    S = MCDisassembler::SoftFail;
+
+  return S;
+}
+
 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder) {
   unsigned imod = fieldFromInstruction(Insn, 18, 2);
   unsigned M = fieldFromInstruction(Insn, 17, 1);
   unsigned iflags = fieldFromInstruction(Insn, 6, 3);
   unsigned mode = fieldFromInstruction(Insn, 0, 5);
 
   DecodeStatus S = MCDisassembler::Success;

llvm/trunk/test/MC/AArch64/ras-extension.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ras < %s | FileCheck %s
+
+  esb
+// CHECK: esb                             // encoding: [0x1f,0x22,0x03,0xd5]
+
+  msr errselr_el1, x0
+  msr errselr_el1, x15
+  msr errselr_el1, x25
+  msr erxctlr_el1, x1
+  msr erxstatus_el1, x2
+  msr erxaddr_el1, x3
+  msr erxmisc0_el1, x4
+  msr erxmisc1_el1, x5
+  msr disr_el1, x6
+  msr vdisr_el2, x7
+  msr vsesr_el2, x8
+// CHECK: msr     ERRSELR_EL1, x0         // encoding: [0x20,0x53,0x18,0xd5]
+// CHECK: msr     ERRSELR_EL1, x15        // encoding: [0x2f,0x53,0x18,0xd5]
+// CHECK: msr     ERRSELR_EL1, x25        // encoding: [0x39,0x53,0x18,0xd5]
+// CHECK: msr     ERXCTLR_EL1, x1         // encoding: [0x21,0x54,0x18,0xd5]
+// CHECK: msr     ERXSTATUS_EL1, x2       // encoding: [0x42,0x54,0x18,0xd5]
+// CHECK: msr     ERXADDR_EL1, x3         // encoding: [0x63,0x54,0x18,0xd5]
+// CHECK: msr     ERXMISC0_EL1, x4        // encoding: [0x04,0x55,0x18,0xd5]
+// CHECK: msr     ERXMISC1_EL1, x5        // encoding: [0x25,0x55,0x18,0xd5]
+// CHECK: msr     DISR_EL1, x6            // encoding: [0x26,0xc1,0x18,0xd5]
+// CHECK: msr     VDISR_EL2, x7           // encoding: [0x27,0xc1,0x1c,0xd5]
+// CHECK: msr     VSESR_EL2, x8           // encoding: [0x68,0x52,0x1c,0xd5]
+
+  mrs x0, errselr_el1
+  mrs x15, errselr_el1
+  mrs x25, errselr_el1
+  mrs x1, erxctlr_el1
+  mrs x2, erxstatus_el1
+  mrs x3, erxaddr_el1
+  mrs x4, erxmisc0_el1
+  mrs x5, erxmisc1_el1
+  mrs x6, disr_el1
+  mrs x7, vdisr_el2
+  mrs x8, vsesr_el2
+// CHECK: mrs     x0, ERRSELR_EL1         // encoding: [0x20,0x53,0x38,0xd5]
+// CHECK: mrs     x15, ERRSELR_EL1        // encoding: [0x2f,0x53,0x38,0xd5]
+// CHECK: mrs     x25, ERRSELR_EL1        // encoding: [0x39,0x53,0x38,0xd5]
+// CHECK: mrs     x1, ERXCTLR_EL1         // encoding: [0x21,0x54,0x38,0xd5]
+// CHECK: mrs     x2, ERXSTATUS_EL1       // encoding: [0x42,0x54,0x38,0xd5]
+// CHECK: mrs     x3, ERXADDR_EL1         // encoding: [0x63,0x54,0x38,0xd5]
+// CHECK: mrs     x4, ERXMISC0_EL1        // encoding: [0x04,0x55,0x38,0xd5]
+// CHECK: mrs     x5, ERXMISC1_EL1        // encoding: [0x25,0x55,0x38,0xd5]
+// CHECK: mrs     x6, DISR_EL1            // encoding: [0x26,0xc1,0x38,0xd5]
+// CHECK: mrs     x7, VDISR_EL2           // encoding: [0x27,0xc1,0x3c,0xd5]
+// CHECK: mrs     x8, VSESR_EL2           // encoding: [0x68,0x52,0x3c,0xd5]
+
+  mrs x0, erridr_el1
+  mrs x1, erxfr_el1
+// CHECK: mrs     x0, ERRIDR_EL1          // encoding: [0x00,0x53,0x38,0xd5]
+// CHECK: mrs     x1, ERXFR_EL1           // encoding: [0x01,0x54,0x38,0xd5]

llvm/trunk/test/MC/ARM/ras-extension.s

+@ RUN: llvm-mc -triple   armv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=ARM
+@ RUN: llvm-mc -triple thumbv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=THUMB
+
+  esb
+@ ARM:   esb   @ encoding: [0x10,0xf0,0x20,0xe3]
+@ THUMB: esb.w @ encoding: [0xaf,0xf3,0x10,0x80]

llvm/trunk/test/MC/Disassembler/AArch64/ras-extension.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+ras --disassemble < %s | FileCheck %s
+
+[0x1f,0x22,0x03,0xd5]
+# CHECK: esb
+
+# CHECK: msr ERRSELR_EL1, x0
+# CHECK: msr ERXCTLR_EL1, x0
+# CHECK: msr ERXSTATUS_EL1, x0
+# CHECK: msr ERXADDR_EL1, x0
+# CHECK: msr ERXMISC0_EL1, x0
+# CHECK: msr ERXMISC1_EL1, x0
+# CHECK: msr DISR_EL1, x0
+# CHECK: msr VDISR_EL2, x0
+# CHECK: msr VSESR_EL2, x0
+[0x20,0x53,0x18,0xd5]
+[0x20,0x54,0x18,0xd5]
+[0x40,0x54,0x18,0xd5]
+[0x60,0x54,0x18,0xd5]
+[0x00,0x55,0x18,0xd5]
+[0x20,0x55,0x18,0xd5]
+[0x20,0xc1,0x18,0xd5]
+[0x20,0xc1,0x1c,0xd5]
+[0x60,0x52,0x1c,0xd5]
+
+# CHECK: mrs x0, ERRSELR_EL1
+# CHECK: mrs x0, ERXCTLR_EL1
+# CHECK: mrs x0, ERXSTATUS_EL1
+# CHECK: mrs x0, ERXADDR_EL1
+# CHECK: mrs x0, ERXMISC0_EL1
+# CHECK: mrs x0, ERXMISC1_EL1
+# CHECK: mrs x0, DISR_EL1
+# CHECK: mrs x0, VDISR_EL2
+# CHECK: mrs x0, VSESR_EL2
+[0x20,0x53,0x38,0xd5]
+[0x20,0x54,0x38,0xd5]
+[0x40,0x54,0x38,0xd5]
+[0x60,0x54,0x38,0xd5]
+[0x00,0x55,0x38,0xd5]
+[0x20,0x55,0x38,0xd5]
+[0x20,0xc1,0x38,0xd5]
+[0x20,0xc1,0x3c,0xd5]
+[0x60,0x52,0x3c,0xd5]
+
+# CHECK: mrs x0, ERRIDR_EL1
+# CHECK: mrs x0, ERXFR_EL1
+[0x00,0x53,0x38,0xd5]
+[0x00,0x54,0x38,0xd5]

llvm/trunk/test/MC/Disassembler/ARM/ras-extension-arm.txt

+# RUN: llvm-mc < %s -triple armv8a-none-eabi -mattr=+ras -disassemble | FileCheck %s --check-prefix=RAS
+# RUN: llvm-mc < %s -triple armv8a-none-eabi -mattr=-ras -disassemble | FileCheck %s --check-prefix=NO-RAS
+
+[0x10,0xf0,0x20,0xe3]
+# RAS: esb
+# NO-RAS: hint #16

llvm/trunk/test/MC/Disassembler/ARM/ras-extension-thumb.txt

+# RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=+ras -disassemble | FileCheck %s --check-prefix=RAS
+# RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=-ras -disassemble | FileCheck %s --check-prefix=NO-RAS
+
+[0xaf,0xf3,0x10,0x80]
+# RAS: esb
+# NO-RAS: hint.w #16