Add optimization bisect opt-in calls for AArch64 passes

[andrew.w.kaylor]

Summary

This patch adds calls to AArch64 passes that can be safely skipped to opt-in to the optimization bisect mechanism.

Note that the call to skipFunction() will also check for the "optnone" function attribute, so this can theoretically result in passes being skipped even when optimization bisect is not being done. However, I believe that any pass that can be safely skipped should be skipped for functions with the optnone attribute.

[rengolin]

With the same constraints as the ARM version (only for debug purposes), LGTM, too.

[probinson]

In D19394#410009, @rengolin wrote:

With the same constraints as the ARM version (only for debug purposes), LGTM, too.

The optnone aspect is controlled in the source via a pragma or attribute. Does that change your opinion?

[rengolin]

In D19394#410856, @probinson wrote:

The optnone aspect is controlled in the source via a pragma or attribute. Does that change your opinion?

Pragmas are user intentions in writing, so one way or another, this removes the possibility of users being surprised by erratic compiler behaviour, which is what I was worried about.

Or is there something else I'm missing?

[probinson]

In D19394#410899, @rengolin wrote:

In D19394#410856, @probinson wrote:

The optnone aspect is controlled in the source via a pragma or attribute. Does that change your opinion?

Pragmas are user intentions in writing, so one way or another, this removes the possibility of users being surprised by erratic compiler behaviour, which is what I was worried about.

Or is there something else I'm missing?

When you say "only for debug purposes" do you mean debugging the compiler, or end-users doing something in their application? Generally bisection is for the former, attribute optnone is for the latter (generally as a tactic to help debug the application, not the compiler).

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

 
 };
 
 } // end anonymous namespace
 
 //===----------------------------------------------------------------------===//
 
 bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
+  if (skipFunction(*F.getFunction()))
+    return false;
+
   // Don't do anything if this isn't an A53 or A57.
   if (!(F.getSubtarget<AArch64Subtarget>().isCortexA53() ||
         F.getSubtarget<AArch64Subtarget>().isCortexA57()))
     return false;
 
   bool Changed = false;
   DEBUG(dbgs() << "***** AArch64A57FPLoadBalancing *****\n");
 

lib/Target/AArch64/AArch64AddressTypePromotion.cpp

for (auto &II : BB) {
         DEBUG(dbgs() << "Record its chain membership\n");
         SeenChains[Last] = SExt;
       }
     }
   }
 }
 
 bool AArch64AddressTypePromotion::runOnFunction(Function &F) {
+  if (skipFunction(F))
+    return false;
+
   if (!EnableAddressTypePromotion || F.isDeclaration())
     return false;
   Func = &F;
   ConsideredSExtType = Type::getInt64Ty(Func->getContext());
 
   DEBUG(dbgs() << "*** " << getPassName() << ": " << Func->getName() << '\n');
 
   Instructions SExtInsts;
   analyzeSExtension(SExtInsts);
   return propagateSignExtension(SExtInsts);
 }

lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp

bool AArch64AdvSIMDScalar::processMachineBasicBlock(MachineBasicBlock *MBB) {
   return Changed;
 }
 
 // runOnMachineFunction - Pass entry point from PassManager.
 bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) {
   bool Changed = false;
   DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
 
+  if (skipFunction(*mf.getFunction()))
+    return false;
+
   MRI = &mf.getRegInfo();
   TII = mf.getSubtarget().getInstrInfo();
 
   // Just check things on a one-block-at-a-time basis.
   for (MachineFunction::iterator I = mf.begin(), E = mf.end(); I != E; ++I)
     if (processMachineBasicBlock(&*I))
       Changed = true;
   return Changed;
 }
 
 // createAArch64AdvSIMDScalar - Factory function used by AArch64TargetMachine
 // to add the pass to the PassManager.
 FunctionPass *llvm::createAArch64AdvSIMDScalar() {
   return new AArch64AdvSIMDScalar();
 }

lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp

 using namespace llvm;
 
 namespace {
 struct LDTLSCleanup : public MachineFunctionPass {
   static char ID;
   LDTLSCleanup() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override {
+    if (skipFunction(*MF.getFunction()))
+      return false;
+
     AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
     if (AFI->getNumLocalDynamicTLSAccesses() < 2) {
       // No point folding accesses if there isn't at least two.
       return false;
     }
 
     MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
     return VisitNode(DT->getRootNode(), 0);

lib/Target/AArch64/AArch64CollectLOH.cpp

for (const MachineInstr &MI : MBB) {
             DEBUG(dbgs() << "Register: " << PrintReg(*AI, TRI) << '\n');
           }
       }
     }
   }
 }
 
 bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   const MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
 
   MapRegToId RegToId;
   MapIdToReg IdToReg;
   AArch64FunctionInfo *AArch64FI = MF.getInfo<AArch64FunctionInfo>();
   assert(AArch64FI && "No MachineFunctionInfo for this function!");
 

lib/Target/AArch64/AArch64ConditionOptimizer.cpp

if (std::get<0>(Info) == ToImm && std::get<1>(Info) == To->getOpcode()) {
     return true;
   }
   return false;
 }
 
 bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) {
   DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
                << "********** Function: " << MF.getName() << '\n');
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   TII = MF.getSubtarget().getInstrInfo();
   DomTree = &getAnalysis<MachineDominatorTree>();
   MRI = &MF.getRegInfo();
 
   bool Changed = false;
 
   // Visit blocks in dominator tree pre-order. The pre-order enables multiple
   // cmp-conversions from the same head block.

lib/Target/AArch64/AArch64ConditionalCompares.cpp

while (CmpConv.canConvert(MBB) && shouldConvert()) {
     updateLoops(RemovedBlocks);
   }
   return Changed;
 }
 
 bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) {
   DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
                << "********** Function: " << MF.getName() << '\n');
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
   SchedModel = MF.getSubtarget().getSchedModel();
   MRI = &MF.getRegInfo();
   DomTree = &getAnalysis<MachineDominatorTree>();
   Loops = getAnalysisIfAvailable<MachineLoopInfo>();
   Traces = &getAnalysis<MachineTraceMetrics>();
   MinInstr = nullptr;

lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

 
 // Scan the function for instructions that have a dead definition of a
 // register. Replace that register with the zero register when possible.
 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
   TRI = MF.getSubtarget().getRegisterInfo();
   bool Changed = false;
   DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
 
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   for (auto &MBB : MF)
     if (processMachineBasicBlock(MBB))
       Changed = true;
   return Changed;
 }
 
 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
   return new AArch64DeadRegisterDefinitions();
 }

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

bool AArch64LoadStoreOpt::enableNarrowLdMerge(MachineFunction &Fn) {
   // FIXME: The benefit from converting narrow loads into a wider load could be
   // microarchitectural as it assumes that a single load with two bitfield
   // extracts is cheaper than two narrow loads. Currently, this conversion is
   // enabled only in cortex-a57 on which performance benefits were verified.
   return ProfitableArch && !Subtarget->requiresStrictAlign();
 }
 
 bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+  if (skipFunction(*Fn.getFunction()))
+    return false;
+
   Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
   TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
   TRI = Subtarget->getRegisterInfo();
 
   // Resize the modified and used register bitfield trackers.  We do this once
   // per function and then clear the bitfield each time we optimize a load or
   // store.
   ModifiedRegs.resize(TRI->getNumRegs());

lib/Target/AArch64/AArch64PromoteConstant.cpp

public:
   AArch64PromoteConstant() : ModulePass(ID) {}
 
   const char *getPassName() const override { return "AArch64 Promote Constant"; }
 
   /// Iterate over the functions and promote the interesting constants into
   /// global variables with module scope.
   bool runOnModule(Module &M) override {
     DEBUG(dbgs() << getPassName() << '\n');
+    if (skipModule(M))
+      return false;
     bool Changed = false;
     PromotionCacheTy PromotionCache;
     for (auto &MF : M) {
       Changed |= runOnFunction(MF, PromotionCache);
     }
     return Changed;
   }
 

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

for (MachineInstr &MMI :
        make_range(MBB->begin()->getIterator(), LastChange->getIterator()))
     MMI.clearRegisterKills(SmallestDef, TRI);
 
   return true;
 }
 
 bool AArch64RedundantCopyElimination::runOnMachineFunction(
     MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
   bool Changed = false;
   for (MachineBasicBlock &MBB : MF)
     Changed |= optimizeCopy(&MBB);
   return Changed;
 }
 
 FunctionPass *llvm::createAArch64RedundantCopyEliminationPass() {
   return new AArch64RedundantCopyElimination();
 }

lib/Target/AArch64/AArch64StorePairSuppress.cpp

bool AArch64StorePairSuppress::isNarrowFPStore(const MachineInstr &MI) {
   case AArch64::STRDui:
   case AArch64::STURSi:
   case AArch64::STURDi:
     return true;
   }
 }
 
 bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
+  if (skipFunction(*MF.getFunction()))
+    return false;
+
   const TargetSubtargetInfo &ST = MF.getSubtarget();
   TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
   TRI = ST.getRegisterInfo();
   MRI = &MF.getRegInfo();
   SchedModel.init(ST.getSchedModel(), &ST, TII);
   Traces = &getAnalysis<MachineTraceMetrics>();
   MinInstr = nullptr;