[LLDB][MIPS] Fix Floating point Registers Encoding

[nitesh.jain]

Summary

Currently floating point regsiters has "eEncodingUint" encoding. Hence register write $fx '1.25' will failed. This patch add eEncodingIEEE754 encoding for floating point registers($f0 - $f31). This patch will fix test_fp_register_write in TestRegisters.py

[slthakur]

LGTM

[nitesh.jain]

Committed in revision 270208.

source/Plugins/Process/Utility/RegisterInfos_mips.h

       LLVM_EXTENSION offsetof(MSA_linux_mips, regname))
 
 // Note that the size and offset will be updated by platform-specific classes.
 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)            \
     { #reg, alt, sizeof(((GPR_linux_mips*)NULL)->reg) / 2, GPR_OFFSET(reg), eEncodingUint,  \
       eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips }, NULL, NULL }
 
 #define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)           \
-    { #reg, alt, sizeof(((FPR_linux_mips*)NULL)->reg), FPR_OFFSET(reg), eEncodingUint,   \
-      eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, NULL }
+    { #reg, alt, sizeof(((FPR_linux_mips*)NULL)->reg), FPR_OFFSET(reg), eEncodingIEEE754,   \
+      eFormatFloat, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, NULL }
+
+#define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3, kind4)      \
+   { #reg, alt, sizeof(((FPR_linux_mips*)NULL)->reg), FPR_OFFSET(reg), eEncodingUint,   \
+     eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, NULL }
 
 #define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4)    \
     { #reg, alt, sizeof(((MSA_linux_mips*)0)->reg), MSA_OFFSET(reg), eEncodingVector,   \
       eFormatVectorOfUInt8, { kind1, kind2, kind3, kind4, msa_##reg##_mips }, NULL, NULL }
 
 #define DEFINE_MSA_INFO(reg, alt, kind1, kind2, kind3, kind4)    \
     { #reg, alt, sizeof(((MSA_linux_mips*)0)->reg), MSA_OFFSET(reg), eEncodingUint, \
       eFormatHex, { kind1, kind2, kind3, kind4, msa_##reg##_mips }, NULL, NULL }

     DEFINE_FPR (f24,   nullptr,    dwarf_f24_mips,      dwarf_f24_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f25,   nullptr,    dwarf_f25_mips,      dwarf_f25_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f26,   nullptr,    dwarf_f26_mips,      dwarf_f26_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f27,   nullptr,    dwarf_f27_mips,      dwarf_f27_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f28,   nullptr,    dwarf_f28_mips,      dwarf_f28_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f29,   nullptr,    dwarf_f29_mips,      dwarf_f29_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f30,   nullptr,    dwarf_f30_mips,      dwarf_f30_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f31,   nullptr,    dwarf_f31_mips,      dwarf_f31_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_FPR (fcsr,  nullptr,    dwarf_fcsr_mips,     dwarf_fcsr_mips, LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_FPR (fir,   nullptr,    dwarf_fir_mips,      dwarf_fir_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_FPR (config5,   nullptr,    dwarf_config5_mips,      dwarf_config5_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR_INFO (fcsr,  nullptr,    dwarf_fcsr_mips,     dwarf_fcsr_mips, LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR_INFO (fir,   nullptr,    dwarf_fir_mips,      dwarf_fir_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR_INFO (config5,   nullptr,    dwarf_config5_mips,      dwarf_config5_mips,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w0,    nullptr,    dwarf_w0_mips,       dwarf_w0_mips,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w1,    nullptr,    dwarf_w1_mips,       dwarf_w1_mips,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w2,    nullptr,    dwarf_w2_mips,       dwarf_w2_mips,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w3,    nullptr,    dwarf_w3_mips,       dwarf_w3_mips,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w4,    nullptr,    dwarf_w4_mips,       dwarf_w4_mips,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w5,    nullptr,    dwarf_w5_mips,       dwarf_w5_mips,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w6,    nullptr,    dwarf_w6_mips,       dwarf_w6_mips,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w7,    nullptr,    dwarf_w7_mips,       dwarf_w7_mips,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),

 static_assert((sizeof(g_register_infos_mips) / sizeof(g_register_infos_mips[0])) == k_num_registers_mips,
     "g_register_infos_mips has wrong number of register infos");
 
 #undef GPR_OFFSET
 #undef FPR_OFFSET
 #undef MSA_OFFSET
 #undef DEFINE_GPR
 #undef DEFINE_FPR
+#undef DEFINE_FPR_INFO
 #undef DEFINE_MSA
 #undef DEFINE_MSA_INFO
 
 #endif // DECLARE_REGISTER_INFOS_MIPS_STRUCT

source/Plugins/Process/Utility/RegisterInfos_mips64.h

           eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips64 }, NULL, NULL }
 #endif
 
 #define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3, kind4)    \
     { #reg, alt, sizeof(((GPR_linux_mips*)0)->reg) / 2, GPR_OFFSET(reg), eEncodingUint, \
       eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips64 }, NULL, NULL }
 
 #define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)    \
+    { #reg, alt, sizeof(((FPR_linux_mips*)0)->reg), FPR_OFFSET(reg), eEncodingIEEE754,  \
+      eFormatFloat, { kind1, kind2, kind3, kind4, fpr_##reg##_mips64 }, NULL, NULL }
+
+#define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3, kind4)    \
     { #reg, alt, sizeof(((FPR_linux_mips*)0)->reg), FPR_OFFSET(reg), eEncodingUint,   \
       eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips64 }, NULL, NULL }
 
 #define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4)    \
     { #reg, alt, sizeof(((MSA_linux_mips*)0)->reg), MSA_OFFSET(reg), eEncodingVector,   \
       eFormatVectorOfUInt8, { kind1, kind2, kind3, kind4, msa_##reg##_mips64 }, NULL, NULL }
 
 #define DEFINE_MSA_INFO(reg, alt, kind1, kind2, kind3, kind4)    \

     DEFINE_FPR (f24,   nullptr,    dwarf_f24_mips64,      dwarf_f24_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f25,   nullptr,    dwarf_f25_mips64,      dwarf_f25_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f26,   nullptr,    dwarf_f26_mips64,      dwarf_f26_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f27,   nullptr,    dwarf_f27_mips64,      dwarf_f27_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f28,   nullptr,    dwarf_f28_mips64,      dwarf_f28_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f29,   nullptr,    dwarf_f29_mips64,      dwarf_f29_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f30,   nullptr,    dwarf_f30_mips64,      dwarf_f30_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_FPR (f31,   nullptr,    dwarf_f31_mips64,      dwarf_f31_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_FPR (fcsr,  nullptr,    dwarf_fcsr_mips64,     dwarf_fcsr_mips64, LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_FPR (fir,   nullptr,    dwarf_fir_mips64,      dwarf_fir_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
-    DEFINE_FPR (config5,   nullptr,    dwarf_config5_mips64,      dwarf_config5_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR_INFO (fcsr,  nullptr,    dwarf_fcsr_mips64,     dwarf_fcsr_mips64, LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR_INFO (fir,   nullptr,    dwarf_fir_mips64,      dwarf_fir_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
+    DEFINE_FPR_INFO (config5,   nullptr,    dwarf_config5_mips64,      dwarf_config5_mips64,  LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w0,    nullptr,    dwarf_w0_mips64,       dwarf_w0_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w1,    nullptr,    dwarf_w1_mips64,       dwarf_w1_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w2,    nullptr,    dwarf_w2_mips64,       dwarf_w2_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w3,    nullptr,    dwarf_w3_mips64,       dwarf_w3_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w4,    nullptr,    dwarf_w4_mips64,       dwarf_w4_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w5,    nullptr,    dwarf_w5_mips64,       dwarf_w5_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w6,    nullptr,    dwarf_w6_mips64,       dwarf_w6_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),
     DEFINE_MSA (w7,    nullptr,    dwarf_w7_mips64,       dwarf_w7_mips64,   LLDB_INVALID_REGNUM,    LLDB_INVALID_REGNUM),

 };
 
 static_assert((sizeof(g_register_infos_mips64) / sizeof(g_register_infos_mips64[0])) == k_num_registers_mips64,
     "g_register_infos_mips64 has wrong number of register infos");
 
 #undef DEFINE_GPR
 #undef DEFINE_GPR_INFO
 #undef DEFINE_FPR
+#undef DEFINE_FPR_INFO
 #undef DEFINE_MSA
 #undef DEFINE_MSA_INFO
 #undef GPR_OFFSET
 #undef FPR_OFFSET
 #undef MSA_OFFSET
 
 #endif // DECLARE_REGISTER_INFOS_MIPS64_STRUCT