Replace MachineRegisterInfo::isSSA() with a MachineFunctionProperty

[dschuff]

Summary

Use the MachineFunctionProperty mechanism to indicate whether a MachineFunction
is in SSA form instead of a custom method on MachineRegisterInfo. NFC.

[dschuff]

The syntax for MachineFunctionProperties is fairly verbose. I'm wondering if we want to do one or more of the following:

1. Shorten the name of MachineFunctionProperties and/or MachineFunctionProperties::Property
2. Rename MachineFunctionProperties::hasProperty (maybe test to match BitVector, or perhaps operator[])
3. Rename MachineFunction::getProperties or perhaps replace it with a hasProperty or testProperty method on MachineFunction directly
4. Make MachineFunctionProperties::Property a C-style enum rather than a scoped enum

I would say maybe 1 and 2, but I don't have a great idea for what names I'd use for 1.

[qcolombet]

include/llvm/CodeGen/MachineRegisterInfo.h

163

Can we keep the getter and setter, just update what they do?

[dschuff]

Keep MRI accessor

[dschuff]

Put the MRI accessor back, and kept all of its uses.
(But kept the new MachineFunction::print() behavior)

include/llvm/CodeGen/MachineRegisterInfo.h

163

We can; that would obviously make this change smaller, and be easier on out-of-tree targets. Longer term if/when we get more properties we might still want to make them nicer to use. But I'm fine with keeping this accessor; the compiled code would pretty much be identical anyway.

[qcolombet]

include/llvm/CodeGen/MachineRegisterInfo.h

163

Agree.

include/llvm/CodeGen/MachineFunction.h

class MachineFunctionProperties {
   // Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be
   // stated as the negative of "has vregs"
 
 public:
   // The properties are stated in "positive" form; i.e. a pass could require
   // that the property hold, but not that it does not hold.
 
   // Property descriptions:
-  // IsSSA (currently unused, intended to eventually replace
-  // MachineRegisterInfo::isSSA())
+  // IsSSA: True when the machine function is in SSA form and virtual registers
+  // have a single def.
   // TracksLiveness: (currently unsued, intended to eventually replace
   // MachineRegisterInfo::tracksLiveness())
   // AllVRegsAllocated: All virtual registers have been allocated; i.e. all
   // register operands are physical registers.
   enum class Property : unsigned {
     IsSSA,
     TracksLiveness,
     AllVRegsAllocated,

include/llvm/CodeGen/MachineRegisterInfo.h

public:
 
     virtual ~Delegate() {}
   };
 
 private:
   const MachineFunction *MF;
   Delegate *TheDelegate;
 
-  /// IsSSA - True when the machine function is in SSA form and virtual
-  /// registers have a single def.
-  bool IsSSA;
-
   /// TracksLiveness - True while register liveness is being tracked accurately.
   /// Basic block live-in lists, kill flags, and implicit defs may not be
   /// accurate when after this flag is cleared.
   bool TracksLiveness;
 
   /// True if subregister liveness is tracked.
   bool TracksSubRegLiveness;
 
void setDelegate(Delegate *delegate) {
 
     TheDelegate = delegate;
   }
 
   //===--------------------------------------------------------------------===//
   // Function State
   //===--------------------------------------------------------------------===//
 
-  // isSSA - Returns true when the machine function is in SSA form. Early
-  // passes require the machine function to be in SSA form where every virtual
-  // register has a single defining instruction.
-  //
-  // The TwoAddressInstructionPass and PHIElimination passes take the machine
-  // function out of SSA form when they introduce multiple defs per virtual
-  // register.
-  bool isSSA() const { return IsSSA; }
-
-  // leaveSSA - Indicates that the machine function is no longer in SSA form.
-  void leaveSSA() { IsSSA = false; }
-
   /// tracksLiveness - Returns true when tracking register liveness accurately.
   ///
   /// While this flag is true, register liveness information in basic block
   /// live-in lists and machine instruction operands is accurate. This means it
   /// can be used to change the code in ways that affect the values in
   /// registers, for example by the register scavenger.
   ///
   /// When this flag is false, liveness is no longer reliable.

lib/CodeGen/IfConversion.cpp

bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
   TRI = ST.getRegisterInfo();
   MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
   MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
   MRI = &MF.getRegInfo();
   SchedModel.init(ST.getSchedModel(), &ST, TII);
 
   if (!TII) return false;
 
-  PreRegAlloc = MRI->isSSA();
+  PreRegAlloc = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::IsSSA);
 
   bool BFChange = false;
   if (!PreRegAlloc) {
     // Tail merge tend to expose more if-conversion opportunities.
     BranchFolder BF(true, false, *MBFI, *MBPI);
     BFChange = BF.OptimizeFunction(MF, TII, ST.getRegisterInfo(),
                                    getAnalysisIfAvailable<MachineModuleInfo>());
   }

lib/CodeGen/LiveVariables.cpp

bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
   PhysRegDef.assign(NumRegs, nullptr);
   PhysRegUse.assign(NumRegs, nullptr);
   PHIVarInfo.resize(MF->getNumBlockIDs());
   PHIJoins.clear();
 
   // FIXME: LiveIntervals will be updated to remove its dependence on
   // LiveVariables to improve compilation time and eliminate bizarre pass
   // dependencies. Until then, we can't change much in -O0.
-  if (!MRI->isSSA())
+  if (!MF->getProperties().hasProperty(
+      MachineFunctionProperties::Property::IsSSA))
     report_fatal_error("regalloc=... not currently supported with -O0");
 
   analyzePHINodes(mf);
 
   // Calculate live variable information in depth first order on the CFG of the
   // function.  This guarantees that we will see the definition of a virtual
   // register before its uses due to dominance properties of SSA (except for PHI
   // nodes, which are treated as a special case).

lib/CodeGen/MIRParser/MIRParser.cpp

bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   MF.getRegInfo().freezeReservedRegs(MF);
   MF.verify();
   return false;
 }
 
 bool MIRParserImpl::initializeRegisterInfo(MachineFunction &MF,
                                            const yaml::MachineFunction &YamlMF,
                                            PerFunctionMIParsingState &PFS) {
+  MachineFunctionProperties &MFProps = MF.getProperties();
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
-  assert(RegInfo.isSSA());
+  assert(MFProps.hasProperty(MachineFunctionProperties::Property::IsSSA));
   if (!YamlMF.IsSSA)
-    RegInfo.leaveSSA();
+    MFProps.clear(MachineFunctionProperties::Property::IsSSA);
   assert(RegInfo.tracksLiveness());
   if (!YamlMF.TracksRegLiveness)
     RegInfo.invalidateLiveness();
   RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
 
   SMDiagnostic Error;
   // Parse the virtual register information.
   for (const auto &VReg : YamlMF.VirtualRegisters) {

lib/CodeGen/MIRPrinter.cpp

 void MIRPrinter::print(const MachineFunction &MF) {
   initRegisterMaskIds(MF);
 
   yaml::MachineFunction YamlMF;
   YamlMF.Name = MF.getName();
   YamlMF.Alignment = MF.getAlignment();
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
   YamlMF.HasInlineAsm = MF.hasInlineAsm();
+  YamlMF.IsSSA = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::IsSSA);
   YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::AllVRegsAllocated);
 
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());
   MST.incorporateFunction(*MF.getFunction());
   convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
   convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST,
void MIRPrinter::print(const MachineFunction &MF) {
   StrOS.flush();
   yaml::Output Out(OS);
   Out << YamlMF;
 }
 
 void MIRPrinter::convert(yaml::MachineFunction &MF,
                          const MachineRegisterInfo &RegInfo,
                          const TargetRegisterInfo *TRI) {
-  MF.IsSSA = RegInfo.isSSA();
   MF.TracksRegLiveness = RegInfo.tracksLiveness();
   MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
 
   // Print the virtual register definitions.
   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
     yaml::VirtualRegisterDefinition VReg;
     VReg.ID = I;

lib/CodeGen/MachineFunction.cpp

AlignAllFunctions("align-all-functions",
                       cl::desc("Force the alignment of all functions."),
                       cl::init(0), cl::Hidden);
 
 void MachineFunctionInitializer::anchor() {}
 
 void MachineFunctionProperties::print(raw_ostream &ROS) const {
   // Leave this function even in NDEBUG as an out-of-line anchor.
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-  if (!Properties.any()) {
-    ROS << "(empty)";
-    return;
-  }
   for (BitVector::size_type i = 0; i < Properties.size(); ++i) {
-    if (Properties[i]) {
-      switch(static_cast<Property>(i)) {
-        case Property::AllVRegsAllocated:
-          ROS << "AllVRegsAllocated ";
-          break;
-        default:
-          // TODO: Implement IsSSA/TracksLiveness when we make them properties.
-          llvm_unreachable("Unexpected value for property enum");
-      }
+    bool HasProperty = Properties[i];
+      case Property::IsSSA:
+        ROS << (HasProperty ? "SSA, " : "Post SSA, ");
+        break;
+        ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs");
+        break;
     }
   }
 #endif
 }
 
 //===----------------------------------------------------------------------===//
 // MachineFunction implementation
 //===----------------------------------------------------------------------===//
 
 // Out-of-line virtual method.
 MachineFunctionInfo::~MachineFunctionInfo() {}
 
 void ilist_traits<MachineBasicBlock>::deleteNode(MachineBasicBlock *MBB) {
   MBB->getParent()->DeleteMachineBasicBlock(MBB);
 }
 
 MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
                                  unsigned FunctionNum, MachineModuleInfo &mmi)
     : Fn(F), Target(TM), STI(TM.getSubtargetImpl(*F)), Ctx(mmi.getContext()),
       MMI(mmi) {
+  // Assume the function starts in SSA form.
+  Properties.set(MachineFunctionProperties::Property::IsSSA);
   if (STI->getRegisterInfo())
     RegInfo = new (Allocator) MachineRegisterInfo(this);
   else
     RegInfo = nullptr;
 
   MFInfo = nullptr;
   FrameInfo = new (Allocator)
       MachineFrameInfo(STI->getFrameLowering()->getStackAlignment(),

 }
 
 void MachineFunction::print(raw_ostream &OS, SlotIndexes *Indexes) const {
   OS << "# Machine code for function " << getName() << ": ";
   OS << "Properties: <";
   getProperties().print(OS);
   OS << "> : ";
   if (RegInfo) {
-    OS << (RegInfo->isSSA() ? "SSA" : "Post SSA");
     if (!RegInfo->tracksLiveness())
-      OS << ", not tracking liveness";
+      OS << "not tracking liveness";
   }
   OS << '\n';
 
   // Print Frame Information
   FrameInfo->print(*this, OS);
 
   // Print JumpTable Information
   if (JumpTableInfo)

lib/CodeGen/MachineLICM.cpp

bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
   const TargetSubtargetInfo &ST = MF.getSubtarget();
   TII = ST.getInstrInfo();
   TLI = ST.getTargetLowering();
   TRI = ST.getRegisterInfo();
   MFI = MF.getFrameInfo();
   MRI = &MF.getRegInfo();
   SchedModel.init(ST.getSchedModel(), &ST, TII);
 
-  PreRegAlloc = MRI->isSSA();
+  PreRegAlloc = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::IsSSA);
 
   if (PreRegAlloc)
     DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
   else
     DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
   DEBUG(dbgs() << MF.getName() << " ********\n");
 
   if (PreRegAlloc) {

lib/CodeGen/MachineRegisterInfo.cpp

 #include "llvm/Target/TargetSubtargetInfo.h"
 
 using namespace llvm;
 
 // Pin the vtable to this file.
 void MachineRegisterInfo::Delegate::anchor() {}
 
 MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
-  : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
+  : MF(MF), TheDelegate(nullptr), TracksLiveness(true),
     TracksSubRegLiveness(false) {
   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
   VRegInfo.reserve(256);
   RegAllocHints.reserve(256);
   UsedPhysRegMask.resize(NumRegs);
   PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
 }
 

lib/CodeGen/MachineVerifier.cpp

struct MachineVerifier {
 
     Pass *const PASS;
     const char *Banner;
     const MachineFunction *MF;
     const TargetMachine *TM;
     const TargetInstrInfo *TII;
     const TargetRegisterInfo *TRI;
     const MachineRegisterInfo *MRI;
+    const MachineFunctionProperties *MFP;
 
     unsigned foundErrors;
 
     typedef SmallVector<unsigned, 16> RegVector;
     typedef SmallVector<const uint32_t*, 4> RegMaskVector;
     typedef DenseSet<unsigned> RegSet;
     typedef DenseMap<unsigned, const MachineInstr*> RegMap;
     typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
     Last = I->first;
   }
 }
 
 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
   // If a pass has introduced virtual registers without clearing the
   // AllVRegsAllocated property (or set it without allocating the vregs)
   // then report an error.
-  if (MF.getProperties().hasProperty(
+  if (MFP->hasProperty(
           MachineFunctionProperties::Property::AllVRegsAllocated) &&
       MRI->getNumVirtRegs()) {
     report(
         "Function has AllVRegsAllocated property but there are VReg operands",
         &MF);
   }
 }
 
 unsigned MachineVerifier::verify(MachineFunction &MF) {
   foundErrors = 0;
 
   this->MF = &MF;
   TM = &MF.getTarget();
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
+  MFP = &MF.getProperties();
 
   LiveVars = nullptr;
   LiveInts = nullptr;
   LiveStks = nullptr;
   Indexes = nullptr;
   if (PASS) {
     LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
     // We don't want to verify LiveVariables if LiveIntervals is available.
if (*i == b)
     return *++i == a;
   return false;
 }
 
 void
 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
   FirstTerminator = nullptr;
 
-  if (MRI->isSSA()) {
+  if (MFP->hasProperty(MachineFunctionProperties::Property::IsSSA)) {
     // If this block has allocatable physical registers live-in, check that
     // it is an entry block or landing pad.
     for (const auto &LI : MBB->liveins()) {
       if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
           MBB->getIterator() != MBB->getParent()->begin()) {
         report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
       }
     }
if (MO->isTied()) {
           if (!OtherMO.isImplicit())
             report("Explicit def should be tied to implicit use", MO, MONum);
         }
       }
     }
 
     // Verify two-address constraints after leaving SSA form.
     unsigned DefIdx;
-    if (!MRI->isSSA() && MO->isUse() &&
-        MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
+    if (!MFP->hasProperty(MachineFunctionProperties::Property::IsSSA) &&
+        MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
         Reg != MI->getOperand(DefIdx).getReg())
       report("Two-address instruction operands must be identical", MO, MONum);
 
     // Check register classes.
     if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
       unsigned SubIdx = MO->getSubReg();
 
       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
if (MO->isDef()) {
     // Register defined.
     // TODO: verify that earlyclobber ops are not used.
     if (MO->isDead())
       addRegWithSubRegs(regsDead, Reg);
     else
       addRegWithSubRegs(regsDefined, Reg);
 
     // Verify SSA form.
-    if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
+    if (MFP->hasProperty(MachineFunctionProperties::Property::IsSSA) &&
+        TargetRegisterInfo::isVirtualRegister(Reg) &&
         std::next(MRI->def_begin(Reg)) != MRI->def_end())
       report("Multiple virtual register defs in SSA form", MO, MONum);
 
     // Check LiveInts for a live segment, but only for virtual registers.
     if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
       SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
       DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
 

lib/CodeGen/PHIElimination.cpp

namespace {
 
   public:
     static char ID; // Pass identification, replacement for typeid
     PHIElimination() : MachineFunctionPass(ID) {
       initializePHIEliminationPass(*PassRegistry::getPassRegistry());
     }
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
+    // This pass takes the function out of SSA form.
+    MachineFunctionProperties getClearedProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::IsSSA);
+    }
     void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   private:
     /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
     /// in predecessor basic blocks.
     ///
     bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
     void LowerPHINode(MachineBasicBlock &MBB,

 
 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
   MRI = &MF.getRegInfo();
   LV = getAnalysisIfAvailable<LiveVariables>();
   LIS = getAnalysisIfAvailable<LiveIntervals>();
 
   bool Changed = false;
 
-  // This pass takes the function out of SSA form.
-  MRI->leaveSSA();
-
   // Split critical edges to help the coalescer. This does not yet support
   // updating LiveIntervals, so we disable it.
   if (!DisableEdgeSplitting && (LV || LIS)) {
     MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
     for (auto &MBB : MF)
       Changed |= SplitPHIEdges(MF, MBB, MLI);
   }
 

lib/CodeGen/ProcessImplicitDefs.cpp

public:
 
   ProcessImplicitDefs() : MachineFunctionPass(ID) {
     initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry());
   }
 
   void getAnalysisUsage(AnalysisUsage &au) const override;
 
   bool runOnMachineFunction(MachineFunction &fn) override;
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::IsSSA);
+  }
 };
 } // end anonymous namespace
 
 char ProcessImplicitDefs::ID = 0;
 char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID;
 
 INITIALIZE_PASS_BEGIN(ProcessImplicitDefs, "processimpdefs",
                 "Process Implicit Definitions", false, false)
bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
   DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
                << "********** Function: " << MF.getName() << '\n');
 
   bool Changed = false;
 
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
-  assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
   assert(WorkList.empty() && "Inconsistent worklist state");
 
   for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
        MFI != MFE; ++MFI) {
     // Scan the basic block for implicit defs.
     for (MachineBasicBlock::instr_iterator MBBI = MFI->instr_begin(),
          MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
       if (MBBI->isImplicitDef())

lib/CodeGen/RegAllocFast.cpp

bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
   MRI = &MF->getRegInfo();
   TRI = MF->getSubtarget().getRegisterInfo();
   TII = MF->getSubtarget().getInstrInfo();
   MRI->freezeReservedRegs(Fn);
   RegClassInfo.runOnMachineFunction(Fn);
   UsedInInstr.clear();
   UsedInInstr.setUniverse(TRI->getNumRegUnits());
 
-  assert(!MRI->isSSA() && "regalloc requires leaving SSA");
+  assert(!MF->getProperties().hasProperty(
+      MachineFunctionProperties::Property::IsSSA)
+         && "regalloc requires leaving SSA");
 
   // initialize the virtual->physical register map to have a 'null'
   // mapping for all virtual registers
   StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
   LiveVirtRegs.setUniverse(MRI->getNumVirtRegs());
 
   // Loop over all of the basic blocks, eliminating virtual register references
   for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();

lib/CodeGen/TailDuplication.cpp

if (skipOptnoneFunction(*MF.getFunction()))
     return false;
 
   TII = MF.getSubtarget().getInstrInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
   MRI = &MF.getRegInfo();
   MMI = getAnalysisIfAvailable<MachineModuleInfo>();
   MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
 
-  PreRegAlloc = MRI->isSSA();
+  PreRegAlloc = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::IsSSA);
+
   RS.reset();
   if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
     RS.reset(new RegScavenger());
 
   bool MadeChange = false;
   while (TailDuplicateBlocks(MF))
     MadeChange = true;
 

lib/CodeGen/TwoAddressInstructionPass.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addPreserved<LiveIntervals>();
     AU.addPreservedID(MachineLoopInfoID);
     AU.addPreservedID(MachineDominatorsID);
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   /// Pass entry point.
   bool runOnMachineFunction(MachineFunction&) override;
+  // This pass takes the function out of SSA form.
+  MachineFunctionProperties getClearedProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::IsSSA);
+  }
 };
 } // end anonymous namespace
 
 char TwoAddressInstructionPass::ID = 0;
 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
                 "Two-Address instruction pass", false, false)
 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
   OptLevel = TM.getOptLevel();
 
   bool MadeChange = false;
 
   DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
   DEBUG(dbgs() << "********** Function: "
         << MF->getName() << '\n');
 
-  // This pass takes the function out of SSA form.
-  MRI->leaveSSA();
-
   TiedOperandMap TiedOperands;
   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
        MBBI != MBBE; ++MBBI) {
     MBB = &*MBBI;
     unsigned Dist = 0;
     DistanceMap.clear();
     SrcRegMap.clear();
     DstRegMap.clear();

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
   TRI = static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
   TII = static_cast<const SIInstrInfo *>(STM.getInstrInfo());
   MRI = &MF.getRegInfo();
 
   LIS = &getAnalysis<LiveIntervals>();
 
   DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
 
-  assert(!MRI->isSSA());
+  assert(!MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::IsSSA));
 
   bool Modified = false;
 
   for (MachineBasicBlock &MBB : MF)
     Modified |= optimizeBlock(MBB);
 
   return Modified;
 }

lib/Target/AMDGPU/SIShrinkInstructions.cpp

static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
 
   return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);
 }
 
 /// \brief This function checks \p MI for operands defined by a move immediate
 /// instruction and then folds the literal constant into the instruction if it
 /// can.  This function assumes that \p MI is a VOP1, VOP2, or VOPC instruction
 /// and will only fold literal constants if we are still in SSA.
-static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
+static void foldImmediates(MachineFunction& MF, MachineInstr &MI,
+                           const SIInstrInfo *TII,
                            MachineRegisterInfo &MRI, bool TryToCommute = true) {
 
-  if (!MRI.isSSA())
+  if (!MF.getProperties().hasProperty(
+          MachineFunctionProperties::Property::IsSSA))
     return;
 
   assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI));
 
   const SIRegisterInfo &TRI = TII->getRegisterInfo();
   int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
   MachineOperand &Src0 = MI.getOperand(Src0Idx);
 
if (Def && Def->isMoveImmediate()) {
         ++NumLiteralConstantsFolded;
         return;
       }
     }
   }
 
   // We have failed to fold src0, so commute the instruction and try again.
   if (TryToCommute && MI.isCommutable() && TII->commuteInstruction(&MI))
-    foldImmediates(MI, TII, MRI, false);
+    foldImmediates(MF, MI, TII, MRI, false);
 
 }
 
 // Copy MachineOperand with all flags except setting it as implicit.
 static MachineOperand copyRegOperandAsImplicit(const MachineOperand &Orig) {
   assert(!Orig.isImplicit());
   return MachineOperand::CreateReg(Orig.getReg(),
                                    Orig.isDef(),
for (I = MBB.begin(); I != MBB.end(); I = Next) {
                  "Unexpected missing register operand");
           Inst32.addOperand(copyRegOperandAsImplicit(*Src2));
         }
       }
 
       ++NumInstructionsShrunk;
       MI.eraseFromParent();
 
-      foldImmediates(*Inst32, TII, MRI);
+      foldImmediates(MF, *Inst32, TII, MRI);
       DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');
 
 
     }
   }
   return false;
 }

lib/Target/WebAssembly/WebAssemblyStoreResults.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineBlockFrequencyInfo>();
     AU.addPreserved<MachineBlockFrequencyInfo>();
     AU.addRequired<MachineDominatorTree>();
     AU.addPreserved<MachineDominatorTree>();
     AU.addRequired<TargetLibraryInfoWrapperPass>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::IsSSA);
+  }
+
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 private:
 };
 } // end anonymous namespace
 
 char WebAssemblyStoreResults::ID = 0;
 FunctionPass *llvm::createWebAssemblyStoreResults() {
bool WebAssemblyStoreResults::runOnMachineFunction(MachineFunction &MF) {
 
   const MachineRegisterInfo &MRI = MF.getRegInfo();
   MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
   const WebAssemblyTargetLowering &TLI =
       *MF.getSubtarget<WebAssemblySubtarget>().getTargetLowering();
   const auto &LibInfo = getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
   bool Changed = false;
 
-  assert(MRI.isSSA() && "StoreResults depends on SSA form");
-
   for (auto &MBB : MF) {
     DEBUG(dbgs() << "Basic Block: " << MBB.getName() << '\n');
     for (auto &MI : MBB)
       switch (MI.getOpcode()) {
       default:
         break;
       case WebAssembly::STORE8_I32:
       case WebAssembly::STORE16_I32: