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Differential D18559

AMDGPU: Add a shader calling convention
ClosedPublic

Authored by bnieuwenhuizen on Mar 29 2016, 9:26 AM.

Details

Reviewers
• tstellarAMD
nhaehnle
arsenm
mareko
Commits
rGdf3a20cd8068: AMDGPU: Add a shader calling convention
rL265589: AMDGPU: Add a shader calling convention
Summary

This makes it possible to distinguish between mesa shaders
and other kernels even in the presence of compute shaders.

This patch depends in its current form on D18292, but only because
it also updates the newly added testcases to use the new
calling convention.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

Diff Detail

Event Timeline

bnieuwenhuizen updated this revision to Diff 51934.Mar 29 2016, 9:26 AM
bnieuwenhuizen retitled this revision from to AMDGPU: Add a shader calling convention.
bnieuwenhuizen updated this object.
bnieuwenhuizen added reviewers: arsenm, • tstellarAMD, nhaehnle, mareko.
bnieuwenhuizen added a subscriber: llvm-commits.
Herald added subscribers: mehdi_amini, arsenm, qcolombet. · View Herald TranscriptMar 29 2016, 9:26 AM
arsenm added inline comments.Mar 29 2016, 9:38 AM
include/llvm/IR/CallingConv.h
181–182

I was actually thinking of having one for each kind of shader

bnieuwenhuizen updated this revision to Diff 51991.Mar 29 2016, 3:24 PM

One calling convention per shader kind it is then.

TCS/TES (or hardware HS/LS/ES etc.) are not added yet, because they
currently work the same as VS.

• tstellarAMD accepted this revision.Apr 1 2016, 1:38 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Apr 1 2016, 1:38 PM
Closed by commit rL265589: AMDGPU: Add a shader calling convention (authored by nha). · Explain WhyApr 6 2016, 12:46 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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Diff 51934

include/llvm/IR/CallingConv.h

Show First 20 Lines • Show All 172 Lines • ▼ Show 20 Lines enum {
/// Calling convention used for AVR signal routines. /// Calling convention used for AVR signal routines.
AVR_SIGNAL = 85, AVR_SIGNAL = 85,
/// Calling convention used for special AVR rtlib functions /// Calling convention used for special AVR rtlib functions
/// which have an "optimized" convention to preserve registers. /// which have an "optimized" convention to preserve registers.
AVR_BUILTIN = 86, AVR_BUILTIN = 86,
/// Calling convention used for Mesa shaders.
AMDGPU_SHADER = 87,
arsenmUnsubmitted
Not Done
ReplyInline Actions

I was actually thinking of having one for each kind of shader

arsenm: I was actually thinking of having one for each kind of shader
/// The highest possible calling convention ID. Must be some 2^k - 1. /// The highest possible calling convention ID. Must be some 2^k - 1.
MaxID = 1023 MaxID = 1023
}; };
} // End CallingConv namespace } // End CallingConv namespace
} // End llvm namespace } // End llvm namespace
#endif #endif

lib/AsmParser/LLLexer.cpp

Show First 20 Lines • Show All 591 Lines • ▼ Show 20 Lines#define KEYWORD(STR) \
KEYWORD(anyregcc); KEYWORD(anyregcc);
KEYWORD(preserve_mostcc); KEYWORD(preserve_mostcc);
KEYWORD(preserve_allcc); KEYWORD(preserve_allcc);
KEYWORD(ghccc); KEYWORD(ghccc);
KEYWORD(x86_intrcc); KEYWORD(x86_intrcc);
KEYWORD(hhvmcc); KEYWORD(hhvmcc);
KEYWORD(hhvm_ccc); KEYWORD(hhvm_ccc);
KEYWORD(cxx_fast_tlscc); KEYWORD(cxx_fast_tlscc);
KEYWORD(amdgpu_shader);
KEYWORD(cc); KEYWORD(cc);
KEYWORD(c); KEYWORD(c);
KEYWORD(attributes); KEYWORD(attributes);
KEYWORD(alwaysinline); KEYWORD(alwaysinline);
KEYWORD(argmemonly); KEYWORD(argmemonly);
▲ Show 20 Lines • Show All 377 Lines • Show Last 20 Lines

lib/AsmParser/LLParser.cpp

Show First 20 Lines • Show All 1,567 Lines • ▼ Show 20 Lines
/// ::= 'anyregcc' /// ::= 'anyregcc'
/// ::= 'preserve_mostcc' /// ::= 'preserve_mostcc'
/// ::= 'preserve_allcc' /// ::= 'preserve_allcc'
/// ::= 'ghccc' /// ::= 'ghccc'
/// ::= 'x86_intrcc' /// ::= 'x86_intrcc'
/// ::= 'hhvmcc' /// ::= 'hhvmcc'
/// ::= 'hhvm_ccc' /// ::= 'hhvm_ccc'
/// ::= 'cxx_fast_tlscc' /// ::= 'cxx_fast_tlscc'
/// ::= 'amdgpu_shader'
/// ::= 'cc' UINT /// ::= 'cc' UINT
/// ///
bool LLParser::ParseOptionalCallingConv(unsigned &CC) { bool LLParser::ParseOptionalCallingConv(unsigned &CC) {
switch (Lex.getKind()) { switch (Lex.getKind()) {
default: CC = CallingConv::C; return false; default: CC = CallingConv::C; return false;
case lltok::kw_ccc: CC = CallingConv::C; break; case lltok::kw_ccc: CC = CallingConv::C; break;
case lltok::kw_fastcc: CC = CallingConv::Fast; break; case lltok::kw_fastcc: CC = CallingConv::Fast; break;
case lltok::kw_coldcc: CC = CallingConv::Cold; break; case lltok::kw_coldcc: CC = CallingConv::Cold; break;
Show All 18 Linesbool LLParser::ParseOptionalCallingConv(unsigned &CC) {
case lltok::kw_anyregcc: CC = CallingConv::AnyReg; break; case lltok::kw_anyregcc: CC = CallingConv::AnyReg; break;
case lltok::kw_preserve_mostcc:CC = CallingConv::PreserveMost; break; case lltok::kw_preserve_mostcc:CC = CallingConv::PreserveMost; break;
case lltok::kw_preserve_allcc: CC = CallingConv::PreserveAll; break; case lltok::kw_preserve_allcc: CC = CallingConv::PreserveAll; break;
case lltok::kw_ghccc: CC = CallingConv::GHC; break; case lltok::kw_ghccc: CC = CallingConv::GHC; break;
case lltok::kw_x86_intrcc: CC = CallingConv::X86_INTR; break; case lltok::kw_x86_intrcc: CC = CallingConv::X86_INTR; break;
case lltok::kw_hhvmcc: CC = CallingConv::HHVM; break; case lltok::kw_hhvmcc: CC = CallingConv::HHVM; break;
case lltok::kw_hhvm_ccc: CC = CallingConv::HHVM_C; break; case lltok::kw_hhvm_ccc: CC = CallingConv::HHVM_C; break;
case lltok::kw_cxx_fast_tlscc: CC = CallingConv::CXX_FAST_TLS; break; case lltok::kw_cxx_fast_tlscc: CC = CallingConv::CXX_FAST_TLS; break;
case lltok::kw_amdgpu_shader: CC = CallingConv::AMDGPU_SHADER; break;
case lltok::kw_cc: { case lltok::kw_cc: {
Lex.Lex(); Lex.Lex();
return ParseUInt32(CC); return ParseUInt32(CC);
} }
} }
Lex.Lex(); Lex.Lex();
return false; return false;
▲ Show 20 Lines • Show All 4,667 Lines • Show Last 20 Lines

lib/AsmParser/LLToken.h

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines enum Kind {
kw_spir_kernel, kw_spir_func, kw_spir_kernel, kw_spir_func,
kw_x86_64_sysvcc, kw_x86_64_win64cc, kw_x86_64_sysvcc, kw_x86_64_win64cc,
kw_webkit_jscc, kw_anyregcc, kw_webkit_jscc, kw_anyregcc,
kw_preserve_mostcc, kw_preserve_allcc, kw_preserve_mostcc, kw_preserve_allcc,
kw_ghccc, kw_ghccc,
kw_x86_intrcc, kw_x86_intrcc,
kw_hhvmcc, kw_hhvm_ccc, kw_hhvmcc, kw_hhvm_ccc,
kw_cxx_fast_tlscc, kw_cxx_fast_tlscc,
kw_amdgpu_shader,
// Attributes: // Attributes:
kw_attributes, kw_attributes,
kw_alwaysinline, kw_alwaysinline,
kw_argmemonly, kw_argmemonly,
kw_sanitize_address, kw_sanitize_address,
kw_builtin, kw_builtin,
kw_byval, kw_byval,
▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines

lib/IR/AsmWriter.cpp

Show First 20 Lines • Show All 312 Lines • ▼ Show 20 Linesstatic void PrintCallingConv(unsigned cc, raw_ostream &Out) {
case CallingConv::PTX_Device: Out << "ptx_device"; break; case CallingConv::PTX_Device: Out << "ptx_device"; break;
case CallingConv::X86_64_SysV: Out << "x86_64_sysvcc"; break; case CallingConv::X86_64_SysV: Out << "x86_64_sysvcc"; break;
case CallingConv::X86_64_Win64: Out << "x86_64_win64cc"; break; case CallingConv::X86_64_Win64: Out << "x86_64_win64cc"; break;
case CallingConv::SPIR_FUNC: Out << "spir_func"; break; case CallingConv::SPIR_FUNC: Out << "spir_func"; break;
case CallingConv::SPIR_KERNEL: Out << "spir_kernel"; break; case CallingConv::SPIR_KERNEL: Out << "spir_kernel"; break;
case CallingConv::X86_INTR: Out << "x86_intrcc"; break; case CallingConv::X86_INTR: Out << "x86_intrcc"; break;
case CallingConv::HHVM: Out << "hhvmcc"; break; case CallingConv::HHVM: Out << "hhvmcc"; break;
case CallingConv::HHVM_C: Out << "hhvm_ccc"; break; case CallingConv::HHVM_C: Out << "hhvm_ccc"; break;
case CallingConv::AMDGPU_SHADER: Out << "amdgpu_shader"; break;
} }
} }
// PrintEscapedString - Print each character of the specified string, escaping // PrintEscapedString - Print each character of the specified string, escaping
// it if it is not printable or if it is an escape char. // it if it is not printable or if it is an escape char.
static void PrintEscapedString(StringRef Name, raw_ostream &Out) { static void PrintEscapedString(StringRef Name, raw_ostream &Out) {
for (unsigned i = 0, e = Name.size(); i != e; ++i) { for (unsigned i = 0, e = Name.size(); i != e; ++i) {
unsigned char C = Name[i]; unsigned char C = Name[i];
▲ Show 20 Lines • Show All 3,146 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Show First 20 Lines • Show All 571 Lines • ▼ Show 20 Lines if (MFI->getShaderType() == ShaderType::COMPUTE) {
OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4); OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
// TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 = // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
// 0" comment but I don't see a corresponding field in the register spec. // 0" comment but I don't see a corresponding field in the register spec.
} else { } else {
OutStreamer->EmitIntValue(RsrcReg, 4); OutStreamer->EmitIntValue(RsrcReg, 4);
OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) | OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4); S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
if (STM.isVGPRSpillingEnabled(MFI)) { if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4); OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4); OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
} }
} }
if (MFI->getShaderType() == ShaderType::PIXEL) { if (MFI->getShaderType() == ShaderType::PIXEL) {
OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4); OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4); OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUCallingConv.td

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
def CC_AMDGPU_Kernel : CallingConv<[ def CC_AMDGPU_Kernel : CallingConv<[
CCCustom<"allocateStack"> CCCustom<"allocateStack">
]>; ]>;
def CC_AMDGPU : CallingConv<[ def CC_AMDGPU : CallingConv<[
CCIf<"static_cast<const AMDGPUSubtarget&>" CCIf<"static_cast<const AMDGPUSubtarget&>"
"(State.getMachineFunction().getSubtarget()).getGeneration() >=" "(State.getMachineFunction().getSubtarget()).getGeneration() >="
"AMDGPUSubtarget::SOUTHERN_ISLANDS && " "AMDGPUSubtarget::SOUTHERN_ISLANDS && "
"State.getMachineFunction().getInfo<SIMachineFunctionInfo>()" "State.getCallingConv() != CallingConv::AMDGPU_SHADER",
"->getShaderType() == ShaderType::COMPUTE",
CCDelegateTo<CC_AMDGPU_Kernel>>, CCDelegateTo<CC_AMDGPU_Kernel>>,
CCIf<"static_cast<const AMDGPUSubtarget&>" CCIf<"static_cast<const AMDGPUSubtarget&>"
"(State.getMachineFunction().getSubtarget()).getGeneration() < " "(State.getMachineFunction().getSubtarget()).getGeneration() < "
"AMDGPUSubtarget::SOUTHERN_ISLANDS && " "AMDGPUSubtarget::SOUTHERN_ISLANDS && "
"State.getMachineFunction().getInfo<R600MachineFunctionInfo>()" "State.getCallingConv() != CallingConv::AMDGPU_SHADER",
"->getShaderType() == ShaderType::COMPUTE",
CCDelegateTo<CC_AMDGPU_Kernel>>, CCDelegateTo<CC_AMDGPU_Kernel>>,
CCIf<"static_cast<const AMDGPUSubtarget&>" CCIf<"static_cast<const AMDGPUSubtarget&>"
"(State.getMachineFunction().getSubtarget()).getGeneration() >= " "(State.getMachineFunction().getSubtarget()).getGeneration() >= "
"AMDGPUSubtarget::SOUTHERN_ISLANDS", "AMDGPUSubtarget::SOUTHERN_ISLANDS",
CCDelegateTo<CC_SI>>, CCDelegateTo<CC_SI>>,
CCIf<"static_cast<const AMDGPUSubtarget&>" CCIf<"static_cast<const AMDGPUSubtarget&>"
"(State.getMachineFunction().getSubtarget()).getGeneration() < " "(State.getMachineFunction().getSubtarget()).getGeneration() < "
"AMDGPUSubtarget::SOUTHERN_ISLANDS", "AMDGPUSubtarget::SOUTHERN_ISLANDS",
CCDelegateTo<CC_R600>> CCDelegateTo<CC_R600>>
]>; ]>;

lib/Target/AMDGPU/AMDGPUSubtarget.h

Show First 20 Lines • Show All 299 Lines • ▼ Show 20 Lines bool dumpCode() const {
return DumpCode; return DumpCode;
} }
bool r600ALUEncoding() const { bool r600ALUEncoding() const {
return R600ALUInst; return R600ALUInst;
} }
bool isAmdHsaOS() const { bool isAmdHsaOS() const {
return TargetTriple.getOS() == Triple::AMDHSA; return TargetTriple.getOS() == Triple::AMDHSA;
} }
bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const; bool isVGPRSpillingEnabled(const Function& F) const;
bool isXNACKEnabled() const { bool isXNACKEnabled() const {
return EnableXNACK; return EnableXNACK;
} }
unsigned getMaxWavesPerCU() const { unsigned getMaxWavesPerCU() const {
if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
return 10; return 10;
Show All 23 Lines

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Linesunsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
case SEA_ISLANDS: return 12; case SEA_ISLANDS: return 12;
} }
} }
AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const { AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {
return AMDGPU::getIsaVersion(getFeatureBits()); return AMDGPU::getIsaVersion(getFeatureBits());
} }
bool AMDGPUSubtarget::isVGPRSpillingEnabled( bool AMDGPUSubtarget::isVGPRSpillingEnabled(const Function& F) const {
const SIMachineFunctionInfo *MFI) const { return F.getCallingConv() != CallingConv::AMDGPU_SHADER || EnableVGPRSpilling;
return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
} }
void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
MachineInstr *begin, MachineInstr *begin,
MachineInstr *end, MachineInstr *end,
unsigned NumRegionInstrs) const { unsigned NumRegionInstrs) const {
if (getGeneration() >= SOUTHERN_ISLANDS) { if (getGeneration() >= SOUTHERN_ISLANDS) {
Show All 12 Lines

lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

Show First 20 Lines • Show All 259 Lines • ▼ Show 20 Linesstatic bool isIntrinsicSourceOfDivergence(const TargetIntrinsicInfo *TII,
case AMDGPUIntrinsic::SI_tid: case AMDGPUIntrinsic::SI_tid:
case AMDGPUIntrinsic::SI_fs_interp: case AMDGPUIntrinsic::SI_fs_interp:
return true; return true;
} }
} }
static bool isArgPassedInSGPR(const Argument *A) { static bool isArgPassedInSGPR(const Argument *A) {
const Function *F = A->getParent(); const Function *F = A->getParent();
unsigned ShaderType = AMDGPU::getShaderType(*F);
// Arguments to compute shaders are never a source of divergence. // Arguments to compute shaders are never a source of divergence.
if (ShaderType == ShaderType::COMPUTE) if (F->getCallingConv() != CallingConv::AMDGPU_SHADER)
return true; return true;
// For non-compute shaders, SGPR inputs are marked with either inreg or byval. // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) || if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) ||
F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::ByVal)) F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::ByVal))
return true; return true;
// Everything else is in VGPRs. // Everything else is in VGPRs.
Show All 38 Lines

lib/Target/AMDGPU/R600ISelLowering.cpp

Show First 20 Lines • Show All 1,753 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
const ISD::InputArg &In = Ins[i]; const ISD::InputArg &In = Ins[i];
EVT VT = In.VT; EVT VT = In.VT;
EVT MemVT = VA.getLocVT(); EVT MemVT = VA.getLocVT();
if (!VT.isVector() && MemVT.isVector()) { if (!VT.isVector() && MemVT.isVector()) {
// Get load source type if scalarized. // Get load source type if scalarized.
MemVT = MemVT.getVectorElementType(); MemVT = MemVT.getVectorElementType();
} }
if (MFI->getShaderType() != ShaderType::COMPUTE) { if (CallConv == CallingConv::AMDGPU_SHADER) {
unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT); SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
InVals.push_back(Register); InVals.push_back(Register);
continue; continue;
} }
PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()), PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
AMDGPUAS::CONSTANT_BUFFER_0); AMDGPUAS::CONSTANT_BUFFER_0);
▲ Show 20 Lines • Show All 642 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 590 Lines • ▼ Show 20 LinesSDValue SITargetLowering::LowerFormalArguments(
const SIRegisterInfo *TRI = const SIRegisterInfo *TRI =
static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo()); static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
FunctionType *FType = MF.getFunction()->getFunctionType(); FunctionType *FType = MF.getFunction()->getFunctionType();
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
if (Subtarget->isAmdHsaOS() && Info->getShaderType() != ShaderType::COMPUTE) { if (Subtarget->isAmdHsaOS() && (Info->getShaderType() != ShaderType::COMPUTE ||
CallConv == CallingConv::AMDGPU_SHADER)) {
const Function *Fn = MF.getFunction(); const Function *Fn = MF.getFunction();
DiagnosticInfoUnsupported NoGraphicsHSA( DiagnosticInfoUnsupported NoGraphicsHSA(
*Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc()); *Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
DAG.getContext()->diagnose(NoGraphicsHSA); DAG.getContext()->diagnose(NoGraphicsHSA);
return SDValue(); return SDValue();
} }
// FIXME: We currently assume all calling conventions are kernels.
SmallVector<ISD::InputArg, 16> Splits; SmallVector<ISD::InputArg, 16> Splits;
BitVector Skipped(Ins.size()); BitVector Skipped(Ins.size());
for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) { for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
const ISD::InputArg &Arg = Ins[i]; const ISD::InputArg &Arg = Ins[i];
// First check if it's a PS input addr // First check if it's a PS input addr
if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() && if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
Show All 9 Lines if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
Info->markPSInputAllocated(PSInputNum); Info->markPSInputAllocated(PSInputNum);
if (Arg.Used) if (Arg.Used)
Info->PSInputEna |= 1 << PSInputNum; Info->PSInputEna |= 1 << PSInputNum;
++PSInputNum; ++PSInputNum;
} }
// Second split vertices into their elements // Second split vertices into their elements
if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) { if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_SHADER &&
Arg.VT.isVector()) {
ISD::InputArg NewArg = Arg; ISD::InputArg NewArg = Arg;
NewArg.Flags.setSplit(); NewArg.Flags.setSplit();
NewArg.VT = Arg.VT.getVectorElementType(); NewArg.VT = Arg.VT.getVectorElementType();
// We REALLY want the ORIGINAL number of vertex elements here, e.g. a // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
// three or five element vertex only needs three or five registers, // three or five element vertex only needs three or five registers,
// NOT four or eight. // NOT four or eight.
Type *ParamType = FType->getParamType(Arg.getOrigArgIndex()); Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
unsigned NumElements = ParamType->getVectorNumElements(); unsigned NumElements = ParamType->getVectorNumElements();
for (unsigned j = 0; j != NumElements; ++j) { for (unsigned j = 0; j != NumElements; ++j) {
Splits.push_back(NewArg); Splits.push_back(NewArg);
NewArg.PartOffset += NewArg.VT.getStoreSize(); NewArg.PartOffset += NewArg.VT.getStoreSize();
} }
} else if (Info->getShaderType() != ShaderType::COMPUTE) { } else if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_SHADER ) {
Splits.push_back(Arg); Splits.push_back(Arg);
} }
} }
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
*DAG.getContext()); *DAG.getContext());
Show All 14 Lines if (Info->getShaderType() == ShaderType::PIXEL &&
((Info->getPSInputAddr() & 0xF) == 0 && ((Info->getPSInputAddr() & 0xF) == 0 &&
Info->isPSInputAllocated(11)))) { Info->isPSInputAllocated(11)))) {
CCInfo.AllocateReg(AMDGPU::VGPR0); CCInfo.AllocateReg(AMDGPU::VGPR0);
CCInfo.AllocateReg(AMDGPU::VGPR1); CCInfo.AllocateReg(AMDGPU::VGPR1);
Info->markPSInputAllocated(0); Info->markPSInputAllocated(0);
Info->PSInputEna |= 1; Info->PSInputEna |= 1;
} }
if (Info->getShaderType() == ShaderType::COMPUTE) { if (MF.getFunction()->getCallingConv() != CallingConv::AMDGPU_SHADER ) {
getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins, getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
Splits); Splits);
} }
// FIXME: How should these inputs interact with inreg / custom SGPR inputs? // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
if (Info->hasPrivateSegmentBuffer()) { if (Info->hasPrivateSegmentBuffer()) {
unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI); unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass); MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
▲ Show 20 Lines • Show All 227 Lines • ▼ Show 20 LinesSDValue SITargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, CallingConv::ID CallConv,
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<SDValue> &OutVals,
SDLoc DL, SelectionDAG &DAG) const { SDLoc DL, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
if (Info->getShaderType() == ShaderType::COMPUTE) if (MF.getFunction()->getCallingConv() != CallingConv::AMDGPU_SHADER)
return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs, return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
OutVals, DL, DAG); OutVals, DL, DAG);
Info->setIfReturnsVoid(Outs.size() == 0); Info->setIfReturnsVoid(Outs.size() == 0);
SmallVector<ISD::OutputArg, 48> Splits; SmallVector<ISD::OutputArg, 48> Splits;
SmallVector<SDValue, 48> SplitVals; SmallVector<SDValue, 48> SplitVals;
▲ Show 20 Lines • Show All 2,082 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 590 Lines • ▼ Show 20 Lines if (RI.isSGPRClass(RC)) {
BuildMI(MBB, MI, DL, get(Opcode)) BuildMI(MBB, MI, DL, get(Opcode))
.addReg(SrcReg) // src .addReg(SrcReg) // src
.addFrameIndex(FrameIndex) // frame_idx .addFrameIndex(FrameIndex) // frame_idx
.addMemOperand(MMO); .addMemOperand(MMO);
return; return;
} }
if (!ST.isVGPRSpillingEnabled(MFI)) { if (!ST.isVGPRSpillingEnabled(*MF->getFunction())) {
LLVMContext &Ctx = MF->getFunction()->getContext(); LLVMContext &Ctx = MF->getFunction()->getContext();
Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to" Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
" spill register"); " spill register");
BuildMI(MBB, MI, DL, get(AMDGPU::KILL)) BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
.addReg(SrcReg); .addReg(SrcReg);
return; return;
} }
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines if (RI.isSGPRClass(RC)) {
unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize()); unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize());
BuildMI(MBB, MI, DL, get(Opcode), DestReg) BuildMI(MBB, MI, DL, get(Opcode), DestReg)
.addFrameIndex(FrameIndex) // frame_idx .addFrameIndex(FrameIndex) // frame_idx
.addMemOperand(MMO); .addMemOperand(MMO);
return; return;
} }
if (!ST.isVGPRSpillingEnabled(MFI)) { if (!ST.isVGPRSpillingEnabled(*MF->getFunction())) {
LLVMContext &Ctx = MF->getFunction()->getContext(); LLVMContext &Ctx = MF->getFunction()->getContext();
Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to" Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
" restore register"); " restore register");
BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg); BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
return; return;
} }
Show All 29 Lines if (!MFI->hasCalculatedTID()) {
MachineBasicBlock::iterator Insert = Entry.front(); MachineBasicBlock::iterator Insert = Entry.front();
DebugLoc DL = Insert->getDebugLoc(); DebugLoc DL = Insert->getDebugLoc();
TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass); TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
if (TIDReg == AMDGPU::NoRegister) if (TIDReg == AMDGPU::NoRegister)
return TIDReg; return TIDReg;
if (MFI->getShaderType() == ShaderType::COMPUTE && if (MF->getFunction()->getCallingConv() != CallingConv::AMDGPU_SHADER &&
WorkGroupSize > WavefrontSize) { WorkGroupSize > WavefrontSize) {
unsigned TIDIGXReg unsigned TIDIGXReg
= TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X); = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X);
unsigned TIDIGYReg unsigned TIDIGYReg
= TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y); = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y);
unsigned TIDIGZReg unsigned TIDIGZReg
= TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z); = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z);
▲ Show 20 Lines • Show All 2,217 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines : AMDGPUMachineFunction(MF),
WorkItemIDZ(false) { WorkItemIDZ(false) {
const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
const Function *F = MF.getFunction(); const Function *F = MF.getFunction();
PSInputAddr = AMDGPU::getInitialPSInputAddr(*F); PSInputAddr = AMDGPU::getInitialPSInputAddr(*F);
const MachineFrameInfo *FrameInfo = MF.getFrameInfo(); const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
if (getShaderType() == ShaderType::COMPUTE) if (F->getCallingConv() != CallingConv::AMDGPU_SHADER)
KernargSegmentPtr = true; KernargSegmentPtr = true;
if (F->hasFnAttribute("amdgpu-work-group-id-y")) if (F->hasFnAttribute("amdgpu-work-group-id-y"))
WorkGroupIDY = true; WorkGroupIDY = true;
if (F->hasFnAttribute("amdgpu-work-group-id-z")) if (F->hasFnAttribute("amdgpu-work-group-id-z"))
WorkGroupIDZ = true; WorkGroupIDZ = true;
if (F->hasFnAttribute("amdgpu-work-item-id-y")) if (F->hasFnAttribute("amdgpu-work-item-id-y"))
WorkItemIDY = true; WorkItemIDY = true;
if (F->hasFnAttribute("amdgpu-work-item-id-z")) if (F->hasFnAttribute("amdgpu-work-item-id-z"))
WorkItemIDZ = true; WorkItemIDZ = true;
// X, XY, and XYZ are the only supported combinations, so make sure Y is // X, XY, and XYZ are the only supported combinations, so make sure Y is
// enabled if Z is. // enabled if Z is.
if (WorkItemIDZ) if (WorkItemIDZ)
WorkItemIDY = true; WorkItemIDY = true;
bool MaySpill = ST.isVGPRSpillingEnabled(this); bool MaySpill = ST.isVGPRSpillingEnabled(*F);
bool HasStackObjects = FrameInfo->hasStackObjects(); bool HasStackObjects = FrameInfo->hasStackObjects();
if (HasStackObjects || MaySpill) if (HasStackObjects || MaySpill)
PrivateSegmentWaveByteOffset = true; PrivateSegmentWaveByteOffset = true;
if (ST.isAmdHsaOS()) { if (ST.isAmdHsaOS()) {
if (HasStackObjects || MaySpill) if (HasStackObjects || MaySpill)
PrivateSegmentBuffer = true; PrivateSegmentBuffer = true;
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SITypeRewriter.cpp

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
bool SITypeRewriter::doInitialization(Module &M) { bool SITypeRewriter::doInitialization(Module &M) {
Mod = &M; Mod = &M;
v16i8 = VectorType::get(Type::getInt8Ty(M.getContext()), 16); v16i8 = VectorType::get(Type::getInt8Ty(M.getContext()), 16);
v4i32 = VectorType::get(Type::getInt32Ty(M.getContext()), 4); v4i32 = VectorType::get(Type::getInt32Ty(M.getContext()), 4);
return false; return false;
} }
bool SITypeRewriter::runOnFunction(Function &F) { bool SITypeRewriter::runOnFunction(Function &F) {
if (AMDGPU::getShaderType(F) == ShaderType::COMPUTE) if (F.getCallingConv() != CallingConv::AMDGPU_SHADER)
return false; return false;
visit(F); visit(F);
visit(F); visit(F);
return false; return false;
} }
▲ Show 20 Lines • Show All 85 Lines • Show Last 20 Lines

test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll

; RUN: opt %s -mtriple amdgcn-- -analyze -divergence | FileCheck %s ; RUN: opt %s -mtriple amdgcn-- -analyze -divergence | FileCheck %s
; CHECK: DIVERGENT: ; CHECK: DIVERGENT:
; CHECK-NOT: %arg0 ; CHECK-NOT: %arg0
; CHECK-NOT: %arg1 ; CHECK-NOT: %arg1
; CHECK-NOT; %arg2 ; CHECK-NOT; %arg2
; CHECK: <2 x i32> %arg3 ; CHECK: <2 x i32> %arg3
; CHECK: DIVERGENT: <3 x i32> %arg4 ; CHECK: DIVERGENT: <3 x i32> %arg4
; CHECK: DIVERGENT: float %arg5 ; CHECK: DIVERGENT: float %arg5
; CHECK: DIVERGENT: i32 %arg6 ; CHECK: DIVERGENT: i32 %arg6
define void @main([4 x <16 x i8>] addrspace(2)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { define cc 87 void @main([4 x <16 x i8>] addrspace(2)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
ret void ret void
} }
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }

test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll

  • This file was added.
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}shader_cc:
; GCN: v_add_i32_e32 v0, vcc, s8, v0
define amdgpu_shader float @shader_cc(<4 x i32> inreg, <4 x i32> inreg, i32 inreg %w, float %v) {
%vi = bitcast float %v to i32
%x = add i32 %vi, %w
%xf = bitcast i32 %x to float
ret float %xf
}
; GCN-LABEL: {{^}}kernel_cc:
; GCN: s_endpgm
define float @kernel_cc(<4 x i32> inreg, <4 x i32> inreg, i32 inreg %w, float %v) {
%vi = bitcast float %v to i32
%x = add i32 %vi, %w
%xf = bitcast i32 %x to float
ret float %xf
}

test/CodeGen/AMDGPU/big_alu.ll

; RUN: llc -march=r600 -mcpu=cedar < %s ; RUN: llc -march=r600 -mcpu=cedar < %s
; This test ensures that R600 backend can handle ifcvt properly ; This test ensures that R600 backend can handle ifcvt properly
; and do not generate ALU clauses with more than 128 instructions. ; and do not generate ALU clauses with more than 128 instructions.
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) #1 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) #1 {
main_body: main_body:
%0 = extractelement <4 x float> %reg0, i32 0 %0 = extractelement <4 x float> %reg0, i32 0
%1 = extractelement <4 x float> %reg0, i32 1 %1 = extractelement <4 x float> %reg0, i32 1
%2 = extractelement <4 x float> %reg0, i32 2 %2 = extractelement <4 x float> %reg0, i32 2
%3 = extractelement <4 x float> %reg0, i32 3 %3 = extractelement <4 x float> %reg0, i32 3
%4 = extractelement <4 x float> %reg1, i32 0 %4 = extractelement <4 x float> %reg1, i32 0
%5 = extractelement <4 x float> %reg9, i32 0 %5 = extractelement <4 x float> %reg9, i32 0
%6 = extractelement <4 x float> %reg8, i32 0 %6 = extractelement <4 x float> %reg8, i32 0
▲ Show 20 Lines • Show All 1,289 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/bitcast.ll

; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; This test just checks that the compiler doesn't crash. ; This test just checks that the compiler doesn't crash.
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
; FUNC-LABEL: {{^}}v32i8_to_v8i32: ; FUNC-LABEL: {{^}}v32i8_to_v8i32:
; SI: s_endpgm ; SI: s_endpgm
define void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 { define amdgpu_shader void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 {
entry: entry:
%1 = load <32 x i8>, <32 x i8> addrspace(2)* %0 %1 = load <32 x i8>, <32 x i8> addrspace(2)* %0
%2 = bitcast <32 x i8> %1 to <8 x i32> %2 = bitcast <32 x i8> %1 to <8 x i32>
%3 = extractelement <8 x i32> %2, i32 1 %3 = extractelement <8 x i32> %2, i32 1
%4 = icmp ne i32 %3, 0 %4 = icmp ne i32 %3, 0
%5 = select i1 %4, float 0.0, float 1.0 %5 = select i1 %4, float 0.0, float 1.0
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5)
ret void ret void
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/cayman-loop-bug.ll

; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: LOOP_START_DX10 ; CHECK: LOOP_START_DX10
; CHECK: ALU_PUSH_BEFORE ; CHECK: ALU_PUSH_BEFORE
; CHECK: LOOP_START_DX10 ; CHECK: LOOP_START_DX10
; CHECK: PUSH ; CHECK: PUSH
; CHECK-NOT: ALU_PUSH_BEFORE ; CHECK-NOT: ALU_PUSH_BEFORE
; CHECK: END_LOOP ; CHECK: END_LOOP
; CHECK: END_LOOP ; CHECK: END_LOOP
define void @main (<4 x float> inreg %reg0) #0 { define amdgpu_shader void @main (<4 x float> inreg %reg0) #0 {
entry: entry:
br label %outer_loop br label %outer_loop
outer_loop: outer_loop:
%cnt = phi i32 [0, %entry], [%cnt_incr, %inner_loop] %cnt = phi i32 [0, %entry], [%cnt_incr, %inner_loop]
%cond = icmp eq i32 %cnt, 16 %cond = icmp eq i32 %cnt, 16
br i1 %cond, label %outer_loop_body, label %exit br i1 %cond, label %outer_loop_body, label %exit
outer_loop_body: outer_loop_body:
%cnt_incr = add i32 %cnt, 1 %cnt_incr = add i32 %cnt, 1
br label %inner_loop br label %inner_loop
inner_loop: inner_loop:
%cnt2 = phi i32 [0, %outer_loop_body], [%cnt2_incr, %inner_loop_body] %cnt2 = phi i32 [0, %outer_loop_body], [%cnt2_incr, %inner_loop_body]
%cond2 = icmp eq i32 %cnt2, 16 %cond2 = icmp eq i32 %cnt2, 16
br i1 %cond, label %inner_loop_body, label %outer_loop br i1 %cond, label %inner_loop_body, label %outer_loop
inner_loop_body: inner_loop_body:
%cnt2_incr = add i32 %cnt2, 1 %cnt2_incr = add i32 %cnt2, 1
br label %inner_loop br label %inner_loop
exit: exit:
ret void ret void
} }
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
No newline at end of file

test/CodeGen/AMDGPU/complex-folding.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: {{^}}main: ; CHECK: {{^}}main:
; CHECK-NOT: MOV ; CHECK-NOT: MOV
define void @main(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0) #0 {
entry: entry:
%0 = extractelement <4 x float> %reg0, i32 0 %0 = extractelement <4 x float> %reg0, i32 0
%1 = call float @fabs(float %0) %1 = call float @fabs(float %0)
%2 = fptoui float %1 to i32 %2 = fptoui float %1 to i32
%3 = bitcast i32 %2 to float %3 = bitcast i32 %2 to float
%4 = insertelement <4 x float> undef, float %3, i32 0 %4 = insertelement <4 x float> undef, float %3, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %4, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %4, i32 0, i32 0)
ret void ret void
} }
declare float @fabs(float ) readnone declare float @fabs(float ) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
No newline at end of file

test/CodeGen/AMDGPU/floor.ll

; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s
; CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0 %r0 = extractelement <4 x float> %reg0, i32 0
%r1 = call float @floor(float %r0) %r1 = call float @floor(float %r0)
%vec = insertelement <4 x float> undef, float %r1, i32 0 %vec = insertelement <4 x float> undef, float %r1, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
declare float @floor(float) readonly declare float @floor(float) readonly
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }

test/CodeGen/AMDGPU/fmad.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0 %r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1 %r1 = extractelement <4 x float> %reg0, i32 1
%r2 = extractelement <4 x float> %reg0, i32 2 %r2 = extractelement <4 x float> %reg0, i32 2
%r3 = fmul float %r0, %r1 %r3 = fmul float %r0, %r1
%r4 = fadd float %r3, %r2 %r4 = fadd float %r3, %r2
%vec = insertelement <4 x float> undef, float %r4, i32 0 %vec = insertelement <4 x float> undef, float %r4, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
declare float @fabs(float ) readnone declare float @fabs(float ) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
No newline at end of file

test/CodeGen/AMDGPU/fmax.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: MAX * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK: MAX * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0 %r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1 %r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fcmp oge float %r0, %r1 %r2 = fcmp oge float %r0, %r1
%r3 = select i1 %r2, float %r0, float %r1 %r3 = select i1 %r2, float %r0, float %r1
%vec = insertelement <4 x float> undef, float %r3, i32 0 %vec = insertelement <4 x float> undef, float %r3, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
No newline at end of file

test/CodeGen/AMDGPU/fmin.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0 %r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1 %r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fcmp uge float %r0, %r1 %r2 = fcmp uge float %r0, %r1
%r3 = select i1 %r2, float %r1, float %r0 %r3 = select i1 %r2, float %r1, float %r0
%vec = insertelement <4 x float> undef, float %r3, i32 0 %vec = insertelement <4 x float> undef, float %r3, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
No newline at end of file

test/CodeGen/AMDGPU/input-mods.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG
;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM ;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM
;EG-LABEL: {{^}}test: ;EG-LABEL: {{^}}test:
;EG: EXP_IEEE * ;EG: EXP_IEEE *
;CM-LABEL: {{^}}test: ;CM-LABEL: {{^}}test:
;CM: EXP_IEEE T{{[0-9]+}}.X, -|T{{[0-9]+}}.X| ;CM: EXP_IEEE T{{[0-9]+}}.X, -|T{{[0-9]+}}.X|
;CM: EXP_IEEE T{{[0-9]+}}.Y (MASKED), -|T{{[0-9]+}}.X| ;CM: EXP_IEEE T{{[0-9]+}}.Y (MASKED), -|T{{[0-9]+}}.X|
;CM: EXP_IEEE T{{[0-9]+}}.Z (MASKED), -|T{{[0-9]+}}.X| ;CM: EXP_IEEE T{{[0-9]+}}.Z (MASKED), -|T{{[0-9]+}}.X|
;CM: EXP_IEEE * T{{[0-9]+}}.W (MASKED), -|T{{[0-9]+}}.X| ;CM: EXP_IEEE * T{{[0-9]+}}.W (MASKED), -|T{{[0-9]+}}.X|
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0 %r0 = extractelement <4 x float> %reg0, i32 0
%r1 = call float @llvm.fabs.f32(float %r0) %r1 = call float @llvm.fabs.f32(float %r0)
%r2 = fsub float -0.000000e+00, %r1 %r2 = fsub float -0.000000e+00, %r1
%r3 = call float @llvm.exp2.f32(float %r2) %r3 = call float @llvm.exp2.f32(float %r2)
%vec = insertelement <4 x float> undef, float %r3, i32 0 %vec = insertelement <4 x float> undef, float %r3, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
declare float @llvm.exp2.f32(float) readnone declare float @llvm.exp2.f32(float) readnone
declare float @llvm.fabs.f32(float) readnone declare float @llvm.fabs.f32(float) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }

test/CodeGen/AMDGPU/large-alloca-graphics.ll

; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=carrizo < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=carrizo < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
; ALL-LABEL: {{^}}large_alloca_pixel_shader: ; ALL-LABEL: {{^}}large_alloca_pixel_shader:
; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GCN: s_mov_b32 s10, -1 ; GCN: s_mov_b32 s10, -1
; CI: s_mov_b32 s11, 0x98f000 ; CI: s_mov_b32 s11, 0x98f000
; VI: s_mov_b32 s11, 0x980000 ; VI: s_mov_b32 s11, 0x980000
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen
; ALL: ; ScratchSize: 32772 ; ALL: ; ScratchSize: 32772
define void @large_alloca_pixel_shader(i32 %x, i32 %y) #1 { define amdgpu_shader void @large_alloca_pixel_shader(i32 %x, i32 %y) #1 {
%large = alloca [8192 x i32], align 4 %large = alloca [8192 x i32], align 4
%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 %gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191
store volatile i32 %x, i32* %gep store volatile i32 %x, i32* %gep
%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y %gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y
%val = load volatile i32, i32* %gep1 %val = load volatile i32, i32* %gep1
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
; ALL-LABEL: {{^}}large_alloca_pixel_shader_inreg: ; ALL-LABEL: {{^}}large_alloca_pixel_shader_inreg:
; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GCN: s_mov_b32 s10, -1 ; GCN: s_mov_b32 s10, -1
; CI: s_mov_b32 s11, 0x98f000 ; CI: s_mov_b32 s11, 0x98f000
; VI: s_mov_b32 s11, 0x980000 ; VI: s_mov_b32 s11, 0x980000
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen
; ALL: ; ScratchSize: 32772 ; ALL: ; ScratchSize: 32772
define void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #1 { define amdgpu_shader void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #1 {
%large = alloca [8192 x i32], align 4 %large = alloca [8192 x i32], align 4
%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 %gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191
store volatile i32 %x, i32* %gep store volatile i32 %x, i32* %gep
%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y %gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y
%val = load volatile i32, i32* %gep1 %val = load volatile i32, i32* %gep1
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind "ShaderType"="0" } attributes #1 = { nounwind "ShaderType"="0" }

test/CodeGen/AMDGPU/llvm.AMDGPU.kill.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}kill_gs_const: ; SI-LABEL: {{^}}kill_gs_const:
; SI-NOT: v_cmpx_le_f32 ; SI-NOT: v_cmpx_le_f32
; SI: s_mov_b64 exec, 0 ; SI: s_mov_b64 exec, 0
define void @kill_gs_const() #0 { define amdgpu_shader void @kill_gs_const() #0 {
main_body: main_body:
%0 = icmp ule i32 0, 3 %0 = icmp ule i32 0, 3
%1 = select i1 %0, float 1.000000e+00, float -1.000000e+00 %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
call void @llvm.AMDGPU.kill(float %1) call void @llvm.AMDGPU.kill(float %1)
%2 = icmp ule i32 3, 0 %2 = icmp ule i32 3, 0
%3 = select i1 %2, float 1.000000e+00, float -1.000000e+00 %3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
call void @llvm.AMDGPU.kill(float %3) call void @llvm.AMDGPU.kill(float %3)
ret void ret void
} }
; SI-LABEL: {{^}}kill_vcc_implicit_def: ; SI-LABEL: {{^}}kill_vcc_implicit_def:
; SI-NOT: v_cmp_gt_f32_e32 vcc, ; SI-NOT: v_cmp_gt_f32_e32 vcc,
; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}} ; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}} ; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]] ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 { define amdgpu_shader void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 {
entry: entry:
%tmp0 = fcmp olt float %13, 0.0 %tmp0 = fcmp olt float %13, 0.0
call void @llvm.AMDGPU.kill(float %14) call void @llvm.AMDGPU.kill(float %14)
%tmp1 = select i1 %tmp0, float 1.0, float 0.0 %tmp1 = select i1 %tmp0, float 1.0, float 0.0
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
ret void ret void
} }
declare void @llvm.AMDGPU.kill(float) declare void @llvm.AMDGPU.kill(float)
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
attributes #0 = { "ShaderType"="2" } attributes #0 = { "ShaderType"="2" }
attributes #1 = { "ShaderType"="0" } attributes #1 = { "ShaderType"="0" }
!0 = !{!"const", null, i32 1} !0 = !{!"const", null, i32 1}

test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s ;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
;RUN: llc < %s -march=amdgcn -mcpu=stoney -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s ;RUN: llc < %s -march=amdgcn -mcpu=stoney -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
;GCN-LABEL: {{^}}main: ;GCN-LABEL: {{^}}main:
;GCN-NOT: s_wqm ;GCN-NOT: s_wqm
;GCN: s_mov_b32 ;GCN: s_mov_b32
;GCN-NEXT: v_interp_mov_f32 ;GCN-NEXT: v_interp_mov_f32
;GCN: v_interp_p1_f32 ;GCN: v_interp_p1_f32
;GCN: v_interp_p2_f32 ;GCN: v_interp_p2_f32
define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 { define amdgpu_shader void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 {
main_body: main_body:
%5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
%6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4) %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4)
%7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4) %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4)
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7)
ret void ret void
} }
; Thest that v_interp_p1 uses different source and destination registers ; Thest that v_interp_p1 uses different source and destination registers
; on 16 bank LDS chips. ; on 16 bank LDS chips.
; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug: ; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug:
; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]] ; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
define void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { define amdgpu_shader void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
main_body: main_body:
%22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
%23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
%24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
%25 = call float @fabs(float %22) %25 = call float @fabs(float %22)
%26 = call float @fabs(float %23) %26 = call float @fabs(float %23)
%27 = call float @fabs(float %24) %27 = call float @fabs(float %24)
%28 = call i32 @llvm.SI.packf16(float %25, float %26) %28 = call i32 @llvm.SI.packf16(float %25, float %26)
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test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s
; CHECK-LABEL: {{^}}v1: ; CHECK-LABEL: {{^}}v1:
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd
define void @v1(i32 %a1) #0 { define amdgpu_shader void @v1(i32 %a1) #0 {
entry: entry:
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%2 = extractelement <4 x float> %1, i32 0 %2 = extractelement <4 x float> %1, i32 0
%3 = extractelement <4 x float> %1, i32 2 %3 = extractelement <4 x float> %1, i32 2
%4 = extractelement <4 x float> %1, i32 3 %4 = extractelement <4 x float> %1, i32 3
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
ret void ret void
} }
; CHECK-LABEL: {{^}}v2: ; CHECK-LABEL: {{^}}v2:
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb
define void @v2(i32 %a1) #0 { define amdgpu_shader void @v2(i32 %a1) #0 {
entry: entry:
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%2 = extractelement <4 x float> %1, i32 0 %2 = extractelement <4 x float> %1, i32 0
%3 = extractelement <4 x float> %1, i32 1 %3 = extractelement <4 x float> %1, i32 1
%4 = extractelement <4 x float> %1, i32 3 %4 = extractelement <4 x float> %1, i32 3
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
ret void ret void
} }
; CHECK-LABEL: {{^}}v3: ; CHECK-LABEL: {{^}}v3:
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe
define void @v3(i32 %a1) #0 { define amdgpu_shader void @v3(i32 %a1) #0 {
entry: entry:
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%2 = extractelement <4 x float> %1, i32 1 %2 = extractelement <4 x float> %1, i32 1
%3 = extractelement <4 x float> %1, i32 2 %3 = extractelement <4 x float> %1, i32 2
%4 = extractelement <4 x float> %1, i32 3 %4 = extractelement <4 x float> %1, i32 3
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
ret void ret void
} }
; CHECK-LABEL: {{^}}v4: ; CHECK-LABEL: {{^}}v4:
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7
define void @v4(i32 %a1) #0 { define amdgpu_shader void @v4(i32 %a1) #0 {
entry: entry:
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%2 = extractelement <4 x float> %1, i32 0 %2 = extractelement <4 x float> %1, i32 0
%3 = extractelement <4 x float> %1, i32 1 %3 = extractelement <4 x float> %1, i32 1
%4 = extractelement <4 x float> %1, i32 2 %4 = extractelement <4 x float> %1, i32 2
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
ret void ret void
} }
; CHECK-LABEL: {{^}}v5: ; CHECK-LABEL: {{^}}v5:
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa
define void @v5(i32 %a1) #0 { define amdgpu_shader void @v5(i32 %a1) #0 {
entry: entry:
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%2 = extractelement <4 x float> %1, i32 1 %2 = extractelement <4 x float> %1, i32 1
%3 = extractelement <4 x float> %1, i32 3 %3 = extractelement <4 x float> %1, i32 3
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
ret void ret void
} }
; CHECK-LABEL: {{^}}v6: ; CHECK-LABEL: {{^}}v6:
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6
define void @v6(i32 %a1) #0 { define amdgpu_shader void @v6(i32 %a1) #0 {
entry: entry:
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%2 = extractelement <4 x float> %1, i32 1 %2 = extractelement <4 x float> %1, i32 1
%3 = extractelement <4 x float> %1, i32 2 %3 = extractelement <4 x float> %1, i32 2
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
ret void ret void
} }
; CHECK-LABEL: {{^}}v7: ; CHECK-LABEL: {{^}}v7:
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9
define void @v7(i32 %a1) #0 { define amdgpu_shader void @v7(i32 %a1) #0 {
entry: entry:
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%2 = extractelement <4 x float> %1, i32 0 %2 = extractelement <4 x float> %1, i32 0
%3 = extractelement <4 x float> %1, i32 3 %3 = extractelement <4 x float> %1, i32 3
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
ret void ret void
} }
declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) readnone declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) readnone
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }

test/CodeGen/AMDGPU/llvm.SI.load.dword.ll

; RUN: llc -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
; Example of a simple geometry shader loading vertex attributes from the ; Example of a simple geometry shader loading vertex attributes from the
; ESGS ring buffer ; ESGS ring buffer
; FIXME: Out of bounds immediate offset crashes ; FIXME: Out of bounds immediate offset crashes
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: buffer_load_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc
; CHECK: s_movk_i32 [[K:s[0-9]+]], 0x4d2 ; encoding ; CHECK: s_movk_i32 [[K:s[0-9]+]], 0x4d2 ; encoding
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc
define void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <32 x i8>] addrspace(2)* byval %arg2, [2 x <16 x i8>] addrspace(2)* byval %arg3, [17 x <16 x i8>] addrspace(2)* inreg %arg4, [17 x <16 x i8>] addrspace(2)* inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9) #0 { define amdgpu_shader void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <32 x i8>] addrspace(2)* byval %arg2, [2 x <16 x i8>] addrspace(2)* byval %arg3, [17 x <16 x i8>] addrspace(2)* inreg %arg4, [17 x <16 x i8>] addrspace(2)* inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9) #0 {
main_body: main_body:
%tmp = getelementptr [2 x <16 x i8>], [2 x <16 x i8>] addrspace(2)* %arg3, i64 0, i32 1 %tmp = getelementptr [2 x <16 x i8>], [2 x <16 x i8>] addrspace(2)* %arg3, i64 0, i32 1
%tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp11 = shl i32 %arg6, 2 %tmp11 = shl i32 %arg6, 2
%tmp12 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0) %tmp12 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0)
%tmp13 = bitcast i32 %tmp12 to float %tmp13 = bitcast i32 %tmp12 to float
%tmp14 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp10, i32 %tmp11, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0) %tmp14 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp10, i32 %tmp11, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0)
%tmp15 = bitcast i32 %tmp14 to float %tmp15 = bitcast i32 %tmp14 to float
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test/CodeGen/AMDGPU/llvm.SI.sendmsg-m0.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=BOTH %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=BOTH %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=BOTH %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=BOTH %s
; BOTH-LABEL: {{^}}main: ; BOTH-LABEL: {{^}}main:
; BOTH: s_mov_b32 m0, s0 ; BOTH: s_mov_b32 m0, s0
; VI-NEXT: s_nop 0 ; VI-NEXT: s_nop 0
; BOTH-NEXT: s_sendmsg Gs_done(nop) ; BOTH-NEXT: s_sendmsg Gs_done(nop)
; BOTH-NEXT: s_endpgm ; BOTH-NEXT: s_endpgm
define void @main(i32 inreg %a) #0 { define amdgpu_shader void @main(i32 inreg %a) #0 {
main_body: main_body:
call void @llvm.SI.sendmsg(i32 3, i32 %a) call void @llvm.SI.sendmsg(i32 3, i32 %a)
ret void ret void
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
declare void @llvm.SI.sendmsg(i32, i32) #1 declare void @llvm.SI.sendmsg(i32, i32) #1
attributes #0 = { "ShaderType"="2" "unsafe-fp-math"="true" } attributes #0 = { "ShaderType"="2" "unsafe-fp-math"="true" }
attributes #1 = { nounwind } attributes #1 = { nounwind }

test/CodeGen/AMDGPU/llvm.SI.tbuffer.store.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
;CHECK-LABEL: {{^}}test1: ;CHECK-LABEL: {{^}}test1:
;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, 0x20, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 ;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, 0x20, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
define void @test1(i32 %a1, i32 %vaddr) #0 { define amdgpu_shader void @test1(i32 %a1, i32 %vaddr) #0 {
%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata, call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 1, i32 0, i32 1, i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 1, i32 0, i32 1,
i32 1, i32 0) i32 1, i32 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}test2: ;CHECK-LABEL: {{^}}test2:
;CHECK: tbuffer_store_format_xyz {{v\[[0-9]+:[0-9]+\]}}, 0x18, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 ;CHECK: tbuffer_store_format_xyz {{v\[[0-9]+:[0-9]+\]}}, 0x18, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
define void @test2(i32 %a1, i32 %vaddr) #0 { define amdgpu_shader void @test2(i32 %a1, i32 %vaddr) #0 {
%vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata, call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata,
i32 3, i32 %vaddr, i32 0, i32 24, i32 13, i32 4, i32 1, i32 0, i32 1, i32 3, i32 %vaddr, i32 0, i32 24, i32 13, i32 4, i32 1, i32 0, i32 1,
i32 1, i32 0) i32 1, i32 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}test3: ;CHECK-LABEL: {{^}}test3:
;CHECK: tbuffer_store_format_xy {{v\[[0-9]+:[0-9]+\]}}, 0x10, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 ;CHECK: tbuffer_store_format_xy {{v\[[0-9]+:[0-9]+\]}}, 0x10, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
define void @test3(i32 %a1, i32 %vaddr) #0 { define amdgpu_shader void @test3(i32 %a1, i32 %vaddr) #0 {
%vdata = insertelement <2 x i32> undef, i32 %a1, i32 0 %vdata = insertelement <2 x i32> undef, i32 %a1, i32 0
call void @llvm.SI.tbuffer.store.v2i32(<16 x i8> undef, <2 x i32> %vdata, call void @llvm.SI.tbuffer.store.v2i32(<16 x i8> undef, <2 x i32> %vdata,
i32 2, i32 %vaddr, i32 0, i32 16, i32 11, i32 4, i32 1, i32 0, i32 1, i32 2, i32 %vaddr, i32 0, i32 16, i32 11, i32 4, i32 1, i32 0, i32 1,
i32 1, i32 0) i32 1, i32 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}test4: ;CHECK-LABEL: {{^}}test4:
;CHECK: tbuffer_store_format_x {{v[0-9]+}}, 0x8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 ;CHECK: tbuffer_store_format_x {{v[0-9]+}}, 0x8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0
define void @test4(i32 %vdata, i32 %vaddr) #0 { define amdgpu_shader void @test4(i32 %vdata, i32 %vaddr) #0 {
call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata, call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata,
i32 1, i32 %vaddr, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 %vaddr, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1,
i32 1, i32 0) i32 1, i32 0)
ret void ret void
} }
declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
declare void @llvm.SI.tbuffer.store.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.tbuffer.store.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
declare void @llvm.SI.tbuffer.store.v4i32(<16 x i8>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.tbuffer.store.v4i32(<16 x i8>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
attributes #0 = { "ShaderType"="1" } attributes #0 = { "ShaderType"="1" }

test/CodeGen/AMDGPU/llvm.SI.tid.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s
;GCN: v_mbcnt_lo_u32_b32_e64 ;GCN: v_mbcnt_lo_u32_b32_e64
;SI: v_mbcnt_hi_u32_b32_e32 ;SI: v_mbcnt_hi_u32_b32_e32
;VI: v_mbcnt_hi_u32_b32_e64 ;VI: v_mbcnt_hi_u32_b32_e64
define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { define amdgpu_shader void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" {
main_body: main_body:
%4 = call i32 @llvm.SI.tid() %4 = call i32 @llvm.SI.tid()
%5 = bitcast i32 %4 to float %5 = bitcast i32 %4 to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5)
ret void ret void
} }
declare i32 @llvm.SI.tid() readnone declare i32 @llvm.SI.tid() readnone
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll

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;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc
;CHECK-DAG: s_waitcnt vmcnt(0) ;CHECK-DAG: s_waitcnt vmcnt(0)
;CHECK-DAG: s_movk_i32 [[SOFS:s[0-9]+]], 0x1fff ;CHECK-DAG: s_movk_i32 [[SOFS:s[0-9]+]], 0x1fff
;CHECK: buffer_atomic_swap v0, s[0:3], [[SOFS]] offset:1 glc ;CHECK: buffer_atomic_swap v0, s[0:3], [[SOFS]] offset:1 glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_swap v0, s[0:3], 0{{$}} ;CHECK: buffer_atomic_swap v0, s[0:3], 0{{$}}
define float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex, i32 %voffset) #0 { define amdgpu_shader float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex, i32 %voffset) #0 {
main_body: main_body:
%o1 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0) %o1 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
%o2 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %o2 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
%o3 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0) %o3 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0)
%o4 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0) %o4 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0)
%ofs.5 = add i32 %voffset, 42 %ofs.5 = add i32 %voffset, 42
%o5 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0) %o5 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0)
%o6 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0) %o6 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
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;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc ;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 idxen glc ;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 idxen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 idxen glc ;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 idxen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_xor v0, v1, s[0:3], 0 idxen glc ;CHECK: buffer_atomic_xor v0, v1, s[0:3], 0 idxen glc
define float @test2(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) #0 { define amdgpu_shader float @test2(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) #0 {
main_body: main_body:
%t1 = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %t1 = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
%t2 = call i32 @llvm.amdgcn.buffer.atomic.sub(i32 %t1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %t2 = call i32 @llvm.amdgcn.buffer.atomic.sub(i32 %t1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
%t3 = call i32 @llvm.amdgcn.buffer.atomic.smin(i32 %t2, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %t3 = call i32 @llvm.amdgcn.buffer.atomic.smin(i32 %t2, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
%t4 = call i32 @llvm.amdgcn.buffer.atomic.umin(i32 %t3, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %t4 = call i32 @llvm.amdgcn.buffer.atomic.umin(i32 %t3, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
%t5 = call i32 @llvm.amdgcn.buffer.atomic.smax(i32 %t4, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %t5 = call i32 @llvm.amdgcn.buffer.atomic.smax(i32 %t4, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
%t6 = call i32 @llvm.amdgcn.buffer.atomic.umax(i32 %t5, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %t6 = call i32 @llvm.amdgcn.buffer.atomic.umax(i32 %t5, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
%t7 = call i32 @llvm.amdgcn.buffer.atomic.and(i32 %t6, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %t7 = call i32 @llvm.amdgcn.buffer.atomic.and(i32 %t6, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v[2:3], s[0:3], 0 idxen offen glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v[2:3], s[0:3], 0 idxen offen glc
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen offset:42 glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen offset:42 glc
;CHECK-DAG: s_waitcnt vmcnt(0) ;CHECK-DAG: s_waitcnt vmcnt(0)
;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[SOFS]] offset:1 glc ;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[SOFS]] offset:1 glc
define float @test3(<4 x i32> inreg %rsrc, i32 %data, i32 %cmp, i32 %vindex, i32 %voffset) #0 { define amdgpu_shader float @test3(<4 x i32> inreg %rsrc, i32 %data, i32 %cmp, i32 %vindex, i32 %voffset) #0 {
main_body: main_body:
%o1 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0) %o1 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
%o2 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o1, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) %o2 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o1, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
%o3 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o2, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0) %o3 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o2, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0)
%o4 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o3, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0) %o4 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o3, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0)
%ofs.5 = add i32 %voffset, 42 %ofs.5 = add i32 %voffset, 42
%o5 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o4, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0) %o5 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o4, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0)
%o6 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o5, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 8192, i1 0) %o6 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o5, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
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test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
;CHECK-LABEL: {{^}}buffer_load: ;CHECK-LABEL: {{^}}buffer_load:
;CHECK: buffer_load_format_xyzw v[0:3], s[0:3], 0 ;CHECK: buffer_load_format_xyzw v[0:3], s[0:3], 0
;CHECK: buffer_load_format_xyzw v[4:7], s[0:3], 0 glc ;CHECK: buffer_load_format_xyzw v[4:7], s[0:3], 0 glc
;CHECK: buffer_load_format_xyzw v[8:11], s[0:3], 0 slc ;CHECK: buffer_load_format_xyzw v[8:11], s[0:3], 0 slc
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) #0 { define amdgpu_shader {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
%data_glc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0) %data_glc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
%data_slc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1) %data_slc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2 ret {<4 x float>, <4 x float>, <4 x float>} %r2
} }
;CHECK-LABEL: {{^}}buffer_load_immoffs: ;CHECK-LABEL: {{^}}buffer_load_immoffs:
;CHECK: buffer_load_format_xyzw v[0:3], s[0:3], 0 offset:42 ;CHECK: buffer_load_format_xyzw v[0:3], s[0:3], 0 offset:42
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_immoffs(<4 x i32> inreg) #0 { define amdgpu_shader <4 x float> @buffer_load_immoffs(<4 x i32> inreg) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_immoffs_large: ;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 61 offset:4095 ;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 61 offset:4095
;CHECK-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7fff ;CHECK-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7fff
;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS1]] offset:4093 ;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS1]] offset:4093
;CHECK: s_mov_b32 [[OFS2:s[0-9]+]], 0x8fff ;CHECK: s_mov_b32 [[OFS2:s[0-9]+]], 0x8fff
;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS2]] offset:1 ;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS2]] offset:1
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) #0 { define amdgpu_shader <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) #0 {
main_body: main_body:
%d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4156, i1 0, i1 0) %d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4156, i1 0, i1 0)
%d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36860, i1 0, i1 0) %d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36860, i1 0, i1 0)
%d.2 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36864, i1 0, i1 0) %d.2 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36864, i1 0, i1 0)
%d.3 = fadd <4 x float> %d.0, %d.1 %d.3 = fadd <4 x float> %d.0, %d.1
%data = fadd <4 x float> %d.2, %d.3 %data = fadd <4 x float> %d.2, %d.3
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_immoffs_reuse: ;CHECK-LABEL: {{^}}buffer_load_immoffs_reuse:
;CHECK: s_movk_i32 [[OFS:s[0-9]+]], 0xfff ;CHECK: s_movk_i32 [[OFS:s[0-9]+]], 0xfff
;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS]] offset:65 ;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS]] offset:65
;CHECK-NOT: s_mov ;CHECK-NOT: s_mov
;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS]] offset:81 ;CHECK: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, s[0:3], [[OFS]] offset:81
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_immoffs_reuse(<4 x i32> inreg) #0 { define amdgpu_shader <4 x float> @buffer_load_immoffs_reuse(<4 x i32> inreg) #0 {
main_body: main_body:
%d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4160, i1 0, i1 0) %d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4160, i1 0, i1 0)
%d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4176, i1 0, i1 0) %d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4176, i1 0, i1 0)
%data = fadd <4 x float> %d.0, %d.1 %data = fadd <4 x float> %d.0, %d.1
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_idx: ;CHECK-LABEL: {{^}}buffer_load_idx:
;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen ;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_ofs: ;CHECK-LABEL: {{^}}buffer_load_ofs:
;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen ;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_ofs_imm: ;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen offset:58 ;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen offset:58
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) #0 {
main_body: main_body:
%ofs = add i32 %1, 58 %ofs = add i32 %1, 58
%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_both: ;CHECK-LABEL: {{^}}buffer_load_both:
;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen ;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_both_reversed: ;CHECK-LABEL: {{^}}buffer_load_both_reversed:
;CHECK: v_mov_b32_e32 v2, v0 ;CHECK: v_mov_b32_e32 v2, v0
;CHECK: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen ;CHECK: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_x: ;CHECK-LABEL: {{^}}buffer_load_x:
;CHECK: buffer_load_format_x v0, s[0:3], 0 ;CHECK: buffer_load_format_x v0, s[0:3], 0
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define float @buffer_load_x(<4 x i32> inreg %rsrc) #0 { define amdgpu_shader float @buffer_load_x(<4 x i32> inreg %rsrc) #0 {
main_body: main_body:
%data = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) %data = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
ret float %data ret float %data
} }
;CHECK-LABEL: {{^}}buffer_load_xy: ;CHECK-LABEL: {{^}}buffer_load_xy:
;CHECK: buffer_load_format_xy v[0:1], s[0:3], 0 ;CHECK: buffer_load_format_xy v[0:1], s[0:3], 0
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) #0 { define amdgpu_shader <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) #0 {
main_body: main_body:
%data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
ret <2 x float> %data ret <2 x float> %data
} }
declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1 declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1
declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #1 declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #1
declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1 declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readonly } attributes #1 = { nounwind readonly }

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
;CHECK-LABEL: {{^}}buffer_load: ;CHECK-LABEL: {{^}}buffer_load:
;CHECK: buffer_load_dwordx4 v[0:3], s[0:3], 0 ;CHECK: buffer_load_dwordx4 v[0:3], s[0:3], 0
;CHECK: buffer_load_dwordx4 v[4:7], s[0:3], 0 glc ;CHECK: buffer_load_dwordx4 v[4:7], s[0:3], 0 glc
;CHECK: buffer_load_dwordx4 v[8:11], s[0:3], 0 slc ;CHECK: buffer_load_dwordx4 v[8:11], s[0:3], 0 slc
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) #0 { define amdgpu_shader {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
%data_glc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0) %data_glc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
%data_slc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1) %data_slc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2 ret {<4 x float>, <4 x float>, <4 x float>} %r2
} }
;CHECK-LABEL: {{^}}buffer_load_immoffs: ;CHECK-LABEL: {{^}}buffer_load_immoffs:
;CHECK: buffer_load_dwordx4 v[0:3], s[0:3], 0 offset:42 ;CHECK: buffer_load_dwordx4 v[0:3], s[0:3], 0 offset:42
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_immoffs(<4 x i32> inreg) #0 { define amdgpu_shader <4 x float> @buffer_load_immoffs(<4 x i32> inreg) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_immoffs_large: ;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1fff ;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1fff
;CHECK: buffer_load_dwordx4 v[0:3], s[0:3], [[OFFSET]] offset:1 ;CHECK: buffer_load_dwordx4 v[0:3], s[0:3], [[OFFSET]] offset:1
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) #0 { define amdgpu_shader <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 8192, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 8192, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_idx: ;CHECK-LABEL: {{^}}buffer_load_idx:
;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_ofs: ;CHECK-LABEL: {{^}}buffer_load_ofs:
;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_ofs_imm: ;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:58 ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:58
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) #0 {
main_body: main_body:
%ofs = add i32 %1, 58 %ofs = add i32 %1, 58
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_both: ;CHECK-LABEL: {{^}}buffer_load_both:
;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_both_reversed: ;CHECK-LABEL: {{^}}buffer_load_both_reversed:
;CHECK: v_mov_b32_e32 v2, v0 ;CHECK: v_mov_b32_e32 v2, v0
;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen ;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) #0 { define amdgpu_shader <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) #0 {
main_body: main_body:
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0)
ret <4 x float> %data ret <4 x float> %data
} }
;CHECK-LABEL: {{^}}buffer_load_x1: ;CHECK-LABEL: {{^}}buffer_load_x1:
;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen ;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_shader float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
main_body: main_body:
%data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0) %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0)
ret float %data ret float %data
} }
;CHECK-LABEL: {{^}}buffer_load_x2: ;CHECK-LABEL: {{^}}buffer_load_x2:
;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen ;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen
;CHECK: s_waitcnt ;CHECK: s_waitcnt
define <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_shader <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
main_body: main_body:
%data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0) %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0)
ret <2 x float> %data ret <2 x float> %data
} }
declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #1 declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #1
declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #1 declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #1
declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1 declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readonly } attributes #1 = { nounwind readonly }

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
;CHECK-LABEL: {{^}}buffer_store: ;CHECK-LABEL: {{^}}buffer_store:
;CHECK: buffer_store_format_xyzw v[0:3], s[0:3], 0 ;CHECK: buffer_store_format_xyzw v[0:3], s[0:3], 0
;CHECK: buffer_store_format_xyzw v[4:7], s[0:3], 0 glc ;CHECK: buffer_store_format_xyzw v[4:7], s[0:3], 0 glc
;CHECK: buffer_store_format_xyzw v[8:11], s[0:3], 0 slc ;CHECK: buffer_store_format_xyzw v[8:11], s[0:3], 0 slc
define void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) #0 { define amdgpu_shader void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_immoffs: ;CHECK-LABEL: {{^}}buffer_store_immoffs:
;CHECK: buffer_store_format_xyzw v[0:3], s[0:3], 0 offset:42 ;CHECK: buffer_store_format_xyzw v[0:3], s[0:3], 0 offset:42
define void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) #0 { define amdgpu_shader void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_idx: ;CHECK-LABEL: {{^}}buffer_store_idx:
;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
define void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) #0 { define amdgpu_shader void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_ofs: ;CHECK-LABEL: {{^}}buffer_store_ofs:
;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen
define void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) #0 { define amdgpu_shader void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_both: ;CHECK-LABEL: {{^}}buffer_store_both:
;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen ;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
define void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) #0 { define amdgpu_shader void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_both_reversed: ;CHECK-LABEL: {{^}}buffer_store_both_reversed:
;CHECK: v_mov_b32_e32 v6, v4 ;CHECK: v_mov_b32_e32 v6, v4
;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen ;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
define void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) #0 { define amdgpu_shader void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0)
ret void ret void
} }
; Ideally, the register allocator would avoid the wait here ; Ideally, the register allocator would avoid the wait here
; ;
;CHECK-LABEL: {{^}}buffer_store_wait: ;CHECK-LABEL: {{^}}buffer_store_wait:
;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
;CHECK: s_waitcnt vmcnt(0) expcnt(0) ;CHECK: s_waitcnt vmcnt(0) expcnt(0)
;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen ;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen ;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
define void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) #0 { define amdgpu_shader void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
%data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0)
call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_x1: ;CHECK-LABEL: {{^}}buffer_store_x1:
;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen ;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen
define void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) #0 { define amdgpu_shader void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_x2: ;CHECK-LABEL: {{^}}buffer_store_x2:
;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen ;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen
define void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 { define amdgpu_shader void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
ret void ret void
} }
declare void @llvm.amdgcn.buffer.store.format.f32(float, <4 x i32>, i32, i32, i1, i1) #1 declare void @llvm.amdgcn.buffer.store.format.f32(float, <4 x i32>, i32, i32, i1, i1) #1
declare void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #1 declare void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #1
declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #1 declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #1
declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2 declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind } attributes #1 = { nounwind }
attributes #2 = { nounwind readonly } attributes #2 = { nounwind readonly }

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
;CHECK-LABEL: {{^}}buffer_store: ;CHECK-LABEL: {{^}}buffer_store:
;CHECK: buffer_store_dwordx4 v[0:3], s[0:3], 0 ;CHECK: buffer_store_dwordx4 v[0:3], s[0:3], 0
;CHECK: buffer_store_dwordx4 v[4:7], s[0:3], 0 glc ;CHECK: buffer_store_dwordx4 v[4:7], s[0:3], 0 glc
;CHECK: buffer_store_dwordx4 v[8:11], s[0:3], 0 slc ;CHECK: buffer_store_dwordx4 v[8:11], s[0:3], 0 slc
define void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) #0 { define amdgpu_shader void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_immoffs: ;CHECK-LABEL: {{^}}buffer_store_immoffs:
;CHECK: buffer_store_dwordx4 v[0:3], s[0:3], 0 offset:42 ;CHECK: buffer_store_dwordx4 v[0:3], s[0:3], 0 offset:42
define void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) #0 { define amdgpu_shader void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_idx: ;CHECK-LABEL: {{^}}buffer_store_idx:
;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
define void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) #0 { define amdgpu_shader void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_ofs: ;CHECK-LABEL: {{^}}buffer_store_ofs:
;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen
define void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) #0 { define amdgpu_shader void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_both: ;CHECK-LABEL: {{^}}buffer_store_both:
;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen ;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
define void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) #0 { define amdgpu_shader void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_both_reversed: ;CHECK-LABEL: {{^}}buffer_store_both_reversed:
;CHECK: v_mov_b32_e32 v6, v4 ;CHECK: v_mov_b32_e32 v6, v4
;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen ;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
define void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) #0 { define amdgpu_shader void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0)
ret void ret void
} }
; Ideally, the register allocator would avoid the wait here ; Ideally, the register allocator would avoid the wait here
; ;
;CHECK-LABEL: {{^}}buffer_store_wait: ;CHECK-LABEL: {{^}}buffer_store_wait:
;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
;CHECK: s_waitcnt vmcnt(0) expcnt(0) ;CHECK: s_waitcnt vmcnt(0) expcnt(0)
;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen ;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen ;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
define void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) #0 { define amdgpu_shader void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0)
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_x1: ;CHECK-LABEL: {{^}}buffer_store_x1:
;CHECK: buffer_store_dword v0, v1, s[0:3], 0 idxen ;CHECK: buffer_store_dword v0, v1, s[0:3], 0 idxen
define void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) #0 { define amdgpu_shader void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}buffer_store_x2: ;CHECK-LABEL: {{^}}buffer_store_x2:
;CHECK: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen ;CHECK: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
define void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 { define amdgpu_shader void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 {
main_body: main_body:
call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
ret void ret void
} }
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1 declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1
declare void @llvm.amdgcn.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #1 declare void @llvm.amdgcn.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #1
declare void @llvm.amdgcn.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #1 declare void @llvm.amdgcn.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #1
declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #2 declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #2
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind } attributes #1 = { nounwind }
attributes #2 = { nounwind readonly } attributes #2 = { nounwind readonly }

test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI ;RUN: llc < %s -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI
;RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI ;RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI
;CHECK-LABEL: {{^}}image_atomic_swap: ;CHECK-LABEL: {{^}}image_atomic_swap:
;SI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x04,0x00,0x00] ;SI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x04,0x00,0x00]
;VI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x04,0x00,0x00] ;VI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x04,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define float @image_atomic_swap(<8 x i32> inreg, <4 x i32>, i32) #0 { define amdgpu_shader float @image_atomic_swap(<8 x i32> inreg, <4 x i32>, i32) #0 {
main_body: main_body:
%orig = call i32 @llvm.amdgcn.image.atomic.swap.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %orig = call i32 @llvm.amdgcn.image.atomic.swap.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%orig.f = bitcast i32 %orig to float %orig.f = bitcast i32 %orig to float
ret float %orig.f ret float %orig.f
} }
;CHECK-LABEL: {{^}}image_atomic_swap_v2i32: ;CHECK-LABEL: {{^}}image_atomic_swap_v2i32:
;SI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x02,0x00,0x00] ;SI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x02,0x00,0x00]
;VI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x02,0x00,0x00] ;VI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x02,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define float @image_atomic_swap_v2i32(<8 x i32> inreg, <2 x i32>, i32) #0 { define amdgpu_shader float @image_atomic_swap_v2i32(<8 x i32> inreg, <2 x i32>, i32) #0 {
main_body: main_body:
%orig = call i32 @llvm.amdgcn.image.atomic.swap.v2i32(i32 %2, <2 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %orig = call i32 @llvm.amdgcn.image.atomic.swap.v2i32(i32 %2, <2 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%orig.f = bitcast i32 %orig to float %orig.f = bitcast i32 %orig to float
ret float %orig.f ret float %orig.f
} }
;CHECK-LABEL: {{^}}image_atomic_swap_i32: ;CHECK-LABEL: {{^}}image_atomic_swap_i32:
;SI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x01,0x00,0x00] ;SI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x01,0x00,0x00]
;VI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x01,0x00,0x00] ;VI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x01,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define float @image_atomic_swap_i32(<8 x i32> inreg, i32, i32) #0 { define amdgpu_shader float @image_atomic_swap_i32(<8 x i32> inreg, i32, i32) #0 {
main_body: main_body:
%orig = call i32 @llvm.amdgcn.image.atomic.swap.i32(i32 %2, i32 %1, <8 x i32> %0, i1 0, i1 0, i1 0) %orig = call i32 @llvm.amdgcn.image.atomic.swap.i32(i32 %2, i32 %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%orig.f = bitcast i32 %orig to float %orig.f = bitcast i32 %orig to float
ret float %orig.f ret float %orig.f
} }
;CHECK-LABEL: {{^}}image_atomic_cmpswap: ;CHECK-LABEL: {{^}}image_atomic_cmpswap:
;SI: image_atomic_cmpswap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x40,0xf0,0x00,0x04,0x00,0x00] ;SI: image_atomic_cmpswap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x40,0xf0,0x00,0x04,0x00,0x00]
;VI: image_atomic_cmpswap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x44,0xf0,0x00,0x04,0x00,0x00] ;VI: image_atomic_cmpswap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x44,0xf0,0x00,0x04,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: v_mov_b32_e32 v0, v4 ;CHECK: v_mov_b32_e32 v0, v4
define float @image_atomic_cmpswap(<8 x i32> inreg, <4 x i32>, i32, i32) #0 { define amdgpu_shader float @image_atomic_cmpswap(<8 x i32> inreg, <4 x i32>, i32, i32) #0 {
main_body: main_body:
%orig = call i32 @llvm.amdgcn.image.atomic.cmpswap.v4i32(i32 %2, i32 %3, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %orig = call i32 @llvm.amdgcn.image.atomic.cmpswap.v4i32(i32 %2, i32 %3, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%orig.f = bitcast i32 %orig to float %orig.f = bitcast i32 %orig to float
ret float %orig.f ret float %orig.f
} }
;CHECK-LABEL: {{^}}image_atomic_add: ;CHECK-LABEL: {{^}}image_atomic_add:
;SI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0x00,0x04,0x00,0x00] ;SI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0x00,0x04,0x00,0x00]
;VI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x00,0x04,0x00,0x00] ;VI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x00,0x04,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define float @image_atomic_add(<8 x i32> inreg, <4 x i32>, i32) #0 { define amdgpu_shader float @image_atomic_add(<8 x i32> inreg, <4 x i32>, i32) #0 {
main_body: main_body:
%orig = call i32 @llvm.amdgcn.image.atomic.add.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %orig = call i32 @llvm.amdgcn.image.atomic.add.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%orig.f = bitcast i32 %orig to float %orig.f = bitcast i32 %orig to float
ret float %orig.f ret float %orig.f
} }
;CHECK-LABEL: {{^}}image_atomic_sub: ;CHECK-LABEL: {{^}}image_atomic_sub:
;SI: image_atomic_sub v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x00,0x04,0x00,0x00] ;SI: image_atomic_sub v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x00,0x04,0x00,0x00]
;VI: image_atomic_sub v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x4c,0xf0,0x00,0x04,0x00,0x00] ;VI: image_atomic_sub v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x4c,0xf0,0x00,0x04,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define float @image_atomic_sub(<8 x i32> inreg, <4 x i32>, i32) #0 { define amdgpu_shader float @image_atomic_sub(<8 x i32> inreg, <4 x i32>, i32) #0 {
main_body: main_body:
%orig = call i32 @llvm.amdgcn.image.atomic.sub.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %orig = call i32 @llvm.amdgcn.image.atomic.sub.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%orig.f = bitcast i32 %orig to float %orig.f = bitcast i32 %orig to float
ret float %orig.f ret float %orig.f
} }
;CHECK-LABEL: {{^}}image_atomic_unchanged: ;CHECK-LABEL: {{^}}image_atomic_unchanged:
;CHECK: image_atomic_smin v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x50,0xf0,0x00,0x04,0x00,0x00] ;CHECK: image_atomic_smin v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x50,0xf0,0x00,0x04,0x00,0x00]
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;CHECK: image_atomic_or v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x64,0xf0,0x00,0x04,0x00,0x00] ;CHECK: image_atomic_or v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x64,0xf0,0x00,0x04,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: image_atomic_xor v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x68,0xf0,0x00,0x04,0x00,0x00] ;CHECK: image_atomic_xor v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x68,0xf0,0x00,0x04,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: image_atomic_inc v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x6c,0xf0,0x00,0x04,0x00,0x00] ;CHECK: image_atomic_inc v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x6c,0xf0,0x00,0x04,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: image_atomic_dec v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x70,0xf0,0x00,0x04,0x00,0x00] ;CHECK: image_atomic_dec v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x70,0xf0,0x00,0x04,0x00,0x00]
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define float @image_atomic_unchanged(<8 x i32> inreg, <4 x i32>, i32) #0 { define amdgpu_shader float @image_atomic_unchanged(<8 x i32> inreg, <4 x i32>, i32) #0 {
main_body: main_body:
%t0 = call i32 @llvm.amdgcn.image.atomic.smin.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %t0 = call i32 @llvm.amdgcn.image.atomic.smin.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%t1 = call i32 @llvm.amdgcn.image.atomic.umin.v4i32(i32 %t0, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %t1 = call i32 @llvm.amdgcn.image.atomic.umin.v4i32(i32 %t0, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%t2 = call i32 @llvm.amdgcn.image.atomic.smax.v4i32(i32 %t1, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %t2 = call i32 @llvm.amdgcn.image.atomic.smax.v4i32(i32 %t1, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%t3 = call i32 @llvm.amdgcn.image.atomic.umax.v4i32(i32 %t2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %t3 = call i32 @llvm.amdgcn.image.atomic.umax.v4i32(i32 %t2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%t4 = call i32 @llvm.amdgcn.image.atomic.and.v4i32(i32 %t3, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %t4 = call i32 @llvm.amdgcn.image.atomic.and.v4i32(i32 %t3, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%t5 = call i32 @llvm.amdgcn.image.atomic.or.v4i32(i32 %t4, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %t5 = call i32 @llvm.amdgcn.image.atomic.or.v4i32(i32 %t4, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
%t6 = call i32 @llvm.amdgcn.image.atomic.xor.v4i32(i32 %t5, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) %t6 = call i32 @llvm.amdgcn.image.atomic.xor.v4i32(i32 %t5, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0)
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test/CodeGen/AMDGPU/llvm.amdgcn.image.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
;CHECK-LABEL: {{^}}image_load_v4i32: ;CHECK-LABEL: {{^}}image_load_v4i32:
;CHECK: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm ;CHECK: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define <4 x float> @image_load_v4i32(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 { define amdgpu_shader <4 x float> @image_load_v4i32(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) %tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret <4 x float> %tex ret <4 x float> %tex
} }
;CHECK-LABEL: {{^}}image_load_v2i32: ;CHECK-LABEL: {{^}}image_load_v2i32:
;CHECK: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm ;CHECK: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define <4 x float> @image_load_v2i32(<8 x i32> inreg %rsrc, <2 x i32> %c) #0 { define amdgpu_shader <4 x float> @image_load_v2i32(<8 x i32> inreg %rsrc, <2 x i32> %c) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.amdgcn.image.load.v2i32(<2 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) %tex = call <4 x float> @llvm.amdgcn.image.load.v2i32(<2 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret <4 x float> %tex ret <4 x float> %tex
} }
;CHECK-LABEL: {{^}}image_load_i32: ;CHECK-LABEL: {{^}}image_load_i32:
;CHECK: image_load v[0:3], v0, s[0:7] dmask:0xf unorm ;CHECK: image_load v[0:3], v0, s[0:7] dmask:0xf unorm
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define <4 x float> @image_load_i32(<8 x i32> inreg %rsrc, i32 %c) #0 { define amdgpu_shader <4 x float> @image_load_i32(<8 x i32> inreg %rsrc, i32 %c) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) %tex = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret <4 x float> %tex ret <4 x float> %tex
} }
;CHECK-LABEL: {{^}}image_load_mip: ;CHECK-LABEL: {{^}}image_load_mip:
;CHECK: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm ;CHECK: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define <4 x float> @image_load_mip(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 { define amdgpu_shader <4 x float> @image_load_mip(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) %tex = call <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret <4 x float> %tex ret <4 x float> %tex
} }
;CHECK-LABEL: {{^}}image_load_1: ;CHECK-LABEL: {{^}}image_load_1:
;CHECK: image_load v0, v[0:3], s[0:7] dmask:0x1 unorm ;CHECK: image_load v0, v[0:3], s[0:7] dmask:0x1 unorm
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
define float @image_load_1(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 { define amdgpu_shader float @image_load_1(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) %tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
%elt = extractelement <4 x float> %tex, i32 0 %elt = extractelement <4 x float> %tex, i32 0
; Only first component used, test that dmask etc. is changed accordingly ; Only first component used, test that dmask etc. is changed accordingly
ret float %elt ret float %elt
} }
;CHECK-LABEL: {{^}}image_store_v4i32: ;CHECK-LABEL: {{^}}image_store_v4i32:
;CHECK: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm ;CHECK: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm
define void @image_store_v4i32(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 { define amdgpu_shader void @image_store_v4i32(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 {
main_body: main_body:
call void @llvm.amdgcn.image.store.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) call void @llvm.amdgcn.image.store.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}image_store_v2i32: ;CHECK-LABEL: {{^}}image_store_v2i32:
;CHECK: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm ;CHECK: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm
define void @image_store_v2i32(<8 x i32> inreg %rsrc, <4 x float> %data, <2 x i32> %coords) #0 { define amdgpu_shader void @image_store_v2i32(<8 x i32> inreg %rsrc, <4 x float> %data, <2 x i32> %coords) #0 {
main_body: main_body:
call void @llvm.amdgcn.image.store.v2i32(<4 x float> %data, <2 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) call void @llvm.amdgcn.image.store.v2i32(<4 x float> %data, <2 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}image_store_i32: ;CHECK-LABEL: {{^}}image_store_i32:
;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm ;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
define void @image_store_i32(<8 x i32> inreg %rsrc, <4 x float> %data, i32 %coords) #0 { define amdgpu_shader void @image_store_i32(<8 x i32> inreg %rsrc, <4 x float> %data, i32 %coords) #0 {
main_body: main_body:
call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret void ret void
} }
;CHECK-LABEL: {{^}}image_store_mip: ;CHECK-LABEL: {{^}}image_store_mip:
;CHECK: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm ;CHECK: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm
define void @image_store_mip(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 { define amdgpu_shader void @image_store_mip(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 {
main_body: main_body:
call void @llvm.amdgcn.image.store.mip.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) call void @llvm.amdgcn.image.store.mip.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret void ret void
} }
; Ideally, the register allocator would avoid the wait here ; Ideally, the register allocator would avoid the wait here
; ;
;CHECK-LABEL: {{^}}image_store_wait: ;CHECK-LABEL: {{^}}image_store_wait:
;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm ;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
;CHECK: s_waitcnt vmcnt(0) expcnt(0) ;CHECK: s_waitcnt vmcnt(0) expcnt(0)
;CHECK: image_load v[0:3], v4, s[8:15] dmask:0xf unorm ;CHECK: image_load v[0:3], v4, s[8:15] dmask:0xf unorm
;CHECK: s_waitcnt vmcnt(0) ;CHECK: s_waitcnt vmcnt(0)
;CHECK: image_store v[0:3], v4, s[16:23] dmask:0xf unorm ;CHECK: image_store v[0:3], v4, s[16:23] dmask:0xf unorm
define void @image_store_wait(<8 x i32> inreg, <8 x i32> inreg, <8 x i32> inreg, <4 x float>, i32) #0 { define amdgpu_shader void @image_store_wait(<8 x i32> inreg, <8 x i32> inreg, <8 x i32> inreg, <4 x float>, i32) #0 {
main_body: main_body:
call void @llvm.amdgcn.image.store.i32(<4 x float> %3, i32 %4, <8 x i32> %0, i32 15, i1 0, i1 0, i1 0, i1 0) call void @llvm.amdgcn.image.store.i32(<4 x float> %3, i32 %4, <8 x i32> %0, i32 15, i1 0, i1 0, i1 0, i1 0)
%data = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %4, <8 x i32> %1, i32 15, i1 0, i1 0, i1 0, i1 0) %data = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %4, <8 x i32> %1, i32 15, i1 0, i1 0, i1 0, i1 0)
call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %4, <8 x i32> %2, i32 15, i1 0, i1 0, i1 0, i1 0) call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %4, <8 x i32> %2, i32 15, i1 0, i1 0, i1 0, i1 0)
ret void ret void
} }
declare void @llvm.amdgcn.image.store.i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #1 declare void @llvm.amdgcn.image.store.i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #1
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test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
;GCN-LABEL: {{^}}v_interp: ;GCN-LABEL: {{^}}v_interp:
;GCN-NOT: s_wqm ;GCN-NOT: s_wqm
;GCN: s_mov_b32 m0, s{{[0-9]+}} ;GCN: s_mov_b32 m0, s{{[0-9]+}}
;GCN: v_interp_p1_f32 ;GCN: v_interp_p1_f32
;GCN: v_interp_p2_f32 ;GCN: v_interp_p2_f32
define void @v_interp(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 { define amdgpu_shader void @v_interp(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 {
main_body: main_body:
%i = extractelement <2 x i32> %4, i32 0 %i = extractelement <2 x i32> %4, i32 0
%j = extractelement <2 x i32> %4, i32 1 %j = extractelement <2 x i32> %4, i32 1
%p0_0 = call float @llvm.amdgcn.interp.p1(i32 %i, i32 0, i32 0, i32 %3) %p0_0 = call float @llvm.amdgcn.interp.p1(i32 %i, i32 0, i32 0, i32 %3)
%p1_0 = call float @llvm.amdgcn.interp.p2(float %p0_0, i32 %j, i32 0, i32 0, i32 %3) %p1_0 = call float @llvm.amdgcn.interp.p2(float %p0_0, i32 %j, i32 0, i32 0, i32 %3)
%p0_1 = call float @llvm.amdgcn.interp.p1(i32 %i, i32 1, i32 0, i32 %3) %p0_1 = call float @llvm.amdgcn.interp.p1(i32 %i, i32 1, i32 0, i32 %3)
%p1_1 = call float @llvm.amdgcn.interp.p2(float %p0_1, i32 %j, i32 1, i32 0, i32 %3) %p1_1 = call float @llvm.amdgcn.interp.p2(float %p0_1, i32 %j, i32 1, i32 0, i32 %3)
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %p0_0, float %p0_0, float %p1_1, float %p1_1) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %p0_0, float %p0_0, float %p1_1, float %p1_1)
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test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s
;GCN-LABEL: {{^}}mbcnt_intrinsics: ;GCN-LABEL: {{^}}mbcnt_intrinsics:
;GCN: v_mbcnt_lo_u32_b32_e64 [[LO:v[0-9]+]], -1, 0 ;GCN: v_mbcnt_lo_u32_b32_e64 [[LO:v[0-9]+]], -1, 0
;SI: v_mbcnt_hi_u32_b32_e32 {{v[0-9]+}}, -1, [[LO]] ;SI: v_mbcnt_hi_u32_b32_e32 {{v[0-9]+}}, -1, [[LO]]
;VI: v_mbcnt_hi_u32_b32_e64 {{v[0-9]+}}, -1, [[LO]] ;VI: v_mbcnt_hi_u32_b32_e64 {{v[0-9]+}}, -1, [[LO]]
define void @mbcnt_intrinsics(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { define amdgpu_shader void @mbcnt_intrinsics(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" {
main_body: main_body:
%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) #1 %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) #1
%4 = bitcast i32 %hi to float %4 = bitcast i32 %hi to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %4, float %4, float %4, float %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %4, float %4, float %4, float %4)
ret void ret void
} }
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/AMDGPU/llvm.pow.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK-LABEL: test1: ;CHECK-LABEL: test1:
;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, ;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
define void @test1(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test1(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0 %r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1 %r1 = extractelement <4 x float> %reg0, i32 1
%r2 = call float @llvm.pow.f32( float %r0, float %r1) %r2 = call float @llvm.pow.f32( float %r0, float %r1)
%vec = insertelement <4 x float> undef, float %r2, i32 0 %vec = insertelement <4 x float> undef, float %r2, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
;CHECK-LABEL: test2: ;CHECK-LABEL: test2:
;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, ;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, ;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, ;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, ;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_shader void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
%vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1) %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
declare float @llvm.pow.f32(float ,float ) readonly declare float @llvm.pow.f32(float ,float ) readonly
declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }

test/CodeGen/AMDGPU/load-input-fold.ll

;RUN: llc < %s -march=r600 -mcpu=cayman ;RUN: llc < %s -march=r600 -mcpu=cayman
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = extractelement <4 x float> %reg2, i32 0 %4 = extractelement <4 x float> %reg2, i32 0
%5 = extractelement <4 x float> %reg2, i32 1 %5 = extractelement <4 x float> %reg2, i32 1
%6 = extractelement <4 x float> %reg2, i32 2 %6 = extractelement <4 x float> %reg2, i32 2
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test/CodeGen/AMDGPU/m0-spill.ll

; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
@lds = external addrspace(3) global [64 x float] @lds = external addrspace(3) global [64 x float]
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK-NOT: v_readlane_b32 m0 ; CHECK-NOT: v_readlane_b32 m0
define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { define amdgpu_shader void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" {
main_body: main_body:
%4 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) %4 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
%cmp = fcmp ueq float 0.0, %4 %cmp = fcmp ueq float 0.0, %4
br i1 %cmp, label %if, label %else br i1 %cmp, label %if, label %else
if: if:
%lds_ptr = getelementptr [64 x float], [64 x float] addrspace(3)* @lds, i32 0, i32 0 %lds_ptr = getelementptr [64 x float], [64 x float] addrspace(3)* @lds, i32 0, i32 0
%lds_data = load float, float addrspace(3)* %lds_ptr %lds_data = load float, float addrspace(3)* %lds_ptr
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test/CodeGen/AMDGPU/max-literals.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: ADD * ; CHECK: ADD *
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = extractelement <4 x float> %reg2, i32 0 %4 = extractelement <4 x float> %reg2, i32 0
%5 = fadd float %0, 2.0 %5 = fadd float %0, 2.0
%6 = fadd float %1, 3.0 %6 = fadd float %1, 3.0
Show All 12 Linesmain_body:
%18 = insertelement <4 x float> undef, float %17, i32 0 %18 = insertelement <4 x float> undef, float %17, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2)
ret void ret void
} }
; CHECK-LABEL: {{^}}main2: ; CHECK-LABEL: {{^}}main2:
; CHECK-NOT: ADD * ; CHECK-NOT: ADD *
define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { define amdgpu_shader void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = extractelement <4 x float> %reg2, i32 0 %4 = extractelement <4 x float> %reg2, i32 0
%5 = fadd float %0, 2.0 %5 = fadd float %0, 2.0
%6 = fadd float %1, 3.0 %6 = fadd float %1, 3.0
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test/CodeGen/AMDGPU/mubuf.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
%1 = getelementptr i32, i32 addrspace(1)* %0, i64 1 %1 = getelementptr i32, i32 addrspace(1)* %0, i64 1
%2 = load i32, i32 addrspace(1)* %1 %2 = load i32, i32 addrspace(1)* %1
store i32 %2, i32 addrspace(1)* %out store i32 %2, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: {{^}}soffset_max_imm: ; CHECK-LABEL: {{^}}soffset_max_imm:
; CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 64 offen glc ; CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 64 offen glc
define void @soffset_max_imm([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 { define amdgpu_shader void @soffset_max_imm([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 {
main_body: main_body:
%tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0 %tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
%tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0 %tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0
%tmp2 = shl i32 %6, 2 %tmp2 = shl i32 %6, 2
%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 64, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0) %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 64, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
%tmp4 = add i32 %6, 16 %tmp4 = add i32 %6, 16
%tmp5 = bitcast float 0.0 to i32 %tmp5 = bitcast float 0.0 to i32
call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
ret void ret void
} }
; Make sure immediates that aren't inline constants don't get folded into ; Make sure immediates that aren't inline constants don't get folded into
; the soffset operand. ; the soffset operand.
; FIXME: for this test we should be smart enough to shift the immediate into ; FIXME: for this test we should be smart enough to shift the immediate into
; the offset field. ; the offset field.
; CHECK-LABEL: {{^}}soffset_no_fold: ; CHECK-LABEL: {{^}}soffset_no_fold:
; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x41 ; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x41
; CHECK: buffer_load_dword v{{[0-9+]}}, v{{[0-9+]}}, s[{{[0-9]+}}:{{[0-9]+}}], [[SOFFSET]] offen glc ; CHECK: buffer_load_dword v{{[0-9+]}}, v{{[0-9+]}}, s[{{[0-9]+}}:{{[0-9]+}}], [[SOFFSET]] offen glc
define void @soffset_no_fold([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 { define amdgpu_shader void @soffset_no_fold([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 {
main_body: main_body:
%tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0 %tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
%tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0 %tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0
%tmp2 = shl i32 %6, 2 %tmp2 = shl i32 %6, 2
%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 65, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0) %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 65, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
%tmp4 = add i32 %6, 16 %tmp4 = add i32 %6, 16
%tmp5 = bitcast float 0.0 to i32 %tmp5 = bitcast float 0.0 to i32
call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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test/CodeGen/AMDGPU/predicate-dp4.ll

;RUN: llc < %s -march=r600 -mcpu=cayman ;RUN: llc < %s -march=r600 -mcpu=cayman
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: PRED_SETE_INT * Pred, ; CHECK: PRED_SETE_INT * Pred,
; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one ; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one
define void @main(<4 x float> inreg) #0 { define amdgpu_shader void @main(<4 x float> inreg) #0 {
main_body: main_body:
%1 = extractelement <4 x float> %0, i32 0 %1 = extractelement <4 x float> %0, i32 0
%2 = bitcast float %1 to i32 %2 = bitcast float %1 to i32
%3 = icmp eq i32 %2, 0 %3 = icmp eq i32 %2, 0
br i1 %3, label %IF, label %ENDIF br i1 %3, label %IF, label %ENDIF
IF: ; preds = %main_body IF: ; preds = %main_body
%4 = call float @llvm.AMDGPU.dp4(<4 x float> %0, <4 x float> %0) %4 = call float @llvm.AMDGPU.dp4(<4 x float> %0, <4 x float> %0)
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test/CodeGen/AMDGPU/pv-packing.ll

; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
;CHECK: DOT4 T{{[0-9]\.X}} ;CHECK: DOT4 T{{[0-9]\.X}}
;CHECK: MULADD_IEEE * T{{[0-9]\.W}} ;CHECK: MULADD_IEEE * T{{[0-9]\.W}}
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg2, i32 0 %3 = extractelement <4 x float> %reg2, i32 0
%4 = extractelement <4 x float> %reg2, i32 1 %4 = extractelement <4 x float> %reg2, i32 1
%5 = extractelement <4 x float> %reg2, i32 2 %5 = extractelement <4 x float> %reg2, i32 2
%6 = extractelement <4 x float> %reg3, i32 0 %6 = extractelement <4 x float> %reg3, i32 0
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test/CodeGen/AMDGPU/pv.ll

; RUN: llc < %s -march=r600 | FileCheck %s ; RUN: llc < %s -march=r600 | FileCheck %s
; CHECK: DOT4 * T{{[0-9]\.W}} (MASKED) ; CHECK: DOT4 * T{{[0-9]\.W}} (MASKED)
; CHECK: MAX T{{[0-9].[XYZW]}}, 0.0, PV.X ; CHECK: MAX T{{[0-9].[XYZW]}}, 0.0, PV.X
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = extractelement <4 x float> %reg2, i32 0 %4 = extractelement <4 x float> %reg2, i32 0
%5 = extractelement <4 x float> %reg2, i32 1 %5 = extractelement <4 x float> %reg2, i32 1
%6 = extractelement <4 x float> %reg2, i32 2 %6 = extractelement <4 x float> %reg2, i32 2
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test/CodeGen/AMDGPU/r600-encoding.ll

; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s
; The earliest R600 GPUs have a slightly different encoding than the rest of ; The earliest R600 GPUs have a slightly different encoding than the rest of
; the VLIW4/5 GPUs. ; the VLIW4/5 GPUs.
; EG: {{^}}test: ; EG: {{^}}test:
; EG: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}] ; EG: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]
; R600: {{^}}test: ; R600: {{^}}test:
; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}] ; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
entry: entry:
%r0 = extractelement <4 x float> %reg0, i32 0 %r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1 %r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fmul float %r0, %r1 %r2 = fmul float %r0, %r1
%vec = insertelement <4 x float> undef, float %r2, i32 0 %vec = insertelement <4 x float> undef, float %r2, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }

test/CodeGen/AMDGPU/r600-export-fix.ll

; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s
;CHECK: EXPORT T{{[0-9]}}.XYZW ;CHECK: EXPORT T{{[0-9]}}.XYZW
;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000
;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000
;CHECK: EXPORT T{{[0-9]}}.0XYZ ;CHECK: EXPORT T{{[0-9]}}.0XYZ
;CHECK: EXPORT T{{[0-9]}}.XYZW ;CHECK: EXPORT T{{[0-9]}}.XYZW
;CHECK: EXPORT T{{[0-9]}}.YZ00 ;CHECK: EXPORT T{{[0-9]}}.YZ00
;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000
;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
%5 = extractelement <4 x float> %4, i32 0 %5 = extractelement <4 x float> %4, i32 0
%6 = fmul float %5, %0 %6 = fmul float %5, %0
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test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll

;RUN: llc < %s -march=r600 -mcpu=cayman ;RUN: llc < %s -march=r600 -mcpu=cayman
define void @main(<4 x float> inreg, <4 x float> inreg) #0 { define amdgpu_shader void @main(<4 x float> inreg, <4 x float> inreg) #0 {
main_body: main_body:
%2 = extractelement <4 x float> %0, i32 0 %2 = extractelement <4 x float> %0, i32 0
%3 = extractelement <4 x float> %0, i32 1 %3 = extractelement <4 x float> %0, i32 1
%4 = extractelement <4 x float> %0, i32 2 %4 = extractelement <4 x float> %0, i32 2
%5 = extractelement <4 x float> %0, i32 3 %5 = extractelement <4 x float> %0, i32 3
%6 = insertelement <4 x float> undef, float %2, i32 0 %6 = insertelement <4 x float> undef, float %2, i32 0
%7 = insertelement <4 x float> %6, float %3, i32 1 %7 = insertelement <4 x float> %6, float %3, i32 1
%8 = insertelement <4 x float> %7, float %4, i32 2 %8 = insertelement <4 x float> %7, float %4, i32 2
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test/CodeGen/AMDGPU/r600cfg.ll

;RUN: llc < %s -march=r600 -mcpu=redwood ;RUN: llc < %s -march=r600 -mcpu=redwood
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = bitcast float %0 to i32 %4 = bitcast float %0 to i32
%5 = icmp eq i32 %4, 0 %5 = icmp eq i32 %4, 0
%6 = sext i1 %5 to i32 %6 = sext i1 %5 to i32
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test/CodeGen/AMDGPU/reciprocal.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0 %r0 = extractelement <4 x float> %reg0, i32 0
%r1 = fdiv float 1.0, %r0 %r1 = fdiv float 1.0, %r0
%vec = insertelement <4 x float> undef, float %r1, i32 0 %vec = insertelement <4 x float> undef, float %r1, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void ret void
} }
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }

test/CodeGen/AMDGPU/ret.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
attributes #0 = { "ShaderType"="1" } attributes #0 = { "ShaderType"="1" }
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
; GCN-LABEL: {{^}}vgpr: ; GCN-LABEL: {{^}}vgpr:
; GCN: v_mov_b32_e32 v1, v0 ; GCN: v_mov_b32_e32 v1, v0
; GCN-DAG: v_add_f32_e32 v0, 1.0, v1 ; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1 ; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1
; GCN: s_waitcnt expcnt(0) ; GCN: s_waitcnt expcnt(0)
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { define amdgpu_shader {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
%x = fadd float %3, 1.0 %x = fadd float %3, 1.0
%a = insertvalue {float, float} undef, float %x, 0 %a = insertvalue {float, float} undef, float %x, 0
%b = insertvalue {float, float} %a, float %3, 1 %b = insertvalue {float, float} %a, float %3, 1
ret {float, float} %b ret {float, float} %b
} }
; GCN-LABEL: {{^}}vgpr_literal: ; GCN-LABEL: {{^}}vgpr_literal:
; GCN: v_mov_b32_e32 v4, v0 ; GCN: v_mov_b32_e32 v4, v0
; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
; GCN-DAG: v_mov_b32_e32 v1, 2.0 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
; GCN-DAG: v_mov_b32_e32 v2, 4.0 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
; GCN-DAG: v_mov_b32_e32 v3, -1.0 ; GCN-DAG: v_mov_b32_e32 v3, -1.0
; GCN: exp 15, 0, 1, 1, 1, v4, v4, v4, v4 ; GCN: exp 15, 0, 1, 1, 1, v4, v4, v4, v4
; GCN: s_waitcnt expcnt(0) ; GCN: s_waitcnt expcnt(0)
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { define amdgpu_shader {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
ret {float, float, float, float} {float 1.0, float 2.0, float 4.0, float -1.0} ret {float, float, float, float} {float 1.0, float 2.0, float 4.0, float -1.0}
} }
; GCN: .long 165580 ; GCN: .long 165580
; GCN-NEXT: .long 562 ; GCN-NEXT: .long 562
; GCN-NEXT: .long 165584 ; GCN-NEXT: .long 165584
; GCN-NEXT: .long 562 ; GCN-NEXT: .long 562
; GCN-LABEL: {{^}}vgpr_ps_addr0: ; GCN-LABEL: {{^}}vgpr_ps_addr0:
; GCN-NOT: v_mov_b32_e32 v0 ; GCN-NOT: v_mov_b32_e32 v0
; GCN-NOT: v_mov_b32_e32 v1 ; GCN-NOT: v_mov_b32_e32 v1
; GCN-NOT: v_mov_b32_e32 v2 ; GCN-NOT: v_mov_b32_e32 v2
; GCN: v_mov_b32_e32 v3, v4 ; GCN: v_mov_b32_e32 v3, v4
; GCN: v_mov_b32_e32 v4, v6 ; GCN: v_mov_b32_e32 v4, v6
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
attributes #1 = { "ShaderType"="0" "InitialPSInputAddr"="0" } attributes #1 = { "ShaderType"="0" "InitialPSInputAddr"="0" }
define {float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 { define amdgpu_shader {float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 {
%i0 = extractelement <2 x i32> %4, i32 0 %i0 = extractelement <2 x i32> %4, i32 0
%i1 = extractelement <2 x i32> %4, i32 1 %i1 = extractelement <2 x i32> %4, i32 1
%i2 = extractelement <2 x i32> %7, i32 0 %i2 = extractelement <2 x i32> %7, i32 0
%i3 = extractelement <2 x i32> %8, i32 0 %i3 = extractelement <2 x i32> %8, i32 0
%f0 = bitcast i32 %i0 to float %f0 = bitcast i32 %i0 to float
%f1 = bitcast i32 %i1 to float %f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float %f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float %f3 = bitcast i32 %i3 to float
%r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0 %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
%r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1 %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
%r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2 %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
%r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3 %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
%r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4 %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
ret {float, float, float, float, float} %r4 ret {float, float, float, float, float} %r4
} }
; GCN: .long 165580 ; GCN: .long 165580
; GCN-NEXT: .long 1 ; GCN-NEXT: .long 1
; GCN-NEXT: .long 165584 ; GCN-NEXT: .long 165584
; GCN-NEXT: .long 1 ; GCN-NEXT: .long 1
; GCN-LABEL: {{^}}ps_input_ena_no_inputs: ; GCN-LABEL: {{^}}ps_input_ena_no_inputs:
; GCN: v_mov_b32_e32 v0, 1.0 ; GCN: v_mov_b32_e32 v0, 1.0
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 { define amdgpu_shader float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 {
ret float 1.0 ret float 1.0
} }
; GCN: .long 165580 ; GCN: .long 165580
; GCN-NEXT: .long 2081 ; GCN-NEXT: .long 2081
; GCN-NEXT: .long 165584 ; GCN-NEXT: .long 165584
; GCN-NEXT: .long 2081 ; GCN-NEXT: .long 2081
; GCN-LABEL: {{^}}ps_input_ena_pos_w: ; GCN-LABEL: {{^}}ps_input_ena_pos_w:
; GCN-DAG: v_mov_b32_e32 v0, v4 ; GCN-DAG: v_mov_b32_e32 v0, v4
; GCN-DAG: v_mov_b32_e32 v1, v2 ; GCN-DAG: v_mov_b32_e32 v1, v2
; GCN: v_mov_b32_e32 v2, v3 ; GCN: v_mov_b32_e32 v2, v3
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define {float, <2 x float>} @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 { define amdgpu_shader {float, <2 x float>} @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 {
%f = bitcast <2 x i32> %8 to <2 x float> %f = bitcast <2 x i32> %8 to <2 x float>
%s = insertvalue {float, <2 x float>} undef, float %14, 0 %s = insertvalue {float, <2 x float>} undef, float %14, 0
%s1 = insertvalue {float, <2 x float>} %s, <2 x float> %f, 1 %s1 = insertvalue {float, <2 x float>} %s, <2 x float> %f, 1
ret {float, <2 x float>} %s1 ret {float, <2 x float>} %s1
} }
; GCN: .long 165580 ; GCN: .long 165580
; GCN-NEXT: .long 562 ; GCN-NEXT: .long 562
; GCN-NEXT: .long 165584 ; GCN-NEXT: .long 165584
; GCN-NEXT: .long 563 ; GCN-NEXT: .long 563
; GCN-LABEL: {{^}}vgpr_ps_addr1: ; GCN-LABEL: {{^}}vgpr_ps_addr1:
; GCN-DAG: v_mov_b32_e32 v0, v2 ; GCN-DAG: v_mov_b32_e32 v0, v2
; GCN-DAG: v_mov_b32_e32 v1, v3 ; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mov_b32_e32 v2, v4 ; GCN: v_mov_b32_e32 v2, v4
; GCN-DAG: v_mov_b32_e32 v3, v6 ; GCN-DAG: v_mov_b32_e32 v3, v6
; GCN-DAG: v_mov_b32_e32 v4, v8 ; GCN-DAG: v_mov_b32_e32 v4, v8
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
attributes #2 = { "ShaderType"="0" "InitialPSInputAddr"="1" } attributes #2 = { "ShaderType"="0" "InitialPSInputAddr"="1" }
define {float, float, float, float, float} @vgpr_ps_addr1([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #2 { define amdgpu_shader {float, float, float, float, float} @vgpr_ps_addr1([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #2 {
%i0 = extractelement <2 x i32> %4, i32 0 %i0 = extractelement <2 x i32> %4, i32 0
%i1 = extractelement <2 x i32> %4, i32 1 %i1 = extractelement <2 x i32> %4, i32 1
%i2 = extractelement <2 x i32> %7, i32 0 %i2 = extractelement <2 x i32> %7, i32 0
%i3 = extractelement <2 x i32> %8, i32 0 %i3 = extractelement <2 x i32> %8, i32 0
%f0 = bitcast i32 %i0 to float %f0 = bitcast i32 %i0 to float
%f1 = bitcast i32 %i1 to float %f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float %f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float %f3 = bitcast i32 %i3 to float
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; GCN-LABEL: {{^}}vgpr_ps_addr119: ; GCN-LABEL: {{^}}vgpr_ps_addr119:
; GCN-DAG: v_mov_b32_e32 v0, v2 ; GCN-DAG: v_mov_b32_e32 v0, v2
; GCN-DAG: v_mov_b32_e32 v1, v3 ; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mov_b32_e32 v2, v6 ; GCN: v_mov_b32_e32 v2, v6
; GCN: v_mov_b32_e32 v3, v8 ; GCN: v_mov_b32_e32 v3, v8
; GCN: v_mov_b32_e32 v4, v12 ; GCN: v_mov_b32_e32 v4, v12
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
attributes #3 = { "ShaderType"="0" "InitialPSInputAddr"="119" } attributes #3 = { "ShaderType"="0" "InitialPSInputAddr"="119" }
define {float, float, float, float, float} @vgpr_ps_addr119([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #3 { define amdgpu_shader {float, float, float, float, float} @vgpr_ps_addr119([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #3 {
%i0 = extractelement <2 x i32> %4, i32 0 %i0 = extractelement <2 x i32> %4, i32 0
%i1 = extractelement <2 x i32> %4, i32 1 %i1 = extractelement <2 x i32> %4, i32 1
%i2 = extractelement <2 x i32> %7, i32 0 %i2 = extractelement <2 x i32> %7, i32 0
%i3 = extractelement <2 x i32> %8, i32 0 %i3 = extractelement <2 x i32> %8, i32 0
%f0 = bitcast i32 %i0 to float %f0 = bitcast i32 %i0 to float
%f1 = bitcast i32 %i1 to float %f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float %f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float %f3 = bitcast i32 %i3 to float
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; GCN-LABEL: {{^}}vgpr_ps_addr418: ; GCN-LABEL: {{^}}vgpr_ps_addr418:
; GCN-NOT: v_mov_b32_e32 v0 ; GCN-NOT: v_mov_b32_e32 v0
; GCN-NOT: v_mov_b32_e32 v1 ; GCN-NOT: v_mov_b32_e32 v1
; GCN-NOT: v_mov_b32_e32 v2 ; GCN-NOT: v_mov_b32_e32 v2
; GCN: v_mov_b32_e32 v3, v4 ; GCN: v_mov_b32_e32 v3, v4
; GCN: v_mov_b32_e32 v4, v8 ; GCN: v_mov_b32_e32 v4, v8
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
attributes #4 = { "ShaderType"="0" "InitialPSInputAddr"="418" } attributes #4 = { "ShaderType"="0" "InitialPSInputAddr"="418" }
define {float, float, float, float, float} @vgpr_ps_addr418([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #4 { define amdgpu_shader {float, float, float, float, float} @vgpr_ps_addr418([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #4 {
%i0 = extractelement <2 x i32> %4, i32 0 %i0 = extractelement <2 x i32> %4, i32 0
%i1 = extractelement <2 x i32> %4, i32 1 %i1 = extractelement <2 x i32> %4, i32 1
%i2 = extractelement <2 x i32> %7, i32 0 %i2 = extractelement <2 x i32> %7, i32 0
%i3 = extractelement <2 x i32> %8, i32 0 %i3 = extractelement <2 x i32> %8, i32 0
%f0 = bitcast i32 %i0 to float %f0 = bitcast i32 %i0 to float
%f1 = bitcast i32 %i1 to float %f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float %f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float %f3 = bitcast i32 %i3 to float
%r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0 %r0 = insertvalue {float, float, float, float, float} undef, float %f0, 0
%r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1 %r1 = insertvalue {float, float, float, float, float} %r0, float %f1, 1
%r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2 %r2 = insertvalue {float, float, float, float, float} %r1, float %f2, 2
%r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3 %r3 = insertvalue {float, float, float, float, float} %r2, float %f3, 3
%r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4 %r4 = insertvalue {float, float, float, float, float} %r3, float %12, 4
ret {float, float, float, float, float} %r4 ret {float, float, float, float, float} %r4
} }
; GCN-LABEL: {{^}}sgpr: ; GCN-LABEL: {{^}}sgpr:
; GCN: s_add_i32 s0, s3, 2 ; GCN: s_add_i32 s0, s3, 2
; GCN: s_mov_b32 s2, s3 ; GCN: s_mov_b32 s2, s3
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define {i32, i32, i32} @sgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { define amdgpu_shader {i32, i32, i32} @sgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
%x = add i32 %2, 2 %x = add i32 %2, 2
%a = insertvalue {i32, i32, i32} undef, i32 %x, 0 %a = insertvalue {i32, i32, i32} undef, i32 %x, 0
%b = insertvalue {i32, i32, i32} %a, i32 %1, 1 %b = insertvalue {i32, i32, i32} %a, i32 %1, 1
%c = insertvalue {i32, i32, i32} %a, i32 %2, 2 %c = insertvalue {i32, i32, i32} %a, i32 %2, 2
ret {i32, i32, i32} %c ret {i32, i32, i32} %c
} }
; GCN-LABEL: {{^}}sgpr_literal: ; GCN-LABEL: {{^}}sgpr_literal:
; GCN: s_mov_b32 s0, 5 ; GCN: s_mov_b32 s0, 5
; GCN-NOT: s_mov_b32 s0, s0 ; GCN-NOT: s_mov_b32 s0, s0
; GCN-DAG: s_mov_b32 s1, 6 ; GCN-DAG: s_mov_b32 s1, 6
; GCN-DAG: s_mov_b32 s2, 7 ; GCN-DAG: s_mov_b32 s2, 7
; GCN-DAG: s_mov_b32 s3, 8 ; GCN-DAG: s_mov_b32 s3, 8
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define {i32, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { define amdgpu_shader {i32, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
%x = add i32 %2, 2 %x = add i32 %2, 2
ret {i32, i32, i32, i32} {i32 5, i32 6, i32 7, i32 8} ret {i32, i32, i32, i32} {i32 5, i32 6, i32 7, i32 8}
} }
; GCN-LABEL: {{^}}both: ; GCN-LABEL: {{^}}both:
; GCN: v_mov_b32_e32 v1, v0 ; GCN: v_mov_b32_e32 v1, v0
; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1 ; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1
; GCN-DAG: v_add_f32_e32 v0, 1.0, v1 ; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
; GCN-DAG: s_add_i32 s0, s3, 2 ; GCN-DAG: s_add_i32 s0, s3, 2
; GCN-DAG: s_mov_b32 s1, s2 ; GCN-DAG: s_mov_b32 s1, s2
; GCN: s_mov_b32 s2, s3 ; GCN: s_mov_b32 s2, s3
; GCN: s_waitcnt expcnt(0) ; GCN: s_waitcnt expcnt(0)
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { define amdgpu_shader {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
%v = fadd float %3, 1.0 %v = fadd float %3, 1.0
%s = add i32 %2, 2 %s = add i32 %2, 2
%a0 = insertvalue {float, i32, float, i32, i32} undef, float %v, 0 %a0 = insertvalue {float, i32, float, i32, i32} undef, float %v, 0
%a1 = insertvalue {float, i32, float, i32, i32} %a0, i32 %s, 1 %a1 = insertvalue {float, i32, float, i32, i32} %a0, i32 %s, 1
%a2 = insertvalue {float, i32, float, i32, i32} %a1, float %3, 2 %a2 = insertvalue {float, i32, float, i32, i32} %a1, float %3, 2
%a3 = insertvalue {float, i32, float, i32, i32} %a2, i32 %1, 3 %a3 = insertvalue {float, i32, float, i32, i32} %a2, i32 %1, 3
%a4 = insertvalue {float, i32, float, i32, i32} %a3, i32 %2, 4 %a4 = insertvalue {float, i32, float, i32, i32} %a3, i32 %2, 4
ret {float, i32, float, i32, i32} %a4 ret {float, i32, float, i32, i32} %a4
} }
; GCN-LABEL: {{^}}structure_literal: ; GCN-LABEL: {{^}}structure_literal:
; GCN: v_mov_b32_e32 v3, v0 ; GCN: v_mov_b32_e32 v3, v0
; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
; GCN-DAG: s_mov_b32 s0, 2 ; GCN-DAG: s_mov_b32 s0, 2
; GCN-DAG: s_mov_b32 s1, 3 ; GCN-DAG: s_mov_b32 s1, 3
; GCN-DAG: v_mov_b32_e32 v1, 2.0 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
; GCN-DAG: v_mov_b32_e32 v2, 4.0 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
; GCN-DAG: exp 15, 0, 1, 1, 1, v3, v3, v3, v3 ; GCN-DAG: exp 15, 0, 1, 1, 1, v3, v3, v3, v3
define {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { define amdgpu_shader {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 {
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
ret {{float, i32}, {i32, <2 x float>}} {{float, i32} {float 1.0, i32 2}, {i32, <2 x float>} {i32 3, <2 x float> <float 2.0, float 4.0>}} ret {{float, i32}, {i32, <2 x float>}} {{float, i32} {float 1.0, i32 2}, {i32, <2 x float>} {i32 3, <2 x float> <float 2.0, float 4.0>}}
} }

test/CodeGen/AMDGPU/ret_jump.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
target triple = "amdgcn--" target triple = "amdgcn--"
; GCN-LABEL: {{^}}main: ; GCN-LABEL: {{^}}main:
; GCN: BB0_3: ; GCN: BB0_3:
; GCN-NEXT: s_branch [[LASTBB:BB[0-9]*_[0-9]*]] ; GCN-NEXT: s_branch [[LASTBB:BB[0-9]*_[0-9]*]]
; GCN-NEXT: BB0_ ; GCN-NEXT: BB0_
; GCN: [[LASTBB]] ; GCN: [[LASTBB]]
; GCN-NEXT: .Lfunc_end0: ; GCN-NEXT: .Lfunc_end0:
; ModuleID = 'bugpoint-reduced-simplified.bc' ; ModuleID = 'bugpoint-reduced-simplified.bc'
target triple = "amdgcn--" target triple = "amdgcn--"
define <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, i32 addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 { define amdgpu_shader <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, i32 addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
main_body: main_body:
%p83 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %p83 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
%p87 = fmul float undef, %p83 %p87 = fmul float undef, %p83
%p88 = fadd float %p87, undef %p88 = fadd float %p87, undef
%p93 = fadd float %p88, undef %p93 = fadd float %p88, undef
%p97 = fmul float %p93, undef %p97 = fmul float %p93, undef
%p102 = fsub float %p97, undef %p102 = fsub float %p97, undef
%p104 = fmul float %p102, undef %p104 = fmul float %p102, undef
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test/CodeGen/AMDGPU/rv7x0_count3.ll

; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s
; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80] ; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80]
define void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
%1 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 0
%2 = extractelement <4 x float> %reg1, i32 1 %2 = extractelement <4 x float> %reg1, i32 1
%3 = extractelement <4 x float> %reg1, i32 2 %3 = extractelement <4 x float> %reg1, i32 2
%4 = extractelement <4 x float> %reg1, i32 3 %4 = extractelement <4 x float> %reg1, i32 3
%5 = insertelement <4 x float> undef, float %1, i32 0 %5 = insertelement <4 x float> undef, float %1, i32 0
%6 = insertelement <4 x float> %5, float %2, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 1
%7 = insertelement <4 x float> %6, float %3, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 2
%8 = insertelement <4 x float> %7, float %4, i32 3 %8 = insertelement <4 x float> %7, float %4, i32 3
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test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll

;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
;REQUIRES: asserts ;REQUIRES: asserts
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #1 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #1 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = fcmp ult float %1, 0.000000e+00 %4 = fcmp ult float %1, 0.000000e+00
%5 = select i1 %4, float 1.000000e+00, float 0.000000e+00 %5 = select i1 %4, float 1.000000e+00, float 0.000000e+00
%6 = fsub float -0.000000e+00, %5 %6 = fsub float -0.000000e+00, %5
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test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll

; XFAIL: * ; XFAIL: *
; REQUIRES: asserts ; REQUIRES: asserts
; RUN: llc -O0 -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck %s -check-prefix=SI ; RUN: llc -O0 -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck %s -check-prefix=SI
; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck %s -check-prefix=SI ; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck %s -check-prefix=SI
declare void @llvm.AMDGPU.barrier.local() nounwind convergent declare void @llvm.AMDGPU.barrier.local() nounwind convergent
; SI-LABEL: {{^}}main( ; SI-LABEL: {{^}}main(
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 2 %1 = extractelement <4 x float> %reg1, i32 2
%2 = fcmp ult float %0, 0.000000e+00 %2 = fcmp ult float %0, 0.000000e+00
%3 = select i1 %2, float 1.000000e+00, float 0.000000e+00 %3 = select i1 %2, float 1.000000e+00, float 0.000000e+00
%4 = fsub float -0.000000e+00, %3 %4 = fsub float -0.000000e+00, %3
%5 = fptosi float %4 to i32 %5 = fptosi float %4 to i32
%6 = bitcast i32 %5 to float %6 = bitcast i32 %5 to float
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test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll

;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
;REQUIRES: asserts ;REQUIRES: asserts
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = fcmp ult float %0, 0.000000e+00 %4 = fcmp ult float %0, 0.000000e+00
%5 = select i1 %4, float 1.000000e+00, float 0.000000e+00 %5 = select i1 %4, float 1.000000e+00, float 0.000000e+00
%6 = fsub float -0.000000e+00, %5 %6 = fsub float -0.000000e+00, %5
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test/CodeGen/AMDGPU/sgpr-copy.ll

; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
; This test checks that no VGPR to SGPR copies are created by the register ; This test checks that no VGPR to SGPR copies are created by the register
; allocator. ; allocator.
declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
; CHECK-LABEL: {{^}}phi1: ; CHECK-LABEL: {{^}}phi1:
; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]] ; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]]
define void @phi1(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_shader void @phi1(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
%tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0) %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0)
%tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16)
%tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32) %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32)
%tmp24 = fptosi float %tmp22 to i32 %tmp24 = fptosi float %tmp22 to i32
%tmp25 = icmp ne i32 %tmp24, 0 %tmp25 = icmp ne i32 %tmp24, 0
br i1 %tmp25, label %ENDIF, label %ELSE br i1 %tmp25, label %ENDIF, label %ELSE
ELSE: ; preds = %main_body ELSE: ; preds = %main_body
%tmp26 = fsub float -0.000000e+00, %tmp21 %tmp26 = fsub float -0.000000e+00, %tmp21
br label %ENDIF br label %ENDIF
ENDIF: ; preds = %ELSE, %main_body ENDIF: ; preds = %ELSE, %main_body
%temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ] %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ]
%tmp27 = fadd float %temp.0, %tmp23 %tmp27 = fadd float %temp.0, %tmp23
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00)
ret void ret void
} }
; Make sure this program doesn't crash ; Make sure this program doesn't crash
; CHECK-LABEL: {{^}}phi2: ; CHECK-LABEL: {{^}}phi2:
define void @phi2(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_shader void @phi2(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
%tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16)
%tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32) %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32)
%tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 36) %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 36)
%tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 40) %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 40)
%tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 48) %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 48)
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 LinesENDIF24: ; preds = %IF25, %ENDIF
%tmp115 = call i32 @llvm.SI.packf16(float %tmp112, float 1.000000e+00) %tmp115 = call i32 @llvm.SI.packf16(float %tmp112, float 1.000000e+00)
%tmp116 = bitcast i32 %tmp115 to float %tmp116 = bitcast i32 %tmp115 to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp114, float %tmp116, float %tmp114, float %tmp116) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp114, float %tmp116, float %tmp114, float %tmp116)
ret void ret void
} }
; We just want ot make sure the program doesn't crash ; We just want ot make sure the program doesn't crash
; CHECK-LABEL: {{^}}loop: ; CHECK-LABEL: {{^}}loop:
define void @loop(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_shader void @loop(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
%tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0) %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0)
%tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 4) %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 4)
%tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 8) %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 8)
%tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 12) %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 12)
%tmp25 = fptosi float %tmp24 to i32 %tmp25 = fptosi float %tmp24 to i32
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; registers were being identified as an SGPR regclass which was causing ; registers were being identified as an SGPR regclass which was causing
; an assertion failure. ; an assertion failure.
; CHECK-LABEL: {{^}}sample_v3: ; CHECK-LABEL: {{^}}sample_v3:
; CHECK: image_sample ; CHECK: image_sample
; CHECK: image_sample ; CHECK: image_sample
; CHECK: exp ; CHECK: exp
; CHECK: s_endpgm ; CHECK: s_endpgm
define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { define amdgpu_shader void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
entry: entry:
%tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0
%tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 16) %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 16)
%tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0 %tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0
%tmp24 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp23, !tbaa !0 %tmp24 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp23, !tbaa !0
%tmp25 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 0 %tmp25 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 0
%tmp26 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp25, !tbaa !0 %tmp26 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp25, !tbaa !0
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesendif: ; preds = %if1, %if0, %entry
%tmp6 = bitcast i32 %tmp5 to float %tmp6 = bitcast i32 %tmp5 to float
store float %tmp6, float addrspace(1)* %out store float %tmp6, float addrspace(1)* %out
ret void ret void
} }
; This test is just checking that we don't crash / assertion fail. ; This test is just checking that we don't crash / assertion fail.
; CHECK-LABEL: {{^}}copy2: ; CHECK-LABEL: {{^}}copy2:
; CHECK: s_endpgm ; CHECK: s_endpgm
define void @copy2([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { define amdgpu_shader void @copy2([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
entry: entry:
br label %LOOP68 br label %LOOP68
LOOP68: ; preds = %ENDIF69, %entry LOOP68: ; preds = %ENDIF69, %entry
%temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ] %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
%t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ] %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
%g = icmp eq i32 0, %t %g = icmp eq i32 0, %t
%l = bitcast float %temp4.7 to i32 %l = bitcast float %temp4.7 to i32
Show All 13 Lines
} }
; This test checks that image_sample resource descriptors aren't loaded into ; This test checks that image_sample resource descriptors aren't loaded into
; vgprs. The verifier will fail if this happens. ; vgprs. The verifier will fail if this happens.
; CHECK-LABEL:{{^}}sample_rsrc: ; CHECK-LABEL:{{^}}sample_rsrc:
; CHECK: image_sample ; CHECK: image_sample
; CHECK: image_sample ; CHECK: image_sample
; CHECK: s_endpgm ; CHECK: s_endpgm
define void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { define amdgpu_shader void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
bb: bb:
%tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0
%tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !2 %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !2
%tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp22, i32 16) %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp22, i32 16)
%tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0 %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0
%tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !2 %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !2
%tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0 %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0
%tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !2 %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !2
Show All 27 Linesbb71: ; preds = %bb80, %bb38
%tmp88 = extractelement <4 x float> %tmp72, i32 0 %tmp88 = extractelement <4 x float> %tmp72, i32 0
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp88, float %tmp88, float %tmp88, float %tmp88) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp88, float %tmp88, float %tmp88, float %tmp88)
ret void ret void
} }
; Check the the resource descriptor is stored in an sgpr. ; Check the the resource descriptor is stored in an sgpr.
; CHECK-LABEL: {{^}}mimg_srsrc_sgpr: ; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
define void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 { define amdgpu_shader void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
%tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0 %tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0
%tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%tmp10 = extractelement <4 x float> %tmp9, i32 0 %tmp10 = extractelement <4 x float> %tmp9, i32 0
%tmp12 = call i32 @llvm.SI.packf16(float undef, float %tmp10) %tmp12 = call i32 @llvm.SI.packf16(float undef, float %tmp10)
%tmp13 = bitcast i32 %tmp12 to float %tmp13 = bitcast i32 %tmp12 to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp13, float undef, float undef, float undef) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp13, float undef, float undef, float undef)
ret void ret void
} }
; Check the the sampler is stored in an sgpr. ; Check the the sampler is stored in an sgpr.
; CHECK-LABEL: {{^}}mimg_ssamp_sgpr: ; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
define void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 { define amdgpu_shader void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 {
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
%tmp8 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp7, align 16, !tbaa !0 %tmp8 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp7, align 16, !tbaa !0
%tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> undef, <4 x i32> %tmp8, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> undef, <4 x i32> %tmp8, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%tmp10 = extractelement <4 x float> %tmp9, i32 0 %tmp10 = extractelement <4 x float> %tmp9, i32 0
%tmp12 = call i32 @llvm.SI.packf16(float %tmp10, float undef) %tmp12 = call i32 @llvm.SI.packf16(float %tmp10, float undef)
%tmp13 = bitcast i32 %tmp12 to float %tmp13 = bitcast i32 %tmp12 to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp13, float undef, float undef, float undef) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp13, float undef, float undef, float undef)
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test/CodeGen/AMDGPU/shared-op-cycle.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
; CHECK: {{^}}main: ; CHECK: {{^}}main:
; CHECK: MULADD_IEEE * ; CHECK: MULADD_IEEE *
; CHECK-NOT: MULADD_IEEE * ; CHECK-NOT: MULADD_IEEE *
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
%w0 = extractelement <4 x float> %reg0, i32 3 %w0 = extractelement <4 x float> %reg0, i32 3
%w1 = extractelement <4 x float> %reg1, i32 3 %w1 = extractelement <4 x float> %reg1, i32 3
%w2 = extractelement <4 x float> %reg2, i32 3 %w2 = extractelement <4 x float> %reg2, i32 3
%sq0 = fmul float %w0, %w0 %sq0 = fmul float %w0, %w0
%r0 = fadd float %sq0, 2.0 %r0 = fadd float %sq0, 2.0
%sq1 = fmul float %w1, %w1 %sq1 = fmul float %w1, %w1
%r1 = fadd float %sq1, 2.0 %r1 = fadd float %sq1, 2.0
%sq2 = fmul float %w2, %w2 %sq2 = fmul float %w2, %w2
%r2 = fadd float %sq2, 2.0 %r2 = fadd float %sq2, 2.0
%v0 = insertelement <4 x float> undef, float %r0, i32 0 %v0 = insertelement <4 x float> undef, float %r0, i32 0
%v1 = insertelement <4 x float> %v0, float %r1, i32 1 %v1 = insertelement <4 x float> %v0, float %r1, i32 1
%v2 = insertelement <4 x float> %v1, float %r2, i32 2 %v2 = insertelement <4 x float> %v1, float %r2, i32 2
%res = call float @llvm.AMDGPU.dp4(<4 x float> %v2, <4 x float> %v2) %res = call float @llvm.AMDGPU.dp4(<4 x float> %v2, <4 x float> %v2)
%vecres = insertelement <4 x float> undef, float %res, i32 0 %vecres = insertelement <4 x float> undef, float %res, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vecres, i32 0, i32 2) call void @llvm.R600.store.swizzle(<4 x float> %vecres, i32 0, i32 2)
ret void ret void
} }
; Function Attrs: readnone ; Function Attrs: readnone
declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
attributes #0 = { "ShaderType"="1" } attributes #0 = { "ShaderType"="1" }
attributes #1 = { readnone } attributes #1 = { readnone }
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test/CodeGen/AMDGPU/si-lod-bias.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
; This shader has the potential to generated illegal VGPR to SGPR copies if ; This shader has the potential to generated illegal VGPR to SGPR copies if
; the wrong register class is used for the REG_SEQUENCE instructions. ; the wrong register class is used for the REG_SEQUENCE instructions.
; CHECK: {{^}}main: ; CHECK: {{^}}main:
; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf ; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf
define void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_shader void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
%tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16)
%tmp22 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0 %tmp22 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0
%tmp23 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp22, !tbaa !0 %tmp23 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp22, !tbaa !0
%tmp24 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0 %tmp24 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0
%tmp25 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp24, !tbaa !0 %tmp25 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp24, !tbaa !0
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test/CodeGen/AMDGPU/si-scheduler.ll

; RUN: llc -march=amdgcn -mcpu=SI --misched=si < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=SI --misched=si < %s | FileCheck %s
; The test checks the "si" machine scheduler pass works correctly. ; The test checks the "si" machine scheduler pass works correctly.
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: s_wqm ; CHECK: s_wqm
; CHECK: s_load_dwordx4 ; CHECK: s_load_dwordx4
; CHECK: s_load_dwordx8 ; CHECK: s_load_dwordx8
; CHECK: s_waitcnt lgkmcnt(0) ; CHECK: s_waitcnt lgkmcnt(0)
; CHECK: image_sample ; CHECK: image_sample
; CHECK: s_waitcnt vmcnt(0) ; CHECK: s_waitcnt vmcnt(0)
; CHECK: exp ; CHECK: exp
; CHECK: s_endpgm ; CHECK: s_endpgm
define void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { define amdgpu_shader void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
main_body: main_body:
%tmp = bitcast [34 x <8 x i32>] addrspace(2)* %arg3 to <32 x i8> addrspace(2)* %tmp = bitcast [34 x <8 x i32>] addrspace(2)* %arg3 to <32 x i8> addrspace(2)*
%tmp22 = load <32 x i8>, <32 x i8> addrspace(2)* %tmp, align 32, !tbaa !0 %tmp22 = load <32 x i8>, <32 x i8> addrspace(2)* %tmp, align 32, !tbaa !0
%tmp23 = bitcast [17 x <4 x i32>] addrspace(2)* %arg2 to <16 x i8> addrspace(2)* %tmp23 = bitcast [17 x <4 x i32>] addrspace(2)* %arg2 to <16 x i8> addrspace(2)*
%tmp24 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp23, align 16, !tbaa !0 %tmp24 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp23, align 16, !tbaa !0
%tmp25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg11) %tmp25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg11)
%tmp26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg11) %tmp26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg11)
%tmp27 = bitcast float %tmp25 to i32 %tmp27 = bitcast float %tmp25 to i32
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test/CodeGen/AMDGPU/si-sgpr-spill.ll

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; CHECK-NOT: s_mov_b32 ; CHECK-NOT: s_mov_b32
; CHECK: s_mov_b32 m0 ; CHECK: s_mov_b32 m0
; Writing to M0 from an SMRD instruction will hang the GPU. ; Writing to M0 from an SMRD instruction will hang the GPU.
; CHECK-NOT: s_buffer_load_dword m0 ; CHECK-NOT: s_buffer_load_dword m0
; CHECK: s_endpgm ; CHECK: s_endpgm
define void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { define amdgpu_shader void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
main_body: main_body:
%tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0
%tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 96) %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 96)
%tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 100) %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 100)
%tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 104) %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 104)
%tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 112) %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 112)
%tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 116) %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 116)
▲ Show 20 Lines • Show All 629 Lines • ▼ Show 20 LinesENDIF66: ; preds = %LOOP65
%tmp608 = fadd float %tmp607, %temp30.1 %tmp608 = fadd float %tmp607, %temp30.1
%tmp609 = fadd float %temp24.1, 1.000000e+00 %tmp609 = fadd float %temp24.1, 1.000000e+00
%tmp610 = fmul float %temp32.0, 5.000000e-01 %tmp610 = fmul float %temp32.0, 5.000000e-01
br label %LOOP65 br label %LOOP65
} }
; CHECK-LABEL: {{^}}main1: ; CHECK-LABEL: {{^}}main1:
; CHECK: s_endpgm ; CHECK: s_endpgm
define void @main1([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { define amdgpu_shader void @main1([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
main_body: main_body:
%tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0
%tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 0) %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 0)
%tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 4) %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 4)
%tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 8) %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 8)
%tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 12) %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 12)
%tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 28) %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 28)
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test/CodeGen/AMDGPU/si-spill-cf.ll

; RUN: llc -march=amdgcn -mcpu=SI < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=SI < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s
; If this occurs it is likely due to reordering and the restore was ; If this occurs it is likely due to reordering and the restore was
; originally supposed to happen before SI_END_CF. ; originally supposed to happen before SI_END_CF.
; SI: s_or_b64 exec, exec, [[SAVED:s\[[0-9]+:[0-9]+\]|[a-z]+]] ; SI: s_or_b64 exec, exec, [[SAVED:s\[[0-9]+:[0-9]+\]|[a-z]+]]
; SI-NOT: v_readlane_b32 [[SAVED]] ; SI-NOT: v_readlane_b32 [[SAVED]]
define void @main() #1 { define amdgpu_shader void @main() #1 {
main_body: main_body:
%0 = call float @llvm.SI.load.const(<16 x i8> undef, i32 16) %0 = call float @llvm.SI.load.const(<16 x i8> undef, i32 16)
%1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 32) %1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 32)
%2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 80) %2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 80)
%3 = call float @llvm.SI.load.const(<16 x i8> undef, i32 84) %3 = call float @llvm.SI.load.const(<16 x i8> undef, i32 84)
%4 = call float @llvm.SI.load.const(<16 x i8> undef, i32 88) %4 = call float @llvm.SI.load.const(<16 x i8> undef, i32 88)
%5 = call float @llvm.SI.load.const(<16 x i8> undef, i32 96) %5 = call float @llvm.SI.load.const(<16 x i8> undef, i32 96)
%6 = call float @llvm.SI.load.const(<16 x i8> undef, i32 100) %6 = call float @llvm.SI.load.const(<16 x i8> undef, i32 100)
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test/CodeGen/AMDGPU/smrd.ll

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Linesentry:
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load using the load.const intrinsic with an immediate offset ; SMRD load using the load.const intrinsic with an immediate offset
; GCN-LABEL: {{^}}smrd_load_const0: ; GCN-LABEL: {{^}}smrd_load_const0:
; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04 ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10
define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { define amdgpu_shader void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body: main_body:
%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
ret void ret void
} }
; SMRD load using the load.const intrinsic with the largest possible immediate ; SMRD load using the load.const intrinsic with the largest possible immediate
; offset. ; offset.
; GCN-LABEL: {{^}}smrd_load_const1: ; GCN-LABEL: {{^}}smrd_load_const1:
; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { define amdgpu_shader void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body: main_body:
%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1020) %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1020)
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
ret void ret void
} }
; SMRD load using the load.const intrinsic with an offset greater than the ; SMRD load using the load.const intrinsic with an offset greater than the
; largets possible immediate. ; largets possible immediate.
; immediate offset. ; immediate offset.
; GCN-LABEL: {{^}}smrd_load_const2: ; GCN-LABEL: {{^}}smrd_load_const2:
; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400 ; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
define void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { define amdgpu_shader void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body: main_body:
%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1024) %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1024)
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
ret void ret void
} }
; SMRD load with the largest possible immediate offset on VI ; SMRD load with the largest possible immediate offset on VI
; GCN-LABEL: {{^}}smrd_load_const3: ; GCN-LABEL: {{^}}smrd_load_const3:
; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
define void @smrd_load_const3(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { define amdgpu_shader void @smrd_load_const3(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body: main_body:
%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1048572) %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1048572)
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
ret void ret void
} }
; SMRD load with an offset greater than the largest possible immediate on VI ; SMRD load with an offset greater than the largest possible immediate on VI
; GCN-LABEL: {{^}}smrd_load_const4: ; GCN-LABEL: {{^}}smrd_load_const4:
; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000 ; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
; SIVI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; SIVI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
; GCN: s_endpgm ; GCN: s_endpgm
define void @smrd_load_const4(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { define amdgpu_shader void @smrd_load_const4(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body: main_body:
%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1048576) %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1048576)
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
attributes #0 = { "ShaderType"="0" } attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/AMDGPU/split-smrd.ll

; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
; FIXME: Move this to sgpr-copy.ll when this is fixed on VI. ; FIXME: Move this to sgpr-copy.ll when this is fixed on VI.
; Make sure that when we split an smrd instruction in order to move it to ; Make sure that when we split an smrd instruction in order to move it to
; the VALU, we are also moving its users to the VALU. ; the VALU, we are also moving its users to the VALU.
; CHECK-LABEL: {{^}}split_smrd_add_worklist: ; CHECK-LABEL: {{^}}split_smrd_add_worklist:
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
define void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(2)* byval %arg) #0 { define amdgpu_shader void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
bb: bb:
%tmp = call float @llvm.SI.load.const(<16 x i8> undef, i32 96) %tmp = call float @llvm.SI.load.const(<16 x i8> undef, i32 96)
%tmp1 = bitcast float %tmp to i32 %tmp1 = bitcast float %tmp to i32
br i1 undef, label %bb2, label %bb3 br i1 undef, label %bb2, label %bb3
bb2: ; preds = %bb bb2: ; preds = %bb
unreachable unreachable
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test/CodeGen/AMDGPU/swizzle-export.ll

; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
;EG: {{^}}main: ;EG: {{^}}main:
;EG: EXPORT T{{[0-9]+}}.XYXX ;EG: EXPORT T{{[0-9]+}}.XYXX
;EG: EXPORT T{{[0-9]+}}.ZXXX ;EG: EXPORT T{{[0-9]+}}.ZXXX
;EG: EXPORT T{{[0-9]+}}.XXWX ;EG: EXPORT T{{[0-9]+}}.XXWX
;EG: EXPORT T{{[0-9]+}}.XXXW ;EG: EXPORT T{{[0-9]+}}.XXXW
define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_shader void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = extractelement <4 x float> %reg1, i32 2 %2 = extractelement <4 x float> %reg1, i32 2
%3 = extractelement <4 x float> %reg1, i32 3 %3 = extractelement <4 x float> %reg1, i32 3
%4 = load <4 x float>, <4 x float> addrspace(8)* null %4 = load <4 x float>, <4 x float> addrspace(8)* null
%5 = extractelement <4 x float> %4, i32 1 %5 = extractelement <4 x float> %4, i32 1
%6 = load <4 x float>, <4 x float> addrspace(8)* null %6 = load <4 x float>, <4 x float> addrspace(8)* null
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Linesmain_body:
call void @llvm.R600.store.swizzle(<4 x float> %75, i32 3, i32 2) call void @llvm.R600.store.swizzle(<4 x float> %75, i32 3, i32 2)
ret void ret void
} }
; EG: {{^}}main2: ; EG: {{^}}main2:
; EG: T{{[0-9]+}}.XY__ ; EG: T{{[0-9]+}}.XY__
; EG: T{{[0-9]+}}.ZXY0 ; EG: T{{[0-9]+}}.ZXY0
define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { define amdgpu_shader void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 {
main_body: main_body:
%0 = extractelement <4 x float> %reg1, i32 0 %0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1 %1 = extractelement <4 x float> %reg1, i32 1
%2 = fadd float %0, 2.5 %2 = fadd float %0, 2.5
%3 = fmul float %1, 3.5 %3 = fmul float %1, 3.5
%4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
%5 = extractelement <4 x float> %4, i32 0 %5 = extractelement <4 x float> %4, i32 0
%6 = call float @llvm.cos.f32(float %5) %6 = call float @llvm.cos.f32(float %5)
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test/CodeGen/AMDGPU/tex-clause-antidep.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: TEX ;CHECK: TEX
;CHECK-NEXT: ALU ;CHECK-NEXT: ALU
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
%1 = extractelement <4 x float> %reg0, i32 0 %1 = extractelement <4 x float> %reg0, i32 0
%2 = extractelement <4 x float> %reg0, i32 1 %2 = extractelement <4 x float> %reg0, i32 1
%3 = extractelement <4 x float> %reg0, i32 2 %3 = extractelement <4 x float> %reg0, i32 2
%4 = extractelement <4 x float> %reg0, i32 3 %4 = extractelement <4 x float> %reg0, i32 3
%5 = insertelement <4 x float> undef, float %1, i32 0 %5 = insertelement <4 x float> undef, float %1, i32 0
%6 = insertelement <4 x float> %5, float %2, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 1
%7 = insertelement <4 x float> %6, float %3, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 2
%8 = insertelement <4 x float> %7, float %4, i32 3 %8 = insertelement <4 x float> %7, float %4, i32 3
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test/CodeGen/AMDGPU/texture-input-merge.ll

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK-NOT: MOV ;CHECK-NOT: MOV
define void @test(<4 x float> inreg %reg0) #0 { define amdgpu_shader void @test(<4 x float> inreg %reg0) #0 {
%1 = extractelement <4 x float> %reg0, i32 0 %1 = extractelement <4 x float> %reg0, i32 0
%2 = extractelement <4 x float> %reg0, i32 1 %2 = extractelement <4 x float> %reg0, i32 1
%3 = extractelement <4 x float> %reg0, i32 2 %3 = extractelement <4 x float> %reg0, i32 2
%4 = extractelement <4 x float> %reg0, i32 3 %4 = extractelement <4 x float> %reg0, i32 3
%5 = fmul float %1, 3.0 %5 = fmul float %1, 3.0
%6 = fmul float %2, 3.0 %6 = fmul float %2, 3.0
%7 = fmul float %3, 3.0 %7 = fmul float %3, 3.0
%8 = fmul float %4, 3.0 %8 = fmul float %4, 3.0
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test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll

;RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s --check-prefix=CHECK ;RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s --check-prefix=CHECK
; Test a simple uniform loop that lives inside non-uniform control flow. ; Test a simple uniform loop that lives inside non-uniform control flow.
;CHECK-LABEL: {{^}}test1: ;CHECK-LABEL: {{^}}test1:
;CHECK: s_cbranch_execz ;CHECK: s_cbranch_execz
;CHECK: %loop_body ;CHECK: %loop_body
define void @test1(<8 x i32> inreg %rsrc, <2 x i32> %addr.base, i32 %y, i32 %p) #0 { define amdgpu_shader void @test1(<8 x i32> inreg %rsrc, <2 x i32> %addr.base, i32 %y, i32 %p) #0 {
main_body: main_body:
%cc = icmp eq i32 %p, 0 %cc = icmp eq i32 %p, 0
br i1 %cc, label %out, label %loop_body br i1 %cc, label %out, label %loop_body
loop_body: loop_body:
%counter = phi i32 [ 0, %main_body ], [ %incr, %loop_body ] %counter = phi i32 [ 0, %main_body ], [ %incr, %loop_body ]
; Prevent the loop from being optimized out ; Prevent the loop from being optimized out
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test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll

Show All 18 Lines
; s12 is offset user SGPR ; s12 is offset user SGPR
; GCN: buffer_store_dword {{v[0-9]+}}, s[12:15], s11 offset:{{[0-9]+}} ; 16-byte Folded Spill ; GCN: buffer_store_dword {{v[0-9]+}}, s[12:15], s11 offset:{{[0-9]+}} ; 16-byte Folded Spill
; GCN: buffer_load_dword v{{[0-9]+}}, s[12:15], s11 offset:{{[0-9]+}} ; 16-byte Folded Reload ; GCN: buffer_load_dword v{{[0-9]+}}, s[12:15], s11 offset:{{[0-9]+}} ; 16-byte Folded Reload
; GCN: NumVgprs: 256 ; GCN: NumVgprs: 256
; GCN: ScratchSize: 1024 ; GCN: ScratchSize: 1024
define void @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <16 x i8>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { define amdgpu_shader void @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <16 x i8>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
bb: bb:
%tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i64 0, i64 0 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i64 0, i64 0
%tmp11 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, align 16, !tbaa !0 %tmp11 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, align 16, !tbaa !0
%tmp12 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 0) %tmp12 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 0)
%tmp13 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 16) %tmp13 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 16)
%tmp14 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 32) %tmp14 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 32)
%tmp15 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %arg4, i64 0, i64 0 %tmp15 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %arg4, i64 0, i64 0
%tmp16 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp15, align 16, !tbaa !0 %tmp16 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp15, align 16, !tbaa !0
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test/CodeGen/AMDGPU/wait.ll

; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX ; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX ; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; The ilpmax scheduler is used for the second test to get the ordering we want for the test. ; The ilpmax scheduler is used for the second test to get the ordering we want for the test.
; DEFAULT-LABEL: {{^}}main: ; DEFAULT-LABEL: {{^}}main:
; DEFAULT: s_load_dwordx4 ; DEFAULT: s_load_dwordx4
; DEFAULT: s_load_dwordx4 ; DEFAULT: s_load_dwordx4
; DEFAULT: s_waitcnt vmcnt(0) ; DEFAULT: s_waitcnt vmcnt(0)
; DEFAULT: exp ; DEFAULT: exp
; DEFAULT: s_waitcnt lgkmcnt(0) ; DEFAULT: s_waitcnt lgkmcnt(0)
; DEFAULT: s_endpgm ; DEFAULT: s_endpgm
define void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) #0 { define amdgpu_shader void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) #0 {
main_body: main_body:
%tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 0 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 0
%tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
%tmp11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp10, i32 0, i32 %arg6) %tmp11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp10, i32 0, i32 %arg6)
%tmp12 = extractelement <4 x float> %tmp11, i32 0 %tmp12 = extractelement <4 x float> %tmp11, i32 0
%tmp13 = extractelement <4 x float> %tmp11, i32 1 %tmp13 = extractelement <4 x float> %tmp11, i32 1
call void @llvm.amdgcn.s.barrier() #1 call void @llvm.amdgcn.s.barrier() #1
%tmp14 = extractelement <4 x float> %tmp11, i32 2 %tmp14 = extractelement <4 x float> %tmp11, i32 2
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; ILPMAX: buffer_load ; ILPMAX: buffer_load
; ILPMAX: s_load_dwordx4 ; ILPMAX: s_load_dwordx4
; ILPMAX: s_waitcnt lgkmcnt(0) ; ILPMAX: s_waitcnt lgkmcnt(0)
; ILPMAX: buffer_load ; ILPMAX: buffer_load
; ILPMAX: s_waitcnt vmcnt(1) ; ILPMAX: s_waitcnt vmcnt(1)
; ILPMAX: s_waitcnt vmcnt(0) ; ILPMAX: s_waitcnt vmcnt(0)
; ILPMAX: s_endpgm ; ILPMAX: s_endpgm
define void @main2([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* define amdgpu_shader void @main2([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)*
byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body: main_body:
%11 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %11 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0
%12 = load <16 x i8>, <16 x i8> addrspace(2)* %11, align 16, !tbaa !0 %12 = load <16 x i8>, <16 x i8> addrspace(2)* %11, align 16, !tbaa !0
%13 = add i32 %5, %7 %13 = add i32 %5, %7
%14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13) %14 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %12, i32 0, i32 %13)
%15 = extractelement <4 x float> %14, i32 0 %15 = extractelement <4 x float> %14, i32 0
%16 = extractelement <4 x float> %14, i32 1 %16 = extractelement <4 x float> %14, i32 1
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test/CodeGen/AMDGPU/wqm.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI
; Check that WQM isn't triggered by image load/store intrinsics. ; Check that WQM isn't triggered by image load/store intrinsics.
; ;
;CHECK-LABEL: {{^}}test1: ;CHECK-LABEL: {{^}}test1:
;CHECK-NOT: s_wqm ;CHECK-NOT: s_wqm
define <4 x float> @test1(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 { define amdgpu_shader <4 x float> @test1(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) %tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
call void @llvm.amdgcn.image.store.v4i32(<4 x float> %tex, <4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) call void @llvm.amdgcn.image.store.v4i32(<4 x float> %tex, <4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
ret <4 x float> %tex ret <4 x float> %tex
} }
; Check that WQM is triggered by image samples and left untouched for loads... ; Check that WQM is triggered by image samples and left untouched for loads...
; ;
;CHECK-LABEL: {{^}}test2: ;CHECK-LABEL: {{^}}test2:
;CHECK-NEXT: ; %main_body ;CHECK-NEXT: ; %main_body
;CHECK-NEXT: s_wqm_b64 exec, exec ;CHECK-NEXT: s_wqm_b64 exec, exec
;CHECK: image_sample ;CHECK: image_sample
;CHECK-NOT: exec ;CHECK-NOT: exec
;CHECK: _load_dword v0, ;CHECK: _load_dword v0,
define float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) #0 { define amdgpu_shader float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) #0 {
main_body: main_body:
%c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%c.2 = bitcast <4 x float> %c.1 to <4 x i32> %c.2 = bitcast <4 x float> %c.1 to <4 x i32>
%c.3 = extractelement <4 x i32> %c.2, i32 0 %c.3 = extractelement <4 x i32> %c.2, i32 0
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3 %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3
%data = load float, float addrspace(1)* %gep %data = load float, float addrspace(1)* %gep
ret float %data ret float %data
} }
; ... but disabled for stores (and, in this simple case, not re-enabled). ; ... but disabled for stores (and, in this simple case, not re-enabled).
; ;
;CHECK-LABEL: {{^}}test3: ;CHECK-LABEL: {{^}}test3:
;CHECK-NEXT: ; %main_body ;CHECK-NEXT: ; %main_body
;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
;CHECK-NEXT: s_wqm_b64 exec, exec ;CHECK-NEXT: s_wqm_b64 exec, exec
;CHECK: image_sample ;CHECK: image_sample
;CHECK: s_and_b64 exec, exec, [[ORIG]] ;CHECK: s_and_b64 exec, exec, [[ORIG]]
;CHECK: store ;CHECK: store
;CHECK-NOT: exec ;CHECK-NOT: exec
define <4 x float> @test3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) #0 { define amdgpu_shader <4 x float> @test3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%tex.1 = bitcast <4 x float> %tex to <4 x i32> %tex.1 = bitcast <4 x float> %tex to <4 x i32>
%tex.2 = extractelement <4 x i32> %tex.1, i32 0 %tex.2 = extractelement <4 x i32> %tex.1, i32 0
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %tex.2 %gep = getelementptr float, float addrspace(1)* %ptr, i32 %tex.2
%wr = extractelement <4 x float> %tex, i32 1 %wr = extractelement <4 x float> %tex, i32 1
store float %wr, float addrspace(1)* %gep store float %wr, float addrspace(1)* %gep
ret <4 x float> %tex ret <4 x float> %tex
} }
; Check that WQM is re-enabled when required. ; Check that WQM is re-enabled when required.
; ;
;CHECK-LABEL: {{^}}test4: ;CHECK-LABEL: {{^}}test4:
;CHECK-NEXT: ; %main_body ;CHECK-NEXT: ; %main_body
;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
;CHECK-NEXT: s_wqm_b64 exec, exec ;CHECK-NEXT: s_wqm_b64 exec, exec
;CHECK: v_mul_lo_i32 [[MUL:v[0-9]+]], v0, v1 ;CHECK: v_mul_lo_i32 [[MUL:v[0-9]+]], v0, v1
;CHECK: s_and_b64 exec, exec, [[ORIG]] ;CHECK: s_and_b64 exec, exec, [[ORIG]]
;CHECK: store ;CHECK: store
;CHECK: s_wqm_b64 exec, exec ;CHECK: s_wqm_b64 exec, exec
;CHECK: image_sample v[0:3], [[MUL]], s[0:7], s[8:11] dmask:0xf ;CHECK: image_sample v[0:3], [[MUL]], s[0:7], s[8:11] dmask:0xf
define <4 x float> @test4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %d, float %data) #0 { define amdgpu_shader <4 x float> @test4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %d, float %data) #0 {
main_body: main_body:
%c.1 = mul i32 %c, %d %c.1 = mul i32 %c, %d
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.1 %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.1
store float %data, float addrspace(1)* %gep store float %data, float addrspace(1)* %gep
%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c.1, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c.1, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
ret <4 x float> %tex ret <4 x float> %tex
} }
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
;CHECK-NEXT: s_wqm_b64 exec, exec ;CHECK-NEXT: s_wqm_b64 exec, exec
;CHECK: %ELSE ;CHECK: %ELSE
;CHECK: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[ORIG]] ;CHECK: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
;CHECK: store ;CHECK: store
;CHECK: s_mov_b64 exec, [[SAVED]] ;CHECK: s_mov_b64 exec, [[SAVED]]
;CHECK: %IF ;CHECK: %IF
;CHECK: image_sample ;CHECK: image_sample
define float @test_control_flow_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %z, float %data) #0 { define amdgpu_shader float @test_control_flow_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %z, float %data) #0 {
main_body: main_body:
%cmp = icmp eq i32 %z, 0 %cmp = icmp eq i32 %z, 0
br i1 %cmp, label %IF, label %ELSE br i1 %cmp, label %IF, label %ELSE
IF: IF:
%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%data.if = extractelement <4 x float> %tex, i32 0 %data.if = extractelement <4 x float> %tex, i32 0
br label %END br label %END
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;CHECK: %Flow ;CHECK: %Flow
;CHECK-NEXT: s_or_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], ;CHECK-NEXT: s_or_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]],
;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]] ;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]]
;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]] ;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]]
;CHECK-NEXT: s_xor_b64 exec, exec, [[SAVED]] ;CHECK-NEXT: s_xor_b64 exec, exec, [[SAVED]]
;CHECK-NEXT: %ELSE ;CHECK-NEXT: %ELSE
;CHECK: store ;CHECK: store
;CHECK: %END ;CHECK: %END
define float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %z, float %data) #0 { define amdgpu_shader float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %z, float %data) #0 {
main_body: main_body:
%cmp = icmp eq i32 %z, 0 %cmp = icmp eq i32 %z, 0
br i1 %cmp, label %ELSE, label %IF br i1 %cmp, label %ELSE, label %IF
IF: IF:
%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%data.if = extractelement <4 x float> %tex, i32 0 %data.if = extractelement <4 x float> %tex, i32 0
br label %END br label %END
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;CHECK: s_and_b64 exec, exec, [[ORIG]] ;CHECK: s_and_b64 exec, exec, [[ORIG]]
;CHECK: store ;CHECK: store
;CHECK: s_wqm_b64 exec, exec ;CHECK: s_wqm_b64 exec, exec
;CHECK: load ;CHECK: load
;CHECK: s_and_b64 exec, exec, [[ORIG]] ;CHECK: s_and_b64 exec, exec, [[ORIG]]
;CHECK: store ;CHECK: store
;CHECK: s_wqm_b64 exec, exec ;CHECK: s_wqm_b64 exec, exec
;CHECK: v_cmp ;CHECK: v_cmp
define <4 x float> @test_control_flow_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <3 x i32> %idx, <2 x float> %data, i32 %coord) #0 { define amdgpu_shader <4 x float> @test_control_flow_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <3 x i32> %idx, <2 x float> %data, i32 %coord) #0 {
main_body: main_body:
%idx.1 = extractelement <3 x i32> %idx, i32 0 %idx.1 = extractelement <3 x i32> %idx, i32 0
%gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1 %gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1
%data.1 = extractelement <2 x float> %data, i32 0 %data.1 = extractelement <2 x float> %data, i32 0
store float %data.1, float addrspace(1)* %gep.1 store float %data.1, float addrspace(1)* %gep.1
; The load that determines the branch (and should therefore be WQM) is ; The load that determines the branch (and should therefore be WQM) is
; surrounded by stores that require disabled WQM. ; surrounded by stores that require disabled WQM.
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
;CHECK-NEXT: s_wqm_b64 exec, exec ;CHECK-NEXT: s_wqm_b64 exec, exec
;CHECK: image_sample ;CHECK: image_sample
;CHECK: s_and_b64 exec, exec, [[ORIG]] ;CHECK: s_and_b64 exec, exec, [[ORIG]]
;CHECK: store ;CHECK: store
;CHECK: load ;CHECK: load
;CHECK: store ;CHECK: store
;CHECK: v_cmp ;CHECK: v_cmp
define float @test_control_flow_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <3 x i32> %idx, <2 x float> %data, i32 %coord) #0 { define amdgpu_shader float @test_control_flow_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <3 x i32> %idx, <2 x float> %data, i32 %coord) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%tex.1 = extractelement <4 x float> %tex, i32 0 %tex.1 = extractelement <4 x float> %tex, i32 0
%idx.1 = extractelement <3 x i32> %idx, i32 0 %idx.1 = extractelement <3 x i32> %idx, i32 0
%gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1 %gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1
%data.1 = extractelement <2 x float> %data, i32 0 %data.1 = extractelement <2 x float> %data, i32 0
store float %data.1, float addrspace(1)* %gep.1 store float %data.1, float addrspace(1)* %gep.1
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;CHECK-NEXT: s_wqm_b64 exec, exec ;CHECK-NEXT: s_wqm_b64 exec, exec
;CHECK: %IF ;CHECK: %IF
;CHECK: load ;CHECK: load
;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]] ;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
;CHECK: store ;CHECK: store
;CHECK: s_mov_b64 exec, [[SAVE]] ;CHECK: s_mov_b64 exec, [[SAVE]]
;CHECK: %END ;CHECK: %END
;CHECK: image_sample ;CHECK: image_sample
define <4 x float> @test_control_flow_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %coord, i32 %y, float %z) #0 { define amdgpu_shader <4 x float> @test_control_flow_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %coord, i32 %y, float %z) #0 {
main_body: main_body:
%cond = icmp eq i32 %y, 0 %cond = icmp eq i32 %y, 0
br i1 %cond, label %IF, label %END br i1 %cond, label %IF, label %END
IF: IF:
%data = load float, float addrspace(1)* %ptr %data = load float, float addrspace(1)* %ptr
%gep = getelementptr float, float addrspace(1)* %ptr, i32 1 %gep = getelementptr float, float addrspace(1)* %ptr, i32 1
store float %data, float addrspace(1)* %gep store float %data, float addrspace(1)* %gep
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;VI: flat_store_dword ;VI: flat_store_dword
;CHECK: s_wqm_b64 exec, exec ;CHECK: s_wqm_b64 exec, exec
;CHECK: v_cmpx_ ;CHECK: v_cmpx_
;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]] ;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
;SI: buffer_store_dword ;SI: buffer_store_dword
;VI: flat_store_dword ;VI: flat_store_dword
;CHECK: s_mov_b64 exec, [[SAVE]] ;CHECK: s_mov_b64 exec, [[SAVE]]
;CHECK: image_sample ;CHECK: image_sample
define <4 x float> @test_kill_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <2 x i32> %idx, <2 x float> %data, i32 %coord, i32 %coord2, float %z) #0 { define amdgpu_shader <4 x float> @test_kill_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <2 x i32> %idx, <2 x float> %data, i32 %coord, i32 %coord2, float %z) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%idx.0 = extractelement <2 x i32> %idx, i32 0 %idx.0 = extractelement <2 x i32> %idx, i32 0
%gep.0 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.0 %gep.0 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.0
%data.0 = extractelement <2 x float> %data, i32 0 %data.0 = extractelement <2 x float> %data, i32 0
store float %data.0, float addrspace(1)* %gep.0 store float %data.0, float addrspace(1)* %gep.0
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
;CHECK-NEXT: s_wqm_b64 exec, exec ;CHECK-NEXT: s_wqm_b64 exec, exec
;CHECK: image_sample ;CHECK: image_sample
;CHECK: s_and_b64 exec, exec, [[ORIG]] ;CHECK: s_and_b64 exec, exec, [[ORIG]]
;SI: buffer_store_dword ;SI: buffer_store_dword
;VI: flat_store_dword ;VI: flat_store_dword
;CHECK-NOT: wqm ;CHECK-NOT: wqm
;CHECK: v_cmpx_ ;CHECK: v_cmpx_
define <4 x float> @test_kill_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %idx, float %data, i32 %coord, i32 %coord2, float %z) #0 { define amdgpu_shader <4 x float> @test_kill_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %idx, float %data, i32 %coord, i32 %coord2, float %z) #0 {
main_body: main_body:
%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %idx %gep = getelementptr float, float addrspace(1)* %ptr, i32 %idx
store float %data, float addrspace(1)* %gep store float %data, float addrspace(1)* %gep
call void @llvm.AMDGPU.kill(float %z) call void @llvm.AMDGPU.kill(float %z)
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