Skeleton for the IR level pass to perform 64bit Integer Division

[Uthkarsh]

Summary

This contains the required pass for performing the 64bit integer division at the IR level. The algorithm has not been incorporated yet but just the skeleton is given for review.

[arsenm]

include/llvm/CodeGen/Passes.h

395–397

These parts touching generic code should be removed since it is a backend pass now. The IDs etc. declarations should be only in AMDGPU.h

lib/Target/AMDGPU/AMDGPU.h

89

Description comments should be in the pass file instead

lib/Target/AMDGPU/AMDGPU64bitDivision.cpp

8

There should not be a free function like this. This should be a method of the pass

lib/Target/AMDGPU/AMDGPU64bitDivision.h

1–2

This header is unnecessary, this can be done entirely in the one cpp file

3–6

You don't need these

8–14

Also any of these

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

256–257

This looks like an unrelated change, and is also incorrect since this should work already. i32 has an instruction and i64 should already be expanded

259–261

Random whitespace change

lib/Target/AMDGPU/AMDGPUIntegerDivisionPass.cpp

1

Name out of date

9–11

This should have a description or be removed

13

AMDGPU.h should be the first included file

27

This should be all lower case and - separated, otherwise it won't really work as a -debug-only= argument

37

This should be removed

67

Dead code

70–74

Dead code

90–91

You're going to need to pre-increment this pointer to avoid iterator invalidation issues when you delete the original div instruction

93

You can pre-increment the iterators to avoid skipping back to the beginning

106

You can do Type->isIntegerTy(64)

150

This shouldn't be here

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

39

Random whitespace

56

Comment not needed

207

Comments should never include names

208

I think this should be moved to addCodeGenPrepare after TargetPassConfig::addCodeGenPrepare()

[• tstellarAMD]

include/llvm/CodeGen/Passes.h

395–397

Since this is a target specific pass the ID should be defined in AMDGPU.h like the other AMDGPU passes.

652–653

This should go in AMDGPU.h too.

include/llvm/InitializePasses.h

152

This in AMDGPU.h too.

include/llvm/LinkAllPasses.h

148–149

I don't think this is needed.

[Uthkarsh]

Have modified most of the requested changes.

[Uthkarsh]

Unnecessary comments deleted.

[arsenm]

The current diff seems to be just the comment changes

[Uthkarsh]

Consolidated diff of the previous commits, along with the changes.

include/llvm/CodeGen/Passes.h

namespace llvm {
   /// createCodeGenPreparePass - Transform the code to expose more pattern
   /// matching during instruction selection.
   FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
 
   /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
   /// load-linked/store-conditional loops.
   extern char &AtomicExpandID;
 
+  /// Lowers unsupported integer division.
+  extern char &IntegerDivisionID;
+
   /// MachineLoopInfo - This pass is a loop analysis pass.
   extern char &MachineLoopInfoID;
 
   /// MachineDominators - This pass is a machine dominators analysis pass.
   extern char &MachineDominatorsID;
 
 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
   extern char &MachineDominanceFrontierID;
/// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
   extern char &StackMapLivenessID;
 
   /// LiveDebugValues pass
   extern char &LiveDebugValuesID;
 
   /// createJumpInstrTables - This pass creates jump-instruction tables.
   ModulePass *createJumpInstrTablesPass();
 
+  /// Lower unsupported integer division
+  FunctionPass *createIntegerDivisionPass(const TargetMachine *TM);
+
   /// createForwardControlFlowIntegrityPass - This pass adds control-flow
   /// integrity.
   ModulePass *createForwardControlFlowIntegrityPass();
 
   /// InterleavedAccess Pass - This pass identifies and matches interleaved
   /// memory accesses to target specific intrinsics.
   ///
   FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);

include/llvm/InitializePasses.h

 void initializeIfConverterPass(PassRegistry&);
 void initializeInductiveRangeCheckEliminationPass(PassRegistry&);
 void initializeIndVarSimplifyPass(PassRegistry&);
 void initializeInferFunctionAttrsLegacyPassPass(PassRegistry&);
 void initializeInlineCostAnalysisPass(PassRegistry&);
 void initializeInstructionCombiningPassPass(PassRegistry&);
 void initializeInstCountPass(PassRegistry&);
 void initializeInstNamerPass(PassRegistry&);
+void initializeIntegerDivisionPass(PassRegistry&);
 void initializeInternalizePassPass(PassRegistry&);
 void initializeIntervalPartitionPass(PassRegistry&);
 void initializeJumpThreadingPass(PassRegistry&);
 void initializeLCSSAPass(PassRegistry&);
 void initializeLICMPass(PassRegistry&);
 void initializeLazyValueInfoPass(PassRegistry&);
 void initializeLintPass(PassRegistry&);
 void initializeLiveDebugVariablesPass(PassRegistry&);

include/llvm/LinkAllPasses.h

ForcePassLinking() {
       (void) llvm::createScalarReplAggregatesPass();
       (void) llvm::createSingleLoopExtractorPass();
       (void) llvm::createStripSymbolsPass();
       (void) llvm::createStripNonDebugSymbolsPass();
       (void) llvm::createStripDeadDebugInfoPass();
       (void) llvm::createStripDeadPrototypesPass();
       (void) llvm::createTailCallEliminationPass();
       (void) llvm::createJumpThreadingPass();
+      /*AMDGPU64bit*/
+      //(void) llvm::createIntegerDivisionPass(nullptr);
       (void) llvm::createUnifyFunctionExitNodesPass();
       (void) llvm::createInstCountPass();
       (void) llvm::createConstantHoistingPass();
       (void) llvm::createCodeGenPreparePass();
       (void) llvm::createEarlyCSEPass();
       (void) llvm::createMergedLoadStoreMotionPass();
       (void) llvm::createGVNPass();
       (void) llvm::createMemCpyOptPass();

include/llvm/Target/TargetLowering.h

protected:
   /// \brief Initialize all of the actions to default values.
   void initActions();
 
 public:
   const TargetMachine &getTargetMachine() const { return TM; }
 
   virtual bool useSoftFloat() const { return false; }
 
+  /// Returns true if the instruction should be expanded by the IR-level
+  /// IntegerDivision pass.
+  virtual bool shouldExpandDivRemInIR(const BinaryOperator &I) const {
+    return false;
+  }
+
   /// Return the pointer type for the given address space, defaults to
   /// the pointer type from the data layout.
   /// FIXME: The default needs to be removed once all the code is updated.
   MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
     return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
   }
 
   /// EVT is not used in-tree, but is used by out-of-tree target.

lib/Target/AMDGPU/AMDGPU.h

 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
 FunctionPass *createSIFixSGPRCopiesPass();
 FunctionPass *createSIFixSGPRLiveRangesPass();
 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
 FunctionPass *createSIInsertWaits(TargetMachine &tm);
 
 ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
+/*Modified Integer Division*/
+FunctionPass *createAMDGPUIntegerDivisionPass(const TargetMachine *TM);
+extern char &AMDGPUIntegerDivisionID;
+
 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
 extern char &AMDGPUAnnotateKernelFeaturesID;
 
 void initializeSIFoldOperandsPass(PassRegistry &);
 extern char &SIFoldOperandsID;
 
 void initializeSIFixSGPRCopiesPass(PassRegistry &);
 extern char &SIFixSGPRCopiesID;

 extern char &SIFixControlFlowLiveIntervalsID;
 
 void initializeSIFixSGPRLiveRangesPass(PassRegistry&);
 extern char &SIFixSGPRLiveRangesID;
 
 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
 extern char &AMDGPUAnnotateUniformValuesPassID;
 
+/*Modified Integer Division : IR Pass to perform 64bit integer division*/
+
+void initializeAMDGPUIntegerDivisionPass(PassRegistry&);
+extern char AMDGPU64bitDivisionID;
+
+
 extern Target TheAMDGPUTarget;
 extern Target TheGCNTarget;
 
 namespace AMDGPU {
 enum TargetIndex {
   TI_CONSTDATA_START,
   TI_SCRATCH_RSRC_DWORD0,
   TI_SCRATCH_RSRC_DWORD1,

lib/Target/AMDGPU/AMDGPU64bitDivision.h

+#include "AMDGPUISelLowering.h"
+#include "AMDGPU.h"
+#include "AMDGPUDiagnosticInfoUnsupported.h"
+#include "AMDGPUFrameLowering.h"
+#include "AMDGPUIntrinsicInfo.h"
+#include "AMDGPURegisterInfo.h"
+#include "AMDGPUSubtarget.h"
+#include "R600MachineFunctionInfo.h"
+#include "SIMachineFunctionInfo.h"
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/IRBuilder.h"
+
+namespace llvm
+{
+  class BinaryOperator;
+}
+
+namespace llvm{
+
+
+
+bool AMDExpandUDivision(BinaryOperator *Div);
+
+}
 No newline at end of file

lib/Target/AMDGPU/AMDGPU64bitDivision.cpp

+#include "AMDGPU64bitDivision.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/IR/Instructions.h"
+
+using namespace llvm;
+
+
+bool llvm::AMDExpandUDivision(BinaryOperator *Div)
+{
+
+  errs()<<"\n AMDExpandUDivision Called\n";
+
+  return true;
+
+}

lib/Target/AMDGPU/AMDGPUISelLowering.h

void getOriginalFunctionArgs(SelectionDAG &DAG,
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                SmallVectorImpl<ISD::InputArg> &OrigIns) const;
   void AnalyzeFormalArguments(CCState &State,
                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
 
 public:
   AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
 
+  bool shouldExpandDivRemInIR(const BinaryOperator &I) const override {
+    return true;
+  }
+
   bool isFAbsFree(EVT VT) const override;
   bool isFNegFree(EVT VT) const override;
   bool isTruncateFree(EVT Src, EVT Dest) const override;
   bool isTruncateFree(Type *Src, Type *Dest) const override;
 
   bool isZExtFree(Type *Src, Type *Dest) const override;
   bool isZExtFree(EVT Src, EVT Dest) const override;
   bool isZExtFree(SDValue Val, EVT VT2) const override;

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

for (MVT VT : ScalarIntVTs) {
 
     // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
     setOperationAction(ISD::UMUL_LOHI, VT, Expand);
 
     setOperationAction(ISD::BSWAP, VT, Expand);
     setOperationAction(ISD::CTTZ, VT, Expand);
     setOperationAction(ISD::CTLZ, VT, Expand);
+
+    setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
   }
 
+
+
   if (!Subtarget->hasBCNT(32))
     setOperationAction(ISD::CTPOP, MVT::i32, Expand);
 
   if (!Subtarget->hasBCNT(64))
     setOperationAction(ISD::CTPOP, MVT::i64, Expand);
 
   // The hardware supports 32-bit ROTR, but not ROTL.
   setOperationAction(ISD::ROTL, MVT::i32, Expand);
SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
 
   SDValue Res[2] = {
     Div,
     Rem
   };
   return DAG.getMergeValues(Res, DL);
 }
 
+// FIXME: This seems to be extremely inefficient. SC produces almost 1/3rd as
+// many instructions for i64 udiv.
 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
                                       SelectionDAG &DAG,
                                       SmallVectorImpl<SDValue> &Results) const {
   assert(Op.getValueType() == MVT::i64);
 
   SDLoc DL(Op);
   EVT VT = Op.getValueType();
   EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());

lib/Target/AMDGPU/AMDGPUIntegerDivisionPass.cpp

+//===-- IntegerDivisionPass.cpp - Expand div/mod instructions -------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+//===----------------------------------------------------------------------===//
+
+/*Modified Integer Division Pass*/
+
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/InstVisitor.h"
+#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/Transforms/Utils/IntegerDivision.h"
+#include "AMDGPU.h"
+#include "AMDGPU64bitDivision.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "AMDGPU integer-division"
+
+namespace {
+
+class AMDGPUIntegerDivision : public FunctionPass,
+                        public InstVisitor<AMDGPUIntegerDivision, bool> {
+
+  const TargetMachine *TM;
+  const TargetLowering *TLI;
+
+  int checkingVariable;                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 
+
+  bool shouldExpandDivRem(const BinaryOperator &I);
+
+public:
+  static char ID;
+  explicit AMDGPUIntegerDivision(const TargetMachine *TM = nullptr)
+    : FunctionPass(ID), TM(TM), TLI(nullptr) {
+  }
+
+  bool doInitialization(Module &M) override;
+  bool runOnFunction(Function &F) override;
+
+  const char *getPassName() const override {
+    return "Integer Division Pass";
+  }
+
+  bool visitInstruction(Instruction &I) {
+    return false;
+  }
+
+  bool visitSDiv(BinaryOperator &I);
+  bool visitUDiv(BinaryOperator &I);
+  bool visitSRem(BinaryOperator &I);
+  bool visitURem(BinaryOperator &I);
+};
+
+} // End anonymous namespace
+
+char AMDGPUIntegerDivision::ID = 0;
+//char &llvm::IntegerDivisionID = AMDGPUIntegerDivision::ID;
+INITIALIZE_TM_PASS(AMDGPUIntegerDivision, DEBUG_TYPE,"Expand integer division", false, false);
+
+char &llvm::AMDGPUIntegerDivisionID = AMDGPUIntegerDivision::ID;
+/*INITIALIZE_PASS_BEGIN(AMDGPUIntegerDivision, DEBUG_TYPE,
+                      "Add AMDGPU function attributes", false, false)
+INITIALIZE_PASS_END(AMDGPUIntegerDivision, DEBUG_TYPE,
+                    "Add AMDGPU function attributes", false, false)*/
+
+bool AMDGPUIntegerDivision::doInitialization(Module &M) {
+  return false;
+}
+
+bool AMDGPUIntegerDivision::runOnFunction(Function &F) {
+//  llvm_unreachable("does this happen");
+  if (TM)
+    TLI = TM->getSubtargetImpl(F)->getTargetLowering();
+
+  else 
+    errs()<<"\n Target Machine Not Initialized\n";
+
+  for (Function::iterator BBI = F.begin(), BBE = F.end(); BBI != BBE; ++BBI) {
+    BasicBlock *BB = &*BBI;
+    for (BasicBlock::iterator II = BB->begin(), IE = BB->end(); II != IE; ++II) {
+      Instruction *I = &*II;
+      if (visit(*I)) {
+        BBI = F.begin();
+        break;
+      }
+    }
+  }
+
+  return false;
+}
+
+bool AMDGPUIntegerDivision::shouldExpandDivRem(const BinaryOperator &I) {
+  assert(TLI);
+  bool shouldExpandInIr = TLI && TLI->shouldExpandDivRemInIR(I);
+  // TODO:Uthkarsh later modify to handle signed 64 bit too.  
+  bool isUdiv64 = I.getOpcode() == Instruction::UDiv &&  I.getType()->getIntegerBitWidth() == 64;
+  return shouldExpandInIr && isUdiv64;
+}
+/*TODO:Uthkarsh 
+  Change the function calls to your own menthods instead of the in-built integer division which
+  introduces more control flow. 
+*/
+bool AMDGPUIntegerDivision::visitSDiv(BinaryOperator &I) {
+  if (shouldExpandDivRem(I)) {
+    expandDivision(&I);
+    return true;
+  }
+  return false;
+}
+
+bool AMDGPUIntegerDivision::visitUDiv(BinaryOperator &I) {
+  // Should call the underlying IR expansion only for 64 bit divisions
+  if (shouldExpandDivRem(I)) {
+    AMDExpandUDivision(&I);
+    return true;
+  }
+  return false;
+}
+
+bool AMDGPUIntegerDivision::visitSRem(BinaryOperator &I) {
+  if (shouldExpandDivRem(I)) {
+    expandRemainder(&I);
+    return true;
+  }
+  return false;
+}
+
+bool AMDGPUIntegerDivision::visitURem(BinaryOperator &I) {
+  if (shouldExpandDivRem(I)) {
+    expandRemainder(&I);
+    return true;
+  }
+  return false;
+}
+
+FunctionPass *llvm::createAMDGPUIntegerDivisionPass(const TargetMachine *TM) {
+  return new AMDGPUIntegerDivision(TM);
+}
+
+//static RegisterPass<AMDGPUIntegerDivision> X("AMD GPU Integer Division", "IR level 64 bit integer division",false,false);
 No newline at end of file

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_os_ostream.h"
 #include "llvm/Transforms/IPO.h"
 #include "llvm/Transforms/Scalar.h"
 #include <llvm/CodeGen/Passes.h>
 
+
 using namespace llvm;
 
 extern "C" void LLVMInitializeAMDGPUTarget() {
   // Register the target
   RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
   RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
 
   PassRegistry *PR = PassRegistry::getPassRegistry();
   initializeSILowerI1CopiesPass(*PR);
   initializeSIFixSGPRCopiesPass(*PR);
   initializeSIFoldOperandsPass(*PR);
   initializeSIFixSGPRLiveRangesPass(*PR);
   initializeSIFixControlFlowLiveIntervalsPass(*PR);
   initializeSILoadStoreOptimizerPass(*PR);
   initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
   initializeAMDGPUAnnotateUniformValuesPass(*PR);
+  /*Modified Integer Division Pass*/
+  initializeAMDGPUIntegerDivisionPass(*PR);
+
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
   if (TT.getOS() == Triple::AMDHSA)
     return make_unique<AMDGPUHSATargetObjectFile>();
 
   return make_unique<AMDGPUTargetObjectFile>();
 }
void AMDGPUPassConfig::addIRPasses() {
   // inlining pass will cause all of the PassConfigs passes to be run
   // one function at a time, which means if we have a nodule with two
   // functions, then we will generate code for the first function
   // without ever running any passes on the second.
   addPass(createBarrierNoopPass());
 
   // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
   addPass(createAMDGPUOpenCLImageTypeLoweringPass());
-
+  /*TODO:Uthkarsh - Integer Division*/
+  addPass(createAMDGPUIntegerDivisionPass(&getAMDGPUTargetMachine()));
   TargetPassConfig::addIRPasses();
 }
 
 void AMDGPUPassConfig::addCodeGenPrepare() {
   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
   if (ST.isPromoteAllocaEnabled()) {
     addPass(createAMDGPUPromoteAlloca(ST));
     addPass(createSROAPass());
   }
+
   TargetPassConfig::addCodeGenPrepare();
+
+  //  addPass(createIntegerDivisionPass(&getAMDGPUTargetMachine()));
 }
 
 bool
 AMDGPUPassConfig::addPreISel() {
   const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
   addPass(createFlattenCFGPass());
   if (ST.IsIRStructurizerEnabled())
     addPass(createStructurizeCFGPass());

lib/Target/AMDGPU/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
 
 tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
 add_public_tablegen_target(AMDGPUCommonTableGen)
 
 add_llvm_target(AMDGPUCodeGen
+  AMDGPU64bitDivision.cpp
+  AMDGPU64bitDivision.h
   AMDILCFGStructurizer.cpp
   AMDGPUAlwaysInlinePass.cpp
   AMDGPUAnnotateKernelFeatures.cpp
   AMDGPUAnnotateUniformValues.cpp
   AMDGPUAsmPrinter.cpp
   AMDGPUDiagnosticInfoUnsupported.cpp
   AMDGPUFrameLowering.cpp
   AMDGPUTargetObjectFile.cpp
   AMDGPUIntrinsicInfo.cpp
   AMDGPUISelDAGToDAG.cpp
   AMDGPUMCInstLower.cpp
   AMDGPUMachineFunction.cpp
   AMDGPUOpenCLImageTypeLoweringPass.cpp
   AMDGPUSubtarget.cpp
   AMDGPUTargetMachine.cpp
   AMDGPUTargetTransformInfo.cpp
   AMDGPUISelLowering.cpp
   AMDGPUInstrInfo.cpp
   AMDGPUPromoteAlloca.cpp
   AMDGPURegisterInfo.cpp
+  AMDGPUIntegerDivisionPass.cpp
   R600ClauseMergePass.cpp
   R600ControlFlowFinalizer.cpp
   R600EmitClauseMarkers.cpp
   R600ExpandSpecialInstrs.cpp
   R600InstrInfo.cpp
   R600ISelLowering.cpp
   R600MachineFunctionInfo.cpp
   R600MachineScheduler.cpp

tools/opt/opt.cpp

int main(int argc, char **argv) {
   initializeTransformUtils(Registry);
   initializeInstCombine(Registry);
   initializeInstrumentation(Registry);
   initializeTarget(Registry);
   // For codegen passes, only passes that do IR to IR transformation are
   // supported.
   initializeCodeGenPreparePass(Registry);
   initializeAtomicExpandPass(Registry);
+  initializeIntegerDivisionPass(Registry);
   initializeRewriteSymbolsPass(Registry);
   initializeWinEHPreparePass(Registry);
   initializeDwarfEHPreparePass(Registry);
   initializeSjLjEHPreparePass(Registry);
 
 #ifdef LINK_POLLY_INTO_TOOLS
   polly::initializePollyPasses(Registry);
 #endif