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Differential D18037

[mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructions
ClosedPublic

Authored by hvarga on Mar 10 2016, 5:43 AM.

Details

Reviewers
dsanders
zbuljan
vkalintiris
zoran.jovanovic
Commits
rL263203: [mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructions
Summary

While implementing MTC* and MFC* instructions for microMIPSr6, it was observed that some of those instructions don't have invalid tests for their immediate operands.

This patch adds invalid tests for following instructions:

  • MTC0
  • MTC2
  • MFC0
  • MFC2
  • DMTC0
  • DMFC0

Diff Detail

Repository
rL LLVM

Event Timeline

hvarga updated this revision to Diff 50263.Mar 10 2016, 5:43 AM
hvarga retitled this revision from to [mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructions.
hvarga updated this object.
hvarga added reviewers: zoran.jovanovic, zbuljan, dsanders.
hvarga added subscribers: llvm-commits, petarj, dsanders.
Herald added a reviewer: vkalintiris. · View Herald TranscriptMar 10 2016, 5:43 AM
dsanders accepted this revision.Mar 10 2016, 5:50 AM
dsanders edited edge metadata.

LGTM

This revision is now accepted and ready to land.Mar 10 2016, 5:50 AM
Closed by commit rL263203: [mips] Invalid tests for MTC0, MTC2, MFC0, MFC2, DMTC0, DMFC0 MIPS instructions (authored by hvarga). · Explain WhyMar 11 2016, 12:05 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
MC/
Mips/
mips32r5/
8 lines
mips32r6/
8 lines
mips64r5/
4 lines
mips64r6/
4 lines

Diff 50394

llvm/trunk/test/MC/Mips/mips32r5/invalid.s

# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. # Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
# invalid set of operands or operand's restrictions not met). # invalid set of operands or operand's restrictions not met).
# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r5 2>%t1 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r5 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.text .text
.set noreorder .set noreorder
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mtc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mtc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate

llvm/trunk/test/MC/Mips/mips32r6/invalid.s

Show All 33 Lineslocal_label:
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mtc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mtc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
mfc2 $4, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate

llvm/trunk/test/MC/Mips/mips64r5/invalid.s

# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. # Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
# invalid set of operands or operand's restrictions not met). # invalid set of operands or operand's restrictions not met).
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r5 2>%t1 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r5 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.text .text
.set noreorder .set noreorder
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate

llvm/trunk/test/MC/Mips/mips64r6/invalid.s

Show All 37 Lines .set noat
drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate