[mips][microMIPS] Implement LLX, LLXE, SCX and SCXE instructions

[zbuljan]

Summary

The patch implements microMIPSr6 LLX, LLXE, SCX and SCXE instructions.

[dsanders]

Hi Zlatko,

I understand that llx/scx/llxe/scxe are about to be significantly changed in the documentation. I therefore think it's best to defer this patch for now and come back to it later.

lib/Target/Mips/MicroMipsInstrInfo.td

267–282

This bit should still be fixed though. lle/sce have always has 9-bit offsets on microMIPS
Could you split it into a separate patch along with the relevant test cases?

[zbuljan]

Hi Daniel,

thanks for review.
I'll leave this patch unattended for now and update it after new documentation arrives.
Also, I'll create separate patch for 9-bit offsets.

[zbuljan]

Patch for 9-bit offset is placed on Phabricator at D18645.

[zbuljan]

LLX, LLXE, SCX and SCXE have been removed from spec.

lib/Target/Mips/MicroMips32r6InstrFormats.td

class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
   bits<32> Inst;
 
   let Inst{31-26} = op;
   let Inst{25-21} = rt;
   let Inst{20-16} = base;
   let Inst{15-0}  = offset;
 }
 
-class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
+class POOL32C_STORE_EVA_FM_MMR6<bits<4> funct, bits<3> fmt> {
   bits<5> rt;
   bits<21> addr;
   bits<5> base = addr{20-16};
   bits<9> offset = addr{8-0};
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b011000;
   let Inst{25-21} = rt;
   let Inst{20-16} = base;
-  let Inst{15-12} = 0b1010;
-  let Inst{11-9}  = funct;
+  let Inst{15-12} = funct;
+  let Inst{11-9}  = fmt;
   let Inst{8-0}   = offset;
 }
 
-class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
+class POOL32C_LOAD_WORD_EVA_FM_MMR6<bits<4> funct, bits<3> fmt> {
   bits<5> rt;
   bits<21> addr;
   bits<5> base = addr{20-16};
   bits<9> offset = addr{8-0};
 
   bits<32> Inst;
 
   let Inst{31-26} = 0b011000;
   let Inst{25-21} = rt;
   let Inst{20-16} = base;
-  let Inst{15-12} = 0b0110;
-  let Inst{11-9}  = funct;
+  let Inst{15-12} = funct;
+  let Inst{11-9}  = fmt;
   let Inst{8-0}   = offset;
 }
 
 class LOAD_WORD_FM_MMR6 {
   bits<5> rt;
   bits<21> addr;
   bits<5> base = addr{20-16};
   bits<16> offset = addr{15-0};

lib/Target/Mips/MicroMips32r6InstrInfo.td

 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
 class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
 class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
-class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
-class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
+class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1010, 0b100>;
+class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1010, 0b110>;
 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
-class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b101>;
-class LLE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b110>;
-class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
+class SHE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1010, 0b101>;
+class LLE_MMR6_ENC : POOL32C_LOAD_WORD_EVA_FM_MMR6<0b0110, 0b110>;
+class LWE_MMR6_ENC : POOL32C_LOAD_WORD_EVA_FM_MMR6<0b0110, 0b111>;
 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
 class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
                                                        0b11001100>;

 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 class LI16_MMR6_ENC : LI_FM_MM16;
 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
+class LLX_MMR6_ENC : POOL32C_LOAD_WORD_EVA_FM_MMR6<0b0001, 0b000>;
+class LLXE_MMR6_ENC : POOL32C_LOAD_WORD_EVA_FM_MMR6<0b0110, 0b010>;
+class SCX_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1001, 0b000>;
+class SCXE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b1010, 0b000>;
 
 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
                                   RegisterOperand GPROpnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
   dag OutOperandList = (outs);
   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
   list<Register> Defs = [AT];

 class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
 
 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
     : Store<opstr, RO>, MMR6Arch<opstr> {
   let DecoderMethod = "DecodeMemMMImm16";
 }
 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
 
-class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
+class STORE_EVA_MMR6_DESC_BASE<string opstr, RegisterOperand RO,
+                               Operand ImmOpnd>
+    : MMR6Arch<opstr>, MipsR6Inst {
   dag OutOperandList = (outs);
-  dag InOperandList = (ins RO:$rt, mem_mm_9:$addr);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
+  dag InOperandList = (ins RO:$rt, ImmOpnd:$addr);
+  string AsmString = !strconcat(opstr, "\t$rt, $addr");
   string DecoderMethod = "DecodeStoreEvaOpMM";
   bit mayStore = 1;
 }
-class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>;
-class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>;
+class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd, mem_simm9gpr>;
+class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd, mem_simm9gpr>;
+class SCX_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"scx", GPR32Opnd, mem_simm9gpr>;
+class SCXE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"scxe", GPR32Opnd,
+                                                mem_simm9gpr>;
 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
-class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>;
-class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> :
-            MMR6Arch<instr_asm>, MipsR6Inst {
+class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd, mem_simm9gpr>;
+class LOAD_WORD_EVA_MMR6_DESC_BASE<string opstr, RegisterOperand RO,
+                                   Operand ImmOpnd>
+    : MMR6Arch<opstr>, MipsR6Inst {
   dag OutOperandList = (outs RO:$rt);
-  dag InOperandList = (ins mem_mm_12:$addr);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
+  dag InOperandList = (ins ImmOpnd:$addr);
+  string AsmString = !strconcat(opstr, "\t$rt, $addr");
   string DecoderMethod = "DecodeMemMMImm9";
   bit mayLoad = 1;
 }
-class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
-class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
+class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd,
+                                                   mem_simm9gpr>;
+class LLX_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"llx", GPR32Opnd,
+                                                   mem_simm9gpr>;
+class LLXE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"llxe", GPR32Opnd,
+                                                    mem_simm9gpr>;
+class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd,
+                                                   mem_simm9gpr>;
 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
       MMR6Arch<"addu16">;
 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
       MMR6Arch<"and16">;
 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
       MMR6Arch<"andi16">;
 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
                    ISA_MICROMIPS32R6;
 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
+def SCX_MMR6 : R6MMR6Rel, SCX_MMR6_DESC, SCX_MMR6_ENC, ISA_MICROMIPS32R6;
+def SCXE_MMR6 : R6MMR6Rel, SCXE_MMR6_DESC, SCXE_MMR6_ENC, ISA_MICROMIPS32R6;
 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
 def SHE_MMR6 : StdMMR6Rel, SHE_MMR6_DESC, SHE_MMR6_ENC, ISA_MICROMIPS32R6;
 def LLE_MMR6 : StdMMR6Rel, LLE_MMR6_DESC, LLE_MMR6_ENC, ISA_MICROMIPS32R6;
+def LLX_MMR6 : R6MMR6Rel, LLX_MMR6_DESC, LLX_MMR6_ENC, ISA_MICROMIPS32R6;
+def LLXE_MMR6 : R6MMR6Rel, LLXE_MMR6_DESC, LLXE_MMR6_ENC, ISA_MICROMIPS32R6;
 def LWE_MMR6 : StdMMR6Rel, LWE_MMR6_DESC, LWE_MMR6_ENC, ISA_MICROMIPS32R6;
 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
                   ISA_MICROMIPS32R6;
 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,

lib/Target/Mips/MicroMipsInstrInfo.td

 class LLBaseMM<string opstr, RegisterOperand RO> :
   InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMemMMImm12";
   let mayLoad = 1;
 }
 
 class LLEBaseMM<string opstr, RegisterOperand RO> :
-  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
+  InstSE<(outs RO:$rt), (ins mem_simm9gpr:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMemMMImm9";
   let mayLoad = 1;
 }
 
 class SCBaseMM<string opstr, RegisterOperand RO> :
   InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMemMMImm12";
   let mayStore = 1;
   let Constraints = "$rt = $dst";
 }
 
 class SCEBaseMM<string opstr, RegisterOperand RO> :
-  InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
+  InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9gpr:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMemMMImm9";
   let mayStore = 1;
   let Constraints = "$rt = $dst";
 }
 
 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
              InstrItinClass Itin = NoItinerary> :
let DecoderMethod = "DecodeMemMMImm16" in {
     def SW_MM  : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
   }
 
   let DecoderMethod = "DecodeMemMMImm9" in {
     def LBE_MM  : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
     def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
     def LHE_MM  : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
     def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
-    def LWE_MM  : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
-    def SBE_MM  : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
-    def SHE_MM  : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
+    def LWE_MM  : LoadMemory<"lwe", GPR32Opnd, mem_simm9gpr>,
+                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
+    def SBE_MM  : StoreMemory<"sbe", GPR32Opnd, mem_simm9gpr>,
+                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
+    def SHE_MM  : StoreMemory<"she", GPR32Opnd, mem_simm9gpr>,
+                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
     def SWE_MM  : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
                   POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
   }
 
   def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
 
   def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
 

lib/Target/Mips/MipsEVAInstrInfo.td

 
 //===----------------------------------------------------------------------===//
 //
 // Instruction descriptions
 //
 //===----------------------------------------------------------------------===//
 
 // Memory Load/Store EVA descriptions
-class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+                         Operand ImmOpnd> {
   dag OutOperandList = (outs GPROpnd:$rt);
-  dag InOperandList = (ins mem_simm9:$addr);
+  dag InOperandList = (ins ImmOpnd:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   string DecoderMethod = "DecodeMemEVA";
   bit canFoldAsLoad = 1;
   bit mayLoad = 1;
 }
 
-class LBE_DESC  : LOAD_EVA_DESC_BASE<"lbe",  GPR32Opnd>;
-class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd>;
-class LHE_DESC  : LOAD_EVA_DESC_BASE<"lhe",  GPR32Opnd>;
-class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd>;
-class LWE_DESC  : LOAD_EVA_DESC_BASE<"lwe",  GPR32Opnd>;
+class LBE_DESC  : LOAD_EVA_DESC_BASE<"lbe",  GPR32Opnd, mem_simm9>;
+class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd, mem_simm9>;
+class LHE_DESC  : LOAD_EVA_DESC_BASE<"lhe",  GPR32Opnd, mem_simm9>;
+class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, mem_simm9>;
+class LWE_DESC  : LOAD_EVA_DESC_BASE<"lwe",  GPR32Opnd, mem_simm9gpr>;
 
 class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+                          Operand ImmOpnd,
                           SDPatternOperator OpNode = null_frag> {
   dag OutOperandList = (outs);
-  dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
+  dag InOperandList = (ins GPROpnd:$rt, ImmOpnd:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   string DecoderMethod = "DecodeMemEVA";
   bit mayStore = 1;
 }
 
-class SBE_DESC  : STORE_EVA_DESC_BASE<"sbe",  GPR32Opnd>;
-class SHE_DESC  : STORE_EVA_DESC_BASE<"she",  GPR32Opnd>;
-class SWE_DESC  : STORE_EVA_DESC_BASE<"swe",  GPR32Opnd>;
+class SBE_DESC  : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, mem_simm9gpr>;
+class SHE_DESC  : STORE_EVA_DESC_BASE<"she", GPR32Opnd, mem_simm9gpr>;
+class SWE_DESC  : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, mem_simm9>;
 
 // Load/Store Left/Right EVA descriptions
 class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$rt);
   dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   string DecoderMethod = "DecodeMemEVA";

 }
 
 class SWLE_DESC  : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swle",  GPR32Opnd>;
 class SWRE_DESC  : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swre",  GPR32Opnd>;
 
 // Load-linked EVA, Store-conditional EVA descriptions
 class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$rt);
-  dag InOperandList = (ins mem_simm9:$addr);
+  dag InOperandList = (ins mem_simm9gpr:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   bit mayLoad = 1;
   string DecoderMethod = "DecodeMemEVA";
 }
 
 class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd>;
 
 class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$dst);
-  dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
+  dag InOperandList = (ins GPROpnd:$rt, mem_simm9gpr:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   bit mayStore = 1;
   string Constraints = "$rt = $dst";
   string DecoderMethod = "DecodeMemEVA";
 }
 
 class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd>;

lib/Target/Mips/MipsInstrInfo.td

 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
   InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
          [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
   let hasSideEffects = 0;
   let isReMaterializable = 1;
 }
 
 // Memory Load/Store
-class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
-           InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
-  InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
+class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
+                 SDPatternOperator OpNode = null_frag,
+                 InstrItinClass Itin = NoItinerary,
+                 ComplexPattern Addr = addr> :
+  InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
          [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
   let DecoderMethod = "DecodeMem";
   let canFoldAsLoad = 1;
   let mayLoad = 1;
 }
 
+class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
+           InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
+  LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
+
 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
             SDPatternOperator OpNode = null_frag,
             InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
   InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
          [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
   let DecoderMethod = "DecodeMem";
   let mayStore = 1;
 }

test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x60 0x85 0x10 0x06 # CHECK: llx $4, 6($5)
+0x60 0x85 0x64 0x06 # CHECK: llxe $4, 6($5)
+0x60 0x85 0x90 0x06 # CHECK: scx $4, 6($5)
+0x60 0x85 0xa0 0x06 # CHECK: scxe $4, 6($5)

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x60 0x85 0x10 0x06 # CHECK: llx $4, 6($5)
+0x60 0x85 0x64 0x06 # CHECK: llxe $4, 6($5)
+0x60 0x85 0x90 0x06 # CHECK: scx $4, 6($5)
+0x60 0x85 0xa0 0x06 # CHECK: scxe $4, 6($5)

test/MC/Mips/eva/invalid.s

 # Instructions that are invalid
 #
 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32r2 \
 # RUN:     -mattr==eva 2>%t1
 # RUN: FileCheck %s < %t1
 
     .set noat
     cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
     cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
     prefe -1, 255($7)  # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
     prefe 32, 255($7)  # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+    lle $4, 512($5)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+    lwe $4, 512($5)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+    sbe $4, 512($5)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+    sce $4, 512($5)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+    she $4, 512($5)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/eva/invalid_R6.s

# RUN: FileCheck %s < %t1
         lwre      $zero,-256($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         lwre      $zero,-176($gp)    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swle      $9,255($s1)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swle      $10,-256($s3)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swle      $8,131($s5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swre      $s4,255($13)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swre      $s4,-256($13)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         swre      $s2,86($14)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lle       $4, 512($5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        lwe       $4, 512($5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sbe       $4, 512($5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sce       $4, 512($5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        she       $4, 512($5)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips/invalid.s

# RUN: FileCheck %s < %t1
   sdbbp16 -1          # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
   sdbbp16 16          # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
   sll $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   sll $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   sra $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   sra $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   srl $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   srl $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  lle $4, 512($5)     # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  lwe $4, 512($5)     # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  sbe $4, 512($5)     # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  sce $4, 512($5)     # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  she $4, 512($5)     # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   swm16 $5, $6, $ra, 8($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
   swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
   swm16 $16-$25, $ra, 8($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
   swm16 $16, 8($sp)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, 8($sp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  lle $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  llx $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  llxe $4, 512($5)             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  lwe $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sbe $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sce $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  scx $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  scxe $4, 512($5)             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  she $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   sel.d $f0, $f2, $f4      # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
   seleqz.s $f1, $f2, $f3   # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
   seleqz.d $f2, $f4, $f8   # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
   selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
   selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
   class.s $f2, $f3         # CHECK: class.s $f2, $f3       # encoding: [0x54,0x62,0x00,0x60]
   class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x54,0x82,0x02,0x60]
   deret                    # CHECK: deret                  # encoding: [0x00,0x00,0xe3,0x7c]
+  llx $4, 6($5)            # CHECK: llx $4, 6($5)          # encoding: [0x60,0x85,0x10,0x06]
+  llxe $4, 6($5)           # CHECK: llxe $4, 6($5)         # encoding: [0x60,0x85,0x64,0x06]
+  scx $4, 6($5)            # CHECK: scx $4, 6($5)          # encoding: [0x60,0x85,0x90,0x06]
+  scxe $4, 6($5)           # CHECK: scxe $4, 6($5)         # encoding: [0x60,0x85,0xa0,0x06]

test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   swm16 $5, $6, $ra, 8($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
   swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
   swm16 $16-$25, $ra, 8($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
   swm16 $16, 8($sp)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, 8($sp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  lle $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  llx $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  llxe $4, 512($5)             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  lwe $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sbe $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sce $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  scx $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  scxe $4, 512($5)             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  she $4, 512($5)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips64r6/valid.s

a:
         selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3  # encoding: [0x54,0x62,0x08,0x78]
         selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8  # encoding: [0x55,0x04,0x12,0x78]
         class.s $f2, $f3         # CHECK: class.s $f2, $f3        # encoding: [0x54,0x62,0x00,0x60]
         class.d $f2, $f4         # CHECK: class.d $f2, $f4        # encoding: [0x54,0x82,0x02,0x60]
         deret                    # CHECK: deret                   # encoding: [0x00,0x00,0xe3,0x7c]
         di                       # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
         di $0                    # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
         di $15                   # CHECK: di $15                  # encoding: [0x00,0x0f,0x47,0x7c]
+        llx $4, 6($5)            # CHECK: llx $4, 6($5)           # encoding: [0x60,0x85,0x10,0x06]
+        llxe $4, 6($5)           # CHECK: llxe $4, 6($5)          # encoding: [0x60,0x85,0x64,0x06]
+        scx $4, 6($5)            # CHECK: scx $4, 6($5)           # encoding: [0x60,0x85,0x90,0x06]
+        scxe $4, 6($5)           # CHECK: scxe $4, 6($5)          # encoding: [0x60,0x85,0xa0,0x06]
 
 1: