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Differential D16863

AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors
ClosedPublic

Authored by • tstellarAMD on Feb 3 2016, 12:21 PM.

Details

Reviewers
arsenm
Commits
rG5dde1d2eb35a: AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors
rL259897: AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors

Diff Detail

Repository
rL LLVM

Event Timeline

• tstellarAMD updated this revision to Diff 46815.Feb 3 2016, 12:21 PM
• tstellarAMD retitled this revision from to AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors.
• tstellarAMD updated this object.
• tstellarAMD added a reviewer: arsenm.
• tstellarAMD added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptFeb 3 2016, 12:21 PM
arsenm accepted this revision.Feb 3 2016, 12:27 PM
arsenm edited edge metadata.

LGTM. How was this working at all before?

This revision is now accepted and ready to land.Feb 3 2016, 12:27 PM
• tstellarAMD updated this revision to Diff 46962.Feb 4 2016, 2:08 PM
• tstellarAMD edited edge metadata.

Fix header files too.

arsenm added a comment.Feb 4 2016, 2:18 PM

LGTM

• tstellarAMD added a comment.Feb 5 2016, 10:10 AM
In D16863#343382, @arsenm wrote:

LGTM. How was this working at all before?

We were passing the correct values, it's just that the parameter names were wrong.

Closed by commit rL259897: AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors (authored by tstellar). · Explain WhyFeb 5 2016, 10:33 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
12 lines
8 lines

Diff 47028

llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.h

Show All 31 Lines
private: private:
protected: protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF; std::unique_ptr<TargetLoweringObjectFile> TLOF;
AMDGPUSubtarget Subtarget; AMDGPUSubtarget Subtarget;
AMDGPUIntrinsicInfo IntrinsicInfo; AMDGPUIntrinsicInfo IntrinsicInfo;
public: public:
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef FS, AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef FS, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
~AMDGPUTargetMachine(); ~AMDGPUTargetMachine();
const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; } const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; }
const AMDGPUSubtarget *getSubtargetImpl(const Function &) const override { const AMDGPUSubtarget *getSubtargetImpl(const Function &) const override {
return &Subtarget; return &Subtarget;
} }
const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override { const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
return &IntrinsicInfo; return &IntrinsicInfo;
} }
TargetIRAnalysis getTargetIRAnalysis() override; TargetIRAnalysis getTargetIRAnalysis() override;
TargetLoweringObjectFile *getObjFileLowering() const override { TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get(); return TLOF.get();
} }
}; };
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// R600 Target Machine (R600 -> Cayman) // R600 Target Machine (R600 -> Cayman)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class R600TargetMachine : public AMDGPUTargetMachine { class R600TargetMachine : public AMDGPUTargetMachine {
public: public:
R600TargetMachine(const Target &T, const Triple &TT, StringRef FS, R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef FS, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
}; };
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GCN Target Machine (SI+) // GCN Target Machine (SI+)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class GCNTargetMachine : public AMDGPUTargetMachine { class GCNTargetMachine : public AMDGPUTargetMachine {
public: public:
GCNTargetMachine(const Target &T, const Triple &TT, StringRef FS, GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
StringRef CPU, TargetOptions Options, Reloc::Model RM, StringRef FS, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL); CodeModel::Model CM, CodeGenOpt::Level OL);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
}; };
} // End namespace llvm } // End namespace llvm
#endif #endif

llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

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AMDGPUTargetMachine::~AMDGPUTargetMachine() { } AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// R600 Target Machine (R600 -> Cayman) // R600 Target Machine (R600 -> Cayman)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT, R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
StringRef FS, StringRef CPU, StringRef CPU, StringRef FS,
TargetOptions Options, Reloc::Model RM, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL) CodeModel::Model CM, CodeGenOpt::Level OL)
: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {} : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// GCN Target Machine (SI+) // GCN Target Machine (SI+)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT, GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
StringRef FS, StringRef CPU, StringRef CPU, StringRef FS,
TargetOptions Options, Reloc::Model RM, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OL) CodeModel::Model CM, CodeGenOpt::Level OL)
: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {} : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// AMDGPU Pass Setup // AMDGPU Pass Setup
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
namespace { namespace {
class AMDGPUPassConfig : public TargetPassConfig { class AMDGPUPassConfig : public TargetPassConfig {
public: public:
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