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AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors
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Authored by • tstellarAMD on Feb 3 2016, 12:21 PM.

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rG5dde1d2eb35a: AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors
rL259897: AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors

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• tstellarAMD updated this revision to Diff 46815.Feb 3 2016, 12:21 PM

• tstellarAMD retitled this revision from to AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors.

• tstellarAMD updated this object.

• tstellarAMD added a reviewer: arsenm.

• tstellarAMD added a subscriber: llvm-commits.

Herald added a subscriber: arsenm. · View Herald TranscriptFeb 3 2016, 12:21 PM

LGTM. How was this working at all before?

This revision is now accepted and ready to land.Feb 3 2016, 12:27 PM

Fix header files too.

LGTM

In D16863#343382, @arsenm wrote:

LGTM. How was this working at all before?

We were passing the correct values, it's just that the parameter names were wrong.

Closed by commit rL259897: AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors (authored by tstellar). · Explain WhyFeb 5 2016, 10:33 AM

This revision was automatically updated to reflect the committed changes.

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lib/

Target/

AMDGPU/

AMDGPUTargetMachine.cpp

8 lines

Diff 46815

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

	Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Lines

	AMDGPUTargetMachine::~AMDGPUTargetMachine() { }			AMDGPUTargetMachine::~AMDGPUTargetMachine() { }

	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	// R600 Target Machine (R600 -> Cayman)			// R600 Target Machine (R600 -> Cayman)
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,			R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
	StringRef FS, StringRef CPU,			StringRef CPU, StringRef FS,
	TargetOptions Options, Reloc::Model RM,			TargetOptions Options, Reloc::Model RM,
	CodeModel::Model CM, CodeGenOpt::Level OL)			CodeModel::Model CM, CodeGenOpt::Level OL)
	: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}			: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}

	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	// GCN Target Machine (SI+)			// GCN Target Machine (SI+)
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,			GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
	StringRef FS, StringRef CPU,			StringRef CPU, StringRef FS,
	TargetOptions Options, Reloc::Model RM,			TargetOptions Options, Reloc::Model RM,
	CodeModel::Model CM, CodeGenOpt::Level OL)			CodeModel::Model CM, CodeGenOpt::Level OL)
	: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}			: AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}

	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	// AMDGPU Pass Setup			// AMDGPU Pass Setup
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	namespace {			namespace {
	class AMDGPUPassConfig : public TargetPassConfig {			class AMDGPUPassConfig : public TargetPassConfig {
	public:			public:
	▲ Show 20 Lines • Show All 221 Lines • Show Last 20 Lines