[mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* instructions

[zbuljan]

Summary

The patch adds CodeGen support for microMIPS32r6 ADD, ADDIU*, ADDU* and microMIPS64r6 DADD* instructions:

• updated add.ll with tests for microMIPSr6 ADD, ADDIU*, ADDU* and DADD* instruction selection
• separated microMIPS64r6 DADD* instructions from equivalent MIPS64 instructions using NotInMicroMips predicate
• added DAG pattern to ADDIU description class for proper selection of the instruction
• implemented DADD, DADDIU and DADDU instructions for microMIPS64r6 and added tests for the standard encodings

[dsanders]

lib/Target/Mips/MicroMips64r6InstrInfo.td

185–195 ↗

(On Diff #45661)

Indentation on the $imm operands.

lib/Target/Mips/Mips64InstrInfo.td

542–545 ↗

(On Diff #45661)

These used to be disabled for any DSP, not just microMIPS DSP. Is there a reason for the change?

[zbuljan]

lib/Target/Mips/Mips64InstrInfo.td

542–545 ↗

(On Diff #45661)

I wanted do disable these for microMIPS also so I introduced new ISA_NOT_MICROMIPS_DSP class with list of predicates: NotInMicroMips and NotDSP.
Maybe it would be better to name class as ISA_NOT_MICROMIPS_NOT_DSP?

[dsanders]

lib/Target/Mips/Mips64InstrInfo.td

542–545 ↗

(On Diff #45661)

Ah ok, it's just the name that's a bit misleading.

I think the change you want is

let AdditionalPredicates = [NotInMicroMips,NotDSP] in {

This is because predicates belong to a specific group of predicates (e.g. EncodingPredicates, InsnPredicates, etc.) and both of these belong to AdditionalPredicates at the moment. That said, it would be easy to change NotDSP into an InsnPredicate since there's only three uses of it, then you could have

let AdditionalPredicates = [NotInMicroMips] in {
  def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
              (DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP;

which is more consistent with other code.

At some point we need to move NotInMicroMips into the EncodingPredicates group.

[zbuljan]

Rebased to work with top of the tree.
Added ASE_NOT_DSP class.

[dsanders]

LGTM

[sdardis]

Post commit comments:

I noticed that MipsSEDAGToDAGISel::selectNode(SDNode *Node) performs the expansion of ISD::ADDE. Unfortunately the logic there was not extended to cover microMIPS:

case ISD::ADDE: {
  if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
    break;
  SDValue InFlag = Node->getOperand(2);
  unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu; // Here
  Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
  return std::make_pair(true, Result);
}

microMIPSR6 re-encodes 'addu', so I believe direct object emission may be broken.

[sdardis]

My previous comment was made a bit too quickly. We have tables that map MIPS(R6) instructions to microMIPS(R6) instructions.

llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td

 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>;
-class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd>;
+class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>;
 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd>;
 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd>;
 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd>;
 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd>;
 
 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrFormats.td

class POOL32S_DMFTC0_FM_MMR6<string instr_asm, bits<5> funct>
   let Inst{31-26} = 0b010110;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-14} = 0;
   let Inst{13-11} = sel;
   let Inst{10-6}  = funct;
   let Inst{5-0}   = 0b111100;
 }
+
+class POOL32S_ARITH_FM_MMR6<string opstr, bits<9> funct>
+    : MMR6Arch<opstr> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<5> rd;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10-9}  = 0b00;
+  let Inst{8-0}   = funct;
+}
+
+class DADDIU_FM_MMR6<string opstr> : MMR6Arch<opstr> {
+  bits<5> rt;
+  bits<5> rs;
+  bits<16> imm16;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010111;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-0}  = imm16;
+}

llvm/trunk/lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>;
 class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>;
 class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>;
 class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
 class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>;
 class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>;
 class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
 class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
+class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
+class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
+class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
                                               II_DMTC1, bitconvert>;
 class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>;
 
 class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>;
 class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
                                               II_DMFC1, bitconvert>;
 class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>;
 
+class DADD_MM64R6_DESC : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>;
+class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
+                                       II_DADDIU, immSExt16, add>,
+                           IsAsCheapAsAMove;
+class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
   def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
let DecoderNamespace = "MicroMipsR6" in {
   def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC,
                      ISA_MICROMIPS64R6;
   def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC,
                      ISA_MICROMIPS64R6;
   def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_DESC, DMFC1_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
   def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC,
                      ISA_MICROMIPS64R6;
+  def DADD_MM64R6: StdMMR6Rel, DADD_MM64R6_DESC, DADD_MM64R6_ENC,
+                   ISA_MICROMIPS64R6;
+  def DADDIU_MM64R6: StdMMR6Rel, DADDIU_MM64R6_DESC, DADDIU_MM64R6_ENC,
+                     ISA_MICROMIPS64R6;
+  def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
 }
 
 //===----------------------------------------------------------------------===//
+//
+// Arbitrary patterns that map to one or more instructions
+//
+//===----------------------------------------------------------------------===//
+
+def : MipsPat<(MipsLo tglobaladdr:$in),
+              (DADDIU_MM64R6 ZERO_64, tglobaladdr:$in)>, ISA_MICROMIPS64R6;
+def : MipsPat<(MipsLo tblockaddress:$in),
+              (DADDIU_MM64R6 ZERO_64, tblockaddress:$in)>, ISA_MICROMIPS64R6;
+def : MipsPat<(MipsLo tjumptable:$in),
+              (DADDIU_MM64R6 ZERO_64, tjumptable:$in)>, ISA_MICROMIPS64R6;
+def : MipsPat<(MipsLo tconstpool:$in),
+              (DADDIU_MM64R6 ZERO_64, tconstpool:$in)>, ISA_MICROMIPS64R6;
+def : MipsPat<(MipsLo tglobaltlsaddr:$in),
+              (DADDIU_MM64R6 ZERO_64, tglobaltlsaddr:$in)>, ISA_MICROMIPS64R6;
+def : MipsPat<(MipsLo texternalsym:$in),
+              (DADDIU_MM64R6 ZERO_64, texternalsym:$in)>, ISA_MICROMIPS64R6;
+
+def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
+              (DADDIU_MM64R6 GPR64:$hi, tglobaladdr:$lo)>, ISA_MICROMIPS64R6;
+def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
+              (DADDIU_MM64R6 GPR64:$hi, tblockaddress:$lo)>, ISA_MICROMIPS64R6;
+def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
+              (DADDIU_MM64R6 GPR64:$hi, tjumptable:$lo)>, ISA_MICROMIPS64R6;
+def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
+              (DADDIU_MM64R6 GPR64:$hi, tconstpool:$lo)>, ISA_MICROMIPS64R6;
+def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
+              (DADDIU_MM64R6 GPR64:$hi, tglobaltlsaddr:$lo)>, ISA_MICROMIPS64R6;
+
+def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
+              (DADDU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
+def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
+              (DADDIU_MM64R6 GPR64:$lhs, imm:$imm)>, ISA_MICROMIPS64R6;
+
+def : WrapperPat<tglobaladdr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
+def : WrapperPat<tconstpool, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
+def : WrapperPat<texternalsym, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
+def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
+def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
+def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
+
+//===----------------------------------------------------------------------===//
+//
 // Instruction aliases
+//
 //===----------------------------------------------------------------------===//
+
 def : MipsInstAlias<"dmtc0 $rt, $rd",
                     (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
 def : MipsInstAlias<"dmfc0 $rt, $rd",
                     (DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
                     ISA_MICROMIPS64R6;
+def : MipsInstAlias<"daddu $rs, $rt, $imm",
+                    (DADDIU_MM64R6 GPR64Opnd:$rs,
+                                   GPR64Opnd:$rt,
+                                   simm16_64:$imm),
+                    0>, ISA_MICROMIPS64R6;
+def : MipsInstAlias<"daddu $rs, $imm",
+                    (DADDIU_MM64R6 GPR64Opnd:$rs,
+                                   GPR64Opnd:$rs,
+                                   simm16_64:$imm),
+                    0>, ISA_MICROMIPS64R6;
+def : MipsInstAlias<"dsubu $rt, $rs, $imm",
+                    (DADDIU_MM64R6 GPR64Opnd:$rt,
+                                   GPR64Opnd:$rs,
+                                   InvertedImOperand64:$imm),
+                    0>, ISA_MICROMIPS64R6;
+def : MipsInstAlias<"dsubu $rs, $imm",
+                    (DADDIU_MM64R6 GPR64Opnd:$rs,
+                                   GPR64Opnd:$rs,
+                                   InvertedImOperand64:$imm),
+                    0>, ISA_MICROMIPS64R6;

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

 
 //===----------------------------------------------------------------------===//
 // Instruction definition
 //===----------------------------------------------------------------------===//
 let DecoderNamespace = "Mips64" in {
 /// Arithmetic Instructions (ALU Immediate)
 def DADDi   : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
               ISA_MIPS3_NOT_32R6_64R6;
-def DADDiu  : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
-                          immSExt16, add>,
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
+                                       II_DADDIU, immSExt16, add>,
                ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
+}
 
 let isCodeGenOnly = 1 in {
 def SLTi64  : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
               SLTI_FM<0xa>;
 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
               SLTI_FM<0xb>;
 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
              ADDI_FM<0xc>;
 def ORi64   : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
               ADDI_FM<0xd>;
 def XORi64  : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
               ADDI_FM<0xe>;
 def LUi64   : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM;
 }
 
 /// Arithmetic Instructions (3-Operand, R-Type)
-def DADD   : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
-             ISA_MIPS3;
-def DADDu  : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
-             ISA_MIPS3;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DADD   : StdMMR6Rel, ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>,
+               ADD_FM<0, 0x2c>, ISA_MIPS3;
+  def DADDu  : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
+               ADD_FM<0, 0x2d>, ISA_MIPS3;
+}
 def DSUBu  : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
              ISA_MIPS3;
 def DSUB   : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
              ISA_MIPS3;
 
 let isCodeGenOnly = 1 in {
 def SLT64  : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;

 // hi/lo relocs
 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
 
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
-def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
+  def : MipsPat<(MipsLo tblockaddress:$in),
+                (DADDiu ZERO_64, tblockaddress:$in)>;
   def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
   def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
   def : MipsPat<(MipsLo tglobaltlsaddr:$in),
                 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
   def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
 
   def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
                 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
   def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
                 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
   def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
                 (DADDiu GPR64:$hi, tjumptable:$lo)>;
   def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
                 (DADDiu GPR64:$hi, tconstpool:$lo)>;
   def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
                 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
 
   def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
   def : WrapperPat<tconstpool, DADDiu, GPR64>;
   def : WrapperPat<texternalsym, DADDiu, GPR64>;
   def : WrapperPat<tblockaddress, DADDiu, GPR64>;
   def : WrapperPat<tjumptable, DADDiu, GPR64>;
   def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
+}
 
 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
                   ZERO_64>;
 
 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
               (BLEZ64 i64:$lhs, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
               (BGEZ64 i64:$lhs, bb:$dst)>;
def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
               (SLL64_64 GPR64:$src)>;
 
 // bswap MipsPattern
 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
 
 // Carry pattern
 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
               (DSUBu GPR64:$lhs, GPR64:$rhs)>;
-let AdditionalPredicates = [NotDSP] in {
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
-                (DADDu GPR64:$lhs, GPR64:$rhs)>;
+                (DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP;
   def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
-                (DADDiu GPR64:$lhs, imm:$imm)>;
+                (DADDiu GPR64:$lhs, imm:$imm)>, ASE_NOT_DSP;
 }
 
 // Octeon bbit0/bbit1 MipsPattern
 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
               (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
               (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),

 def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>;
 def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>;
 def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>;
 def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>;
 
 //===----------------------------------------------------------------------===//
 // Instruction aliases
 //===----------------------------------------------------------------------===//
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"move $dst, $src",
                       (OR64 GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
         GPR_64;
   def : MipsInstAlias<"move $dst, $src",
                       (DADDu GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
         GPR_64;
-def : MipsInstAlias<"daddu $rs, $rt, $imm",
-                    (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
-                    0>, ISA_MIPS3;
   def : MipsInstAlias<"dadd $rs, $rt, $imm",
                       (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
                       0>, ISA_MIPS3_NOT_32R6_64R6;
-def : MipsInstAlias<"daddu $rs, $imm",
-                    (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
-                    0>, ISA_MIPS3;
   def : MipsInstAlias<"dadd $rs, $imm",
                       (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
                       0>, ISA_MIPS3_NOT_32R6_64R6;
+  def : MipsInstAlias<"daddu $rs, $rt, $imm",
+                      (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
+                      0>, ISA_MIPS3;
+  def : MipsInstAlias<"daddu $rs, $imm",
+                      (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
+                      0>, ISA_MIPS3;
+}
 def : MipsInstAlias<"dsll $rd, $rt, $rs",
                     (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
                     ISA_MIPS3;
 def : MipsInstAlias<"dneg $rt, $rs",
                     (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
                     ISA_MIPS3;
 def : MipsInstAlias<"dneg $rt",
                     (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
                     ISA_MIPS3;
 def : MipsInstAlias<"dnegu $rt, $rs",
                     (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
                     ISA_MIPS3;
-def : MipsInstAlias<"dsubu $rt, $rs, $imm",
-                    (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
-                            InvertedImOperand64:$imm), 0>, ISA_MIPS3;
 def : MipsInstAlias<"dsubi $rs, $rt, $imm",
                     (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
                            InvertedImOperand64:$imm),
                     0>, ISA_MIPS3_NOT_32R6_64R6;
 def : MipsInstAlias<"dsubi $rs, $imm",
                     (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
                            InvertedImOperand64:$imm),
                     0>, ISA_MIPS3_NOT_32R6_64R6;
 def : MipsInstAlias<"dsub $rs, $rt, $imm",
                     (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
                            InvertedImOperand64:$imm),
                     0>, ISA_MIPS3_NOT_32R6_64R6;
 def : MipsInstAlias<"dsub $rs, $imm",
                     (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
                            InvertedImOperand64:$imm),
                     0>, ISA_MIPS3_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def : MipsInstAlias<"dsubu $rt, $rs, $imm",
+                      (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
+                              InvertedImOperand64:$imm), 0>, ISA_MIPS3;
   def : MipsInstAlias<"dsubu $rs, $imm",
                       (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
-                            InvertedImOperand64:$imm),
-                    0>, ISA_MIPS3;
+                              InvertedImOperand64:$imm), 0>, ISA_MIPS3;
+}
 def : MipsInstAlias<"dsra $rd, $rt, $rs",
                     (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
                     ISA_MIPS3;
 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
                     (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
                     ISA_MIPS3;
 
 // Two operand (implicit 0 selector) versions:

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 }
 
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
 // It can be used only on instructions that doesn't inherit PredicateControl.
 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
   let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
 }
 
+class ASE_NOT_DSP {
+  list<Predicate> InsnPredicates = [NotDSP];
+}
+
 //===----------------------------------------------------------------------===//
 
 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
   let EncodingPredicates = [HasStdEnc];
 }
 
 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
   InstAlias<Asm, Result, Emit>, PredicateControl;

 
 // Arbitrary immediates
 def : MipsPat<(i32 imm:$imm),
           (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
 
 // Carry MipsPatterns
 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
               (SUBu GPR32:$lhs, GPR32:$rhs)>;
-let AdditionalPredicates = [NotDSP] in {
-  def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
-                (ADDu GPR32:$lhs, GPR32:$rhs)>;
-  def : MipsPat<(addc  GPR32:$src, immSExt16:$imm),
-                (ADDiu GPR32:$src, imm:$imm)>;
-}
+              (ADDu GPR32:$lhs, GPR32:$rhs)>, ASE_NOT_DSP;
+              (ADDiu GPR32:$src, imm:$imm)>, ASE_NOT_DSP;
 
 // Support multiplication for pre-Mips32 targets that don't have
 // the MUL instruction.
 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
               (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
       ISA_MIPS1_NOT_32R6_64R6;
 
 // SYNC

llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll

 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -O2 | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM64
 
 define signext i1 @add_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: add_i1:
 
-  ; ALL:        addu    $[[T0:[0-9]+]], $4, $5
-  ; ALL:        sll     $[[T0]], $[[T0]], 31
-  ; ALL:        sra     $2, $[[T0]], 31
+  ; NOT-R2-R6:  addu    $[[T0:[0-9]+]], $4, $5
+  ; NOT-R2-R6:  sll     $[[T0]], $[[T0]], 31
+  ; NOT-R2-R6:  sra     $2, $[[T0]], 31
+
+  ; R2-R6:      addu    $[[T0:[0-9]+]], $4, $5
+  ; R2-R6:      sll     $[[T0]], $[[T0]], 31
+  ; R2-R6:      sra     $2, $[[T0]], 31
+
+  ; MMR6:       addu16  $[[T0:[0-9]+]], $4, $5
+  ; MMR6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; MMR6:       sra     $2, $[[T1]], 31
 
   %r = add i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @add_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: add_i8:
 
   ; NOT-R2-R6:  addu    $[[T0:[0-9]+]], $4, $5
   ; NOT-R2-R6:  sll     $[[T0]], $[[T0]], 24
   ; NOT-R2-R6:  sra     $2, $[[T0]], 24
 
-  ; R2-R6:         addu    $[[T0:[0-9]+]], $4, $5
-  ; R2-R6:         seb     $2, $[[T0:[0-9]+]]
+  ; R2-R6:      addu    $[[T0:[0-9]+]], $4, $5
+  ; R2-R6:      seb     $2, $[[T0:[0-9]+]]
 
+  ; MMR6:       addu16  $[[T0:[0-9]+]], $4, $5
+  ; MMR6:       seb     $2, $[[T0]]
+
   %r = add i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @add_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: add_i16:
 
   ; NOT-R2-R6:  addu    $[[T0:[0-9]+]], $4, $5
   ; NOT-R2-R6:  sll     $[[T0]], $[[T0]], 16
   ; NOT-R2-R6:  sra     $2, $[[T0]], 16
 
-  ; R2-R6:         addu    $[[T0:[0-9]+]], $4, $5
-  ; R2-R6:         seh     $2, $[[T0:[0-9]+]]
+  ; R2-R6:      addu    $[[T0:[0-9]+]], $4, $5
+  ; R2-R6:      seh     $2, $[[T0]]
+
+  ; MMR6:       addu16  $[[T0:[0-9]+]], $4, $5
+  ; MMR6:       seh     $2, $[[T0]]
 
   %r = add i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @add_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: add_i32:
 
-  ; ALL:        addu    $2, $4, $5
+  ; NOT-R2-R6:  addu    $2, $4, $5
+  ; R2-R6:      addu    $2, $4, $5
+
+  ; MMR6:       addu16  $[[T0:[0-9]+]], $4, $5
 
   %r = add i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @add_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: add_i64:
 
   ; GP32:       addu    $3, $5, $7
   ; GP32:       sltu    $[[T0:[0-9]+]], $3, $7
   ; GP32:       addu    $[[T1:[0-9]+]], $[[T0]], $6
   ; GP32:       addu    $2, $4, $[[T1]]
 
   ; GP64:       daddu   $2, $4, $5
 
+  ; MM32:       addu    $3, $5, $7
+  ; MM32:       sltu    $[[T0:[0-9]+]], $3, $7
+  ; MM32:       addu    $[[T1:[0-9]+]], $[[T0]], $6
+  ; MM32:       addu    $2, $4, $[[T1]]
+
+  ; MM64:       daddu   $2, $4, $5
+
   %r = add i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @add_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: add_i128:
 
; ALL-LABEL: add_i128:
   ; GP32:       move      $4, $[[T5]]
   ; GP32:       move      $5, $[[T1]]
 
   ; GP64:       daddu     $3, $5, $7
   ; GP64:       sltu      $[[T0:[0-9]+]], $3, $7
   ; GP64:       daddu     $[[T1:[0-9]+]], $[[T0]], $6
   ; GP64:       daddu     $2, $4, $[[T1]]
 
+  ; MM32:       lw        $[[T0:[0-9]+]], 28($sp)
+  ; MM32:       addu      $[[T1:[0-9]+]], $7, $[[T0]]
+  ; MM32:       sltu      $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+  ; MM32:       lw        $[[T3:[0-9]+]], 24($sp)
+  ; MM32:       addu      $[[T4:[0-9]+]], $[[T2]], $[[T3]]
+  ; MM32:       addu      $[[T5:[0-9]+]], $6, $[[T4]]
+  ; MM32:       sltu      $[[T6:[0-9]+]], $[[T5]], $[[T3]]
+  ; MM32:       lw        $[[T7:[0-9]+]], 20($sp)
+  ; MM32:       addu      $[[T8:[0-9]+]], $[[T6]], $[[T7]]
+  ; MM32:       addu      $[[T9:[0-9]+]], $5, $[[T8]]
+  ; MM32:       sltu      $[[T10:[0-9]+]], $[[T9]], $[[T7]]
+  ; MM32:       lw        $[[T11:[0-9]+]], 16($sp)
+  ; MM32:       addu      $[[T12:[0-9]+]], $[[T10]], $[[T11]]
+  ; MM32:       addu      $[[T13:[0-9]+]], $4, $[[T12]]
+  ; MM32:       move      $4, $[[T5]]
+  ; MM32:       move      $5, $[[T1]]
+
+  ; MM64:       daddu     $3, $5, $7
+  ; MM64:       sltu      $[[T0:[0-9]+]], $3, $7
+  ; MM64:       daddu     $[[T1:[0-9]+]], $[[T0]], $6
+  ; MM64:       daddu     $2, $4, $[[T1]]
+
   %r = add i128 %a, %b
   ret i128 %r
 }
+
+define signext i1 @add_i1_4(i1 signext %a) {
+; ALL-LABEL: add_i1_4:
+
+  ; ALL:        move      $2, $4
+
+  %r = add i1 4, %a
+  ret i1 %r
+}
+
+define signext i8 @add_i8_4(i8 signext %a) {
+; ALL-LABEL: add_i8_4:
+
+  ; NOT-R2-R6:  sll     $[[T0:[0-9]+]], $4, 24
+  ; NOT-R2-R6:  lui     $[[T1:[0-9]+]], 1024
+  ; NOT-R2-R6:  addu    $[[T0]], $[[T0]], $[[T1]]
+  ; NOT-R2-R6:  sra     $2, $[[T0]], 24
+
+  ; R2-R6:      addiu   $[[T0:[0-9]+]], $4, 4
+  ; R2-R6:      seb     $2, $[[T0]]
+
+  ; MM32:       addiur2 $[[T0:[0-9]+]], $4, 4
+  ; MM32:       seb     $2, $[[T0]]
+
+  ; MM64:       addiur2 $[[T0:[0-9]+]], $4, 4
+  ; MM64:       seb     $2, $[[T0]]
+
+  %r = add i8 4, %a
+  ret i8 %r
+}
+
+define signext i16 @add_i16_4(i16 signext %a) {
+; ALL-LABEL: add_i16_4:
+
+  ; NOT-R2-R6:  sll     $[[T0:[0-9]+]], $4, 16
+  ; NOT-R2-R6:  lui     $[[T1:[0-9]+]], 4
+  ; NOT-R2-R6:  addu    $[[T0]], $[[T0]], $[[T1]]
+  ; NOT-R2-R6:  sra     $2, $[[T0]], 16
+
+  ; R2-R6:      addiu   $[[T0:[0-9]+]], $4, 4
+  ; R2-R6:      seh     $2, $[[T0]]
+
+  ; MM32:       addiur2 $[[T0:[0-9]+]], $4, 4
+  ; MM32:       seh     $2, $[[T0]]
+
+  ; MM64:       addiur2 $[[T0:[0-9]+]], $4, 4
+  ; MM64:       seh     $2, $[[T0]]
+
+  %r = add i16 4, %a
+  ret i16 %r
+}
+
+define signext i32 @add_i32_4(i32 signext %a) {
+; ALL-LABEL: add_i32_4:
+
+  ; GP32:       addiu   $2, $4, 4
+
+  ; GP64:       addiu   $2, $4, 4
+
+  ; MM32:       addiur2 $2, $4, 4
+
+  ; MM64:       addiur2 $2, $4, 4
+
+  %r = add i32 4, %a
+  ret i32 %r
+}
+
+define signext i64 @add_i64_4(i64 signext %a) {
+; ALL-LABEL: add_i64_4:
+
+  ; GP32:       addiu   $[[T0:[0-9]+]], $5, 4
+  ; GP32:       addiu   $[[T1:[0-9]+]], $zero, 4
+  ; GP32:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; GP32:       addu    $2, $4, $[[T1]]
+
+  ; GP64:       daddiu  $2, $4, 4
+
+  ; MM32:       addiu   $[[T0:[0-9]+]], $5, 4
+  ; MM32:       li16    $[[T1:[0-9]+]], 4
+  ; MM32:       sltu    $[[T2:[0-9]+]], $[[T0]], $[[T1]]
+  ; MM32:       addu    $2, $4, $[[T2]]
+
+  ; MM64:       daddiu  $2, $4, 4
+
+  %r = add i64 4, %a
+  ret i64 %r
+}
+
+define signext i128 @add_i128_4(i128 signext %a) {
+; ALL-LABEL: add_i128_4:
+
+  ; GP32:       addiu   $[[T0:[0-9]+]], $7, 4
+  ; GP32:       addiu   $[[T1:[0-9]+]], $zero, 4
+  ; GP32:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; GP32:       addu    $[[T2:[0-9]+]], $6, $[[T1]]
+  ; GP32:       sltu    $[[T1]], $[[T2]], $zero
+  ; GP32:       addu    $[[T3:[0-9]+]], $5, $[[T1]]
+  ; GP32:       sltu    $[[T1]], $[[T3]], $zero
+  ; GP32:       addu    $[[T1]], $4, $[[T1]]
+  ; GP32:       move    $4, $[[T2]]
+  ; GP32:       move    $5, $[[T0]]
+
+  ; GP64:       daddiu  $[[T0:[0-9]+]], $5, 4
+  ; GP64:       daddiu  $[[T1:[0-9]+]], $zero, 4
+  ; GP64:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; GP64:       daddu   $2, $4, $[[T1]]
+
+  ; MM32:       addiu   $[[T0:[0-9]+]], $7, 4
+  ; MM32:       li16    $[[T1:[0-9]+]], 4
+  ; MM32:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; MM32:       addu    $[[T2:[0-9]+]], $6, $[[T1]]
+  ; MM32:       lui     $[[T1]], 0
+  ; MM32:       sltu    $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MM32:       addu    $[[T3]], $5, $[[T3]]
+  ; MM32:       sltu    $[[T1]], $[[T3]], $[[T1]]
+  ; MM32:       addu    $[[T1]], $4, $[[T1]]
+  ; MM32:       move    $4, $[[T2]]
+  ; MM32:       move    $5, $[[T0]]
+
+  ; MM64:       daddiu  $[[T0:[0-9]+]], $5, 4
+  ; MM64:       daddiu  $[[T1:[0-9]+]], $zero, 4
+  ; MM64:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; MM64:       daddu   $2, $4, $[[T1]]
+
+  %r = add i128 4, %a
+  ret i128 %r
+}
+
+define signext i1 @add_i1_3(i1 signext %a) {
+; ALL-LABEL: add_i1_3:
+
+  ; ALL:        sll     $[[T0:[0-9]+]], $4, 31
+  ; ALL:        lui     $[[T1:[0-9]+]], 32768
+
+  ; GP32:       addu    $[[T0]], $[[T0]], $[[T1]]
+  ; GP32:       sra     $[[T1]], $[[T0]], 31
+
+  ; GP64:       addu    $[[T0]], $[[T0]], $[[T1]]
+  ; GP64:       sra     $[[T1]], $[[T0]], 31
+
+  ; MMR6:       addu16  $[[T0]], $[[T0]], $[[T1]]
+  ; MMR6:       sra     $[[T0]], $[[T0]], 31
+
+  %r = add i1 3, %a
+  ret i1 %r
+}
+
+define signext i8 @add_i8_3(i8 signext %a) {
+; ALL-LABEL: add_i8_3:
+
+  ; NOT-R2-R6:  sll     $[[T0:[0-9]+]], $4, 24
+  ; NOT-R2-R6:  lui     $[[T1:[0-9]+]], 768
+  ; NOT-R2-R6:  addu    $[[T0]], $[[T0]], $[[T1]]
+  ; NOT-R2-R6:  sra     $2, $[[T0]], 24
+
+  ; R2-R6:      addiu   $[[T0:[0-9]+]], $4, 3
+  ; R2-R6:      seb     $2, $[[T0]]
+
+  ; MMR6:       addius5 $[[T0:[0-9]+]], 3
+  ; MMR6:       seb     $2, $[[T0]]
+
+  %r = add i8 3, %a
+  ret i8 %r
+}
+
+define signext i16 @add_i16_3(i16 signext %a) {
+; ALL-LABEL: add_i16_3:
+
+  ; NOT-R2-R6:  sll     $[[T0:[0-9]+]], $4, 16
+  ; NOT-R2-R6:  lui     $[[T1:[0-9]+]], 3
+  ; NOT-R2-R6:  addu    $[[T0]], $[[T0]], $[[T1]]
+  ; NOT-R2-R6:  sra     $2, $[[T0]], 16
+
+  ; R2-R6:      addiu   $[[T0:[0-9]+]], $4, 3
+  ; R2-R6:      seh     $2, $[[T0]]
+
+  ; MMR6:       addius5 $[[T0:[0-9]+]], 3
+  ; MMR6:       seh     $2, $[[T0]]
+
+  %r = add i16 3, %a
+  ret i16 %r
+}
+
+define signext i32 @add_i32_3(i32 signext %a) {
+; ALL-LABEL: add_i32_3:
+
+  ; NOT-R2-R6:  addiu   $2, $4, 3
+
+  ; R2-R6:      addiu   $2, $4, 3
+
+  ; MMR6:       addius5 $[[T0:[0-9]+]], 3
+  ; MMR6:       move    $2, $[[T0]]
+
+  %r = add i32 3, %a
+  ret i32 %r
+}
+
+define signext i64 @add_i64_3(i64 signext %a) {
+; ALL-LABEL: add_i64_3:
+
+  ; GP32:       addiu   $[[T0:[0-9]+]], $5, 3
+  ; GP32:       addiu   $[[T1:[0-9]+]], $zero, 3
+  ; GP32:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; GP32:       addu    $2, $4, $[[T1]]
+
+  ; GP64:       daddiu  $2, $4, 3
+
+  ; MM32:       addiu   $[[T0:[0-9]+]], $5, 3
+  ; MM32:       li16    $[[T1:[0-9]+]], 3
+  ; MM32:       sltu    $[[T2:[0-9]+]], $[[T0]], $[[T1]]
+  ; MM32:       addu    $2, $4, $[[T2]]
+
+  ; MM64:       daddiu  $2, $4, 3
+
+  %r = add i64 3, %a
+  ret i64 %r
+}
+
+define signext i128 @add_i128_3(i128 signext %a) {
+; ALL-LABEL: add_i128_3:
+
+  ; GP32:       addiu   $[[T0:[0-9]+]], $7, 3
+  ; GP32:       addiu   $[[T1:[0-9]+]], $zero, 3
+  ; GP32:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; GP32:       addu    $[[T2:[0-9]+]], $6, $[[T1]]
+  ; GP32:       sltu    $[[T3:[0-9]+]], $[[T2]], $zero
+  ; GP32:       addu    $[[T4:[0-9]+]], $5, $[[T3]]
+  ; GP32:       sltu    $[[T5:[0-9]+]], $[[T4]], $zero
+  ; GP32:       addu    $[[T5]], $4, $[[T5]]
+  ; GP32:       move    $4, $[[T2]]
+  ; GP32:       move    $5, $[[T0]]
+
+  ; GP64:       daddiu  $[[T0:[0-9]+]], $5, 3
+  ; GP64:       daddiu  $[[T1:[0-9]+]], $zero, 3
+  ; GP64:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; GP64:       daddu   $2, $4, $[[T1]]
+
+  ; MM32:       addiu   $[[T0:[0-9]+]], $7, 3
+  ; MM32:       li16    $[[T1:[0-9]+]], 3
+  ; MM32:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; MM32:       addu    $[[T2:[0-9]+]], $6, $[[T1]]
+  ; MM32:       lui     $[[T3:[0-9]+]], 0
+  ; MM32:       sltu    $[[T4:[0-9]+]], $[[T2]], $[[T3]]
+  ; MM32:       addu    $[[T4]], $5, $[[T4]]
+  ; MM32:       sltu    $[[T5:[0-9]+]], $[[T4]], $[[T3]]
+  ; MM32:       addu    $[[T5]], $4, $[[T5]]
+  ; MM32:       move    $4, $[[T2]]
+  ; MM32:       move    $5, $[[T0]]
+
+  ; MM64:       daddiu  $[[T0:[0-9]+]], $5, 3
+  ; MM64:       daddiu  $[[T1:[0-9]+]], $zero, 3
+  ; MM64:       sltu    $[[T1]], $[[T0]], $[[T1]]
+  ; MM64:       daddu   $2, $4, $[[T1]]
+
+  %r = add i128 3, %a
+  ret i128 %r
+}

llvm/trunk/test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16
 0x5a 0x32 0x2a 0xfc # CHECK: dmtc0 $17, $18, 5
 0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20
 0x02 0xb6 0x7d 0x3c # CHECK: dmtc2 $21, $22
 0x5a 0x51 0x00 0xfc # CHECK: dmfc0 $18, $17
 0x59 0x21 0x08 0xfc # CHECK: dmfc0 $9, $1, 1
 0x55 0x24 0x24 0x3b # CHECK: dmfc1 $9, $f4
 0x01 0xd2 0x6d 0x3c # CHECK: dmfc2 $14, $18
+0x58 0xe6 0x49 0x10 # CHECK: dadd $9, $6, $7
+0x5b 0xe1 0x99 0x10 # CHECK: dadd $19, $1, $ra
+0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079
+0x5d 0x26 0xc5 0x67 # CHECK: daddiu $9, $6, -15001
+0x5d 0x29 0xc5 0x67 # CHECK: daddiu $9, $9, -15001
+0x5d 0x23 0x00 0x20 # CHECK: daddiu $9, $3, 32
+0x5f 0x56 0xee 0x16 # CHECK: daddiu $26, $22, -4586
+0x5d 0xeb 0xec 0x5f # CHECK: daddiu $15, $11, -5025
+0x5d 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586
+0x5e 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
+0x5d 0x7a 0x7c 0xcd # CHECK: daddiu $11, $26, 31949
+0x5f 0xbd 0xff 0xe0 # CHECK: daddiu $sp, $sp, -32
+0x59 0x61 0xd1 0x50 # CHECK: daddu $26, $1, $11
+0x5b 0xe1 0x99 0x50 # CHECK: daddu $19, $1, $ra
+0x58 0xe6 0x49 0x50 # CHECK: daddu $9, $6, $7
+0x58 0x69 0x49 0x50 # CHECK: daddu $9, $9, $3
+0x5d 0x26 0xc5 0x67 # CHECK: daddiu $9, $6, -15001
+0x5d 0x29 0x00 0x0a # CHECK: daddiu $9, $9, 10
+0x5e 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
+0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079
+0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5
+0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5

llvm/trunk/test/MC/Mips/micromips64r6/valid.s

a:
         dmtc0 $15, $16           # CHECK: dmtc0 $15, $16, 0       # encoding: [0x59,0xf0,0x02,0xfc]
         dmtc0 $17, $18, 5        # CHECK: dmtc0 $17, $18, 5       # encoding: [0x5a,0x32,0x2a,0xfc]
         dmtc1 $19, $f20          # CHECK: dmtc1 $19, $f20         # encoding: [0x56,0x74,0x2c,0x3b]
         dmtc2 $21, $22           # CHECK: dmtc2 $21, $22          # encoding: [0x02,0xb6,0x7d,0x3c]
         dmfc0 $18, $17           # CHECK: dmfc0 $18, $17, 0       # encoding: [0x5a,0x51,0x00,0xfc]
         dmfc0 $9, $1, 1          # CHECK: dmfc0 $9, $1, 1         # encoding: [0x59,0x21,0x08,0xfc]
         dmfc1 $9, $f4            # CHECK: dmfc1 $9, $f4           # encoding: [0x55,0x24,0x24,0x3b]
         dmfc2 $14, $18           # CHECK: dmfc2 $14, $18          # encoding: [0x01,0xd2,0x6d,0x3c]
+        dadd $9, $6, $7          # CHECK: dadd $9, $6, $7         # encoding: [0x58,0xe6,0x49,0x10]
+        dadd $s3, $at, $ra       # CHECK: dadd $19, $1, $ra       # encoding: [0x5b,0xe1,0x99,0x10]
+        daddiu $24, $2, 18079    # CHECK: daddiu $24, $2, 18079   # encoding: [0x5f,0x02,0x46,0x9f]
+        daddiu $9, $6, -15001    # CHECK: daddiu $9, $6, -15001   # encoding: [0x5d,0x26,0xc5,0x67]
+        daddiu $9, -15001        # CHECK: daddiu $9, $9, -15001   # encoding: [0x5d,0x29,0xc5,0x67]
+        daddiu $9, $3, 8 * 4     # CHECK: daddiu $9, $3, 32       # encoding: [0x5d,0x23,0x00,0x20]
+        daddiu $9, $3, (8 * 4)   # CHECK: daddiu $9, $3, 32       # encoding: [0x5d,0x23,0x00,0x20]
+        daddiu $k0, $s6, -4586   # CHECK: daddiu $26, $22, -4586  # encoding: [0x5f,0x56,0xee,0x16]
+        daddiu $15, $11, -5025   # CHECK: daddiu $15, $11, -5025  # encoding: [0x5d,0xeb,0xec,0x5f]
+        daddiu $14, $14, 4586    # CHECK: daddiu $14, $14, 4586   # encoding: [0x5d,0xce,0x11,0xea]
+        daddiu $19, $19, 26943   # CHECK: daddiu $19, $19, 26943  # encoding: [0x5e,0x73,0x69,0x3f]
+        daddiu $11, $26, 31949   # CHECK: daddiu $11, $26, 31949  # encoding: [0x5d,0x7a,0x7c,0xcd]
+        daddiu $sp, $sp, -32     # CHECK: daddiu $sp, $sp, -32    # encoding: [0x5f,0xbd,0xff,0xe0]
+        daddu $26, $1, $11       # CHECK: daddu $26, $1, $11      # encoding: [0x59,0x61,0xd1,0x50]
+        daddu $19, $1, $ra       # CHECK: daddu $19, $1, $ra      # encoding: [0x5b,0xe1,0x99,0x50]
+        daddu $9, $6, $7         # CHECK: daddu $9, $6, $7        # encoding: [0x58,0xe6,0x49,0x50]
+        daddu $9, $3             # CHECK: daddu $9, $9, $3        # encoding: [0x58,0x69,0x49,0x50]
+        daddu $9, $6, -15001     # CHECK: daddiu $9, $6, -15001   # encoding: [0x5d,0x26,0xc5,0x67]
+        daddu $9, 10             # CHECK: daddiu $9, $9, 10       # encoding: [0x5d,0x29,0x00,0x0a]
+        daddu $19, 26943         # CHECK: daddiu $19, $19, 26943  # encoding: [0x5e,0x73,0x69,0x3f]
+        daddu $24, $2, 18079     # CHECK: daddiu $24, $2, 18079   # encoding: [0x5f,0x02,0x46,0x9f]
+        dsubu $3, 5              # CHECK: daddiu $3, $3, -5       # encoding: [0x5c,0x63,0xff,0xfb]
+        dsubu $3, $4, 5          # CHECK: daddiu $3, $4, -5       # encoding: [0x5c,0x64,0xff,0xfb]
 
 1: