[mips] Optimize materialization of i64 constants.

[vkalintiris]

Summary

Avoid MipsAnalyzeImmediate pass if the constant fits in an 32-bit
integer. This allows us to generate the same instructions for the
materialization of the same constants regardless the width of their
type.

Depends on D16221.

[dsanders]

lib/Target/Mips/MipsInstrInfo.td

2056

The bug is probably the use of 'imm' here. I think you want immSExt32.

test/CodeGen/Mips/cmov.ll

499–500

This constant now takes two instructions to materialize but it used to only take one.

test/CodeGen/Mips/load-store-left-right.ll

157–159

This isn't the same constant as the previous code.
New: 0xffff_ffff_ffff_ffff
Old: 0x0000_0000_ffff_ffff

test/MC/Mips/sext_64_32.ll

18–20

This is a nop now because the mask is 0xffff_ffff_ffff_ffff which is the case because lui is sign-extended. It's not clear from the test but I suspect it used to be 0x0000_0000_ffff_ffff which is best done with the dsll32/dsrl32 pair the old test is hinting at.

lib/Target/Mips/Mips64InstrInfo.td

 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
 def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
 }
 
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
+// Materialize i64 constants.
+defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>;
+
 // extended loads
 def : MipsPat<(i64 (extloadi1  addr:$src)), (LB64 addr:$src)>;
 def : MipsPat<(i64 (extloadi8  addr:$src)), (LB64 addr:$src)>;
 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
 
 // hi/lo relocs
 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;

lib/Target/Mips/MipsInstrInfo.td

 
 // Load/store pattern templates.
 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
   MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
 
 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
   MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
 
+// Materialize constants.
+multiclass MaterializeImms<ValueType VT, Register ZEROReg,
+                           Instruction ADDiuOp, Instruction LUiOp,
+                           Instruction ORiOp> {
 // Small immediates
 let AdditionalPredicates = [NotInMicroMips] in {
-def : MipsPat<(i32 immSExt16:$in),
-              (ADDiu ZERO, imm:$in)>;
-def : MipsPat<(i32 immZExt16:$in),
-              (ORi ZERO, imm:$in)>;
+def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>;
+def : MipsPat<(VT immZExt16:$imm), (ORiOp ZEROReg, imm:$imm)>;
 }
-def : MipsPat<(i32 immLow16Zero:$in),
-              (LUi (HI16 imm:$in))>;
+def : MipsPat<(VT immLow16Zero:$imm), (LUiOp (HI16 imm:$imm))>;
 
 // Arbitrary immediates
-def : MipsPat<(i32 imm:$imm),
-          (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
+def : MipsPat<(VT imm:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
+}
+
+defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>;
 
 // Carry MipsPatterns
 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
               (SUBu GPR32:$lhs, GPR32:$rhs)>;
 let AdditionalPredicates = [NotDSP] in {
   def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
                 (ADDu GPR32:$lhs, GPR32:$rhs)>;
   def : MipsPat<(addc  GPR32:$src, immSExt16:$imm),

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
 
       return std::make_pair(true, Result);
     }
     break;
   }
 
   case ISD::Constant: {
     const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
+    int64_t Imm = CN->getSExtValue();
     unsigned Size = CN->getValueSizeInBits(0);
 
-    if (Size == 32)
+    if (isInt<32>(Imm) || isUInt<32>(Imm))
       break;
 
     MipsAnalyzeImmediate AnalyzeImm;
-    int64_t Imm = CN->getSExtValue();
 
     const MipsAnalyzeImmediate::InstSeq &Seq =
       AnalyzeImm.Analyze(Imm, Size, false);
 
     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
     SDLoc DL(CN);
     SDNode *RegOpnd;
     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),

test/CodeGen/Mips/atomic.ll

 ; HAS-SEB-SEH:   seb     $[[R19:[0-9]+]], $[[R17]]
 
 ; MIPS32-ANY:    xor     $[[R20:[0-9]+]], $[[R19]], $5
 ; MIPS32-ANY:    sltiu   $2, $[[R20]], 1
 
 ; FIXME: avoid redundant sign/zero-extensions.
 ; MIPS64-ANY:    dsll    $[[R20:[0-9]+]], $[[R19]], 32
 ; MIPS64-ANY:    dsrl    $[[R21:[0-9]+]], $[[R20]], 32
-; MIPS64-ANY:    daddiu  $[[R22:[0-9]+]], $zero, 1
-; MIPS64-ANY:    dsll    $[[R23:[0-9]+]], $[[R22]], 32
-; MIPS64-ANY:    daddiu  $[[R24:[0-9]+]], $[[R23]], -1
-; MIPS64-ANY:    and     $[[R25:[0-9]+]], $5, $[[R24]]
+; MIPS64-ANY:    lui     $[[R22:[0-9]+]], 65535
+; MIPS64-ANY:    ori     $[[R23:[0-9]+]], $[[R22]], 65535
+; MIPS64-ANY:    and     $[[R25:[0-9]+]], $5, $[[R22]]
 ; MIPS64-ANY:    xor     $[[R26:[0-9]+]], $[[R21]], $[[R25]]
 ; MIPS64-ANY:    sltiu   $2, $[[R26]], 1
 }
 
 ; Check one i16 so that we cover the seh sign extend
 @z = common global i16 0, align 1
 
 define i16 @AtomicLoadAdd16(i16 signext %incr) nounwind {

test/CodeGen/Mips/cmov.ll

 ; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768
 ; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
-; FIXME: Fix constant materialization for i64 imms.
-; 64-CMP-DAG:  daddiu  $[[R0:[0-9]+]], $zero, 1
-; 64-CMP-DAG:  dsll    $[[R1:[0-9]+]], $[[R0]], 48
-; 64-CMP-DAG:  daddiu  $[[R2:[0-9]+]], $[[R1]], -1
-; 64-CMP-DAG:  dsll    $[[R3:[0-9]+]], $[[R2]], 16
-; 64-CMP-DAG:  daddiu  $[[R4:[0-9]+]], $[[R3]], 32767
+; 64-CMP-DAG:  lui $[[R0:[0-9]+]], 65535
+; 64-CMP-DAG:  ori $[[R1:[0-9]+]], $[[R0]], 32767
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3{{$}}
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  slt $[[R5:[0-9]+]], $[[R4]], $4
+; 64-CMP-DAG:  slt $[[R2:[0-9]+]], $[[R1]], $4
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R5]]
-; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I3]], $[[R5]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R2]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I3]], $[[R2]]
 ; 64-CMP-DAG:  or $2, $[[T1]], $[[T0]]
 
 define i32 @slti2(i32 signext %a) {
 entry:
   %cmp = icmp sgt i32 %a, -32769
   %cond = select i1 %cmp, i32 3, i32 5
   ret i32 %cond
 }

 ; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 64-CMOV-DAG: slt $[[R0:[0-9]+]], ${{[0-9]+}}, $4
 ; 64-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]]
 
-; FIXME: Fix constant materialization for i64 imms.
-; 64-CMP-DAG:  daddiu  $[[R0:[0-9]+]], $zero, 1
-; 64-CMP-DAG:  dsll    $[[R1:[0-9]+]], $[[R0]], 48
-; 64-CMP-DAG:  daddiu  $[[R2:[0-9]+]], $[[R1]], -1
-; 64-CMP-DAG:  dsll    $[[R3:[0-9]+]], $[[R2]], 16
-; 64-CMP-DAG:  daddiu  $[[R4:[0-9]+]], $[[R3]], 32766
+; 64-CMP-DAG:  lui $[[R0:[0-9]+]], 65535
+; 64-CMP-DAG:  ori $[[R1:[0-9]+]], $[[R0]], 32766
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3{{$}}
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  slt $[[R5:[0-9]+]], $[[R4]], $4
+; 64-CMP-DAG:  slt $[[R2:[0-9]+]], $[[R1]], $4
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R5]]
-; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I3]], $[[R5]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R2]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I3]], $[[R2]]
 ; 64-CMP-DAG:  or $2, $[[T1]], $[[T0]]
 
 define i32 @slti3(i32 signext %a) {
 entry:
   %cmp = icmp sgt i32 %a, -32770
   %cond = select i1 %cmp, i32 3, i32 5
   ret i32 %cond
 }

 entry:
   %cmp = icmp sgt i32 %a, -32770
   %conv = select i1 %cmp, i32 5, i32 4
   ret i32 %conv
 }
 
 ; ALL-LABEL: slti64_3:
 
-; 64-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32766
-; 64-DAG: slt $[[R1:[0-9]+]], $[[R0]], $4
-; 64-DAG: ori $2, $[[R1]], 4
+; 64-DAG: lui $[[R0:[0-9]+]], 65535
+; 64-DAG: ori $[[R1:[0-9]+]], $[[R0]], 32766
+; 64-DAG: slt $[[R2:[0-9]+]], $[[R1]], $4
+; 64-DAG: ori $2, $[[R2]], 4
 define i64 @slti64_3(i64 %a) {
 entry:
   %cmp = icmp sgt i64 %a, -32770
   %conv = select i1 %cmp, i64 5, i64 4
   ret i64 %conv
 }
 
 ; sltiu instructions.

 ; 32-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768
 ; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]]
 
-; FIXME: Fix constant materialization for i64 imms.
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMP-DAG:  addiu $[[I5:[0-9]+]], $zero, 5
-; 64-CMP-DAG:  daddiu  $[[R0:[0-9]+]], $zero, 1
-; 64-CMP-DAG:  dsll    $[[R1:[0-9]+]], $[[R0]], 48
-; 64-CMP-DAG:  daddiu  $[[R2:[0-9]+]], $[[R1]], -1
-; 64-CMP-DAG:  dsll    $[[R3:[0-9]+]], $[[R2]], 16
-; 64-CMP-DAG:  daddiu  $[[R4:[0-9]+]], $[[R3]], 32767
-; 64-CMP-DAG:  sltu $[[R5:[0-9]+]], $[[R4]], $4
+; 64-CMP-DAG:  lui $[[R0:[0-9]+]], 65535
+; 64-CMP-DAG:  ori $[[R1:[0-9]+]], $[[R0]], 32767
+; 64-CMP-DAG:  sltu $[[R2:[0-9]+]], $[[R1]], $4
 ; FIXME: We can do better than this by using selccz to choose between +0 and +2
-; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R5]]
-; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I3]], $[[R5]]
+; 64-CMP-DAG:  seleqz $[[T0:[0-9]+]], $[[I5]], $[[R1]]
+; 64-CMP-DAG:  selnez $[[T1:[0-9]+]], $[[I3]], $[[R1]]
 ; 64-CMP-DAG:  or $2, $[[T1]], $[[T0]]
 
 define i32 @sltiu2(i32 signext %a) {
 entry:
   %cmp = icmp ugt i32 %a, -32769
   %cond = select i1 %cmp, i32 3, i32 5
   ret i32 %cond
 }

 ; 32-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]]
 ; 32-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
 ; 64-CMOV-DAG: sltu $[[R0:[0-9]+]], ${{[0-9]+}}, $4
 ; 64-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]]
 
-; FIXME: Fix constant materialization for i64 imms.
 ; 64-CMP-DAG:  addiu $[[I3:[0-9]+]], $zero, 3
 ; 64-CMP-DAG:  addiu $[[I5:2]], $zero, 5
-; 64-CMP-DAG:  daddiu  $[[R0:[0-9]+]], $zero, 1
-; 64-CMP-DAG:  dsll    $[[R1:[0-9]+]], $[[R0]], 48
-; 64-CMP-DAG:  daddiu  $[[R2:[0-9]+]], $[[R1]], -1
-; 64-CMP-DAG:  dsll    $[[R3:[0-9]+]], $[[R2]], 16
-; 64-CMP-DAG:  daddiu  $[[R4:[0-9]+]], $[[R3]], 32766
-; 64-CMP-DAG:  sltu $[[R5:[0-9]+]], $[[R4]], $4
+; 64-CMP-DAG:  lui $[[R0:[0-9]+]], 65535
+; 64-CMP-DAG:  ori $[[R1:[0-9]+]], $[[R0]], 32766
+; 64-CMP-DAG:  sltu $[[R2:[0-9]+]], $[[R1]], $4
 ; FIXME: We can do better than this by using selccz to choose between -0 and -2
-; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R5]]
-; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R5]]
+; 64-CMP-DAG:  selnez $[[T0:[0-9]+]], $[[I3]], $[[R2]]
+; 64-CMP-DAG:  seleqz $[[T1:[0-9]+]], $[[I5]], $[[R2]]
 ; 64-CMP-DAG:  or $2, $[[T0]], $[[T1]]
 
 define i32 @sltiu3(i32 signext %a) {
 entry:
   %cmp = icmp ugt i32 %a, -32770
   %cond = select i1 %cmp, i32 3, i32 5
   ret i32 %cond
 }

test/CodeGen/Mips/llvm-ir/ret.ll

 
 define i64 @ret_i64_65537() {
 ; ALL-LABEL: ret_i64_65537:
 ; ALL:           lui $[[T0:[0-9]+]], 1
 
 ; GPR32-DAG:     ori $3, $[[T0]], 1
 ; GPR32-DAG:     addiu $2, $zero, 0
 
-; GPR64-DAG:     daddiu $2, $[[T0]], 1
+; GPR64-DAG:     ori $2, $[[T0]], 1
 
 ; NOT-R6-DAG:    jr $ra # <MCInst #{{[0-9]+}} JR
 ; R6-DAG:        jr $ra # <MCInst #{{[0-9]+}} JALR
 
   ret i64 65537
 }
 
 define i64 @ret_i64_281479271677952() {

test/CodeGen/Mips/load-store-left-right.ll

 ; MIPS32R6:        lw $[[PTR:[0-9]+]], %got(sui)(
 ; MIPS32R6-EL-DAG: lw $2, 0($[[PTR]])
 ; MIPS32R6-EL-DAG: addiu $3, $zero, 0
 ; MIPS32R6-EB-DAG: lw $3, 0($[[PTR]])
 ; MIPS32R6-EB-DAG: addiu $2, $zero, 0
 
 ; MIPS64-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
 ; MIPS64-EL-DAG: lwr $[[R0]], 0($[[R1]])
-; MIPS64-EL-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
-; MIPS64-EL-DAG: dsll   $[[R3:[0-9]+]], $[[R2]], 32
-; MIPS64-EL-DAG: daddiu $[[R4:[0-9]+]], $[[R3]], -1
-; MIPS64-EL-DAG: and    ${{[0-9]+}}, $[[R0]], $[[R4]]
-
+; MIPS64-EL-DAG: lui $[[R1:[0-9]+]], 65535
+; MIPS64-EL-DAG: ori $[[R2:[0-9]+]], $[[R1]], 65535
+; MIPS64-EL-DAG: and    ${{[0-9]+}}, $[[R0]], $[[R2]]
 ; MIPS64-EB:     lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
 ; MIPS64-EB:     lwr $[[R0]], 3($[[R1]])
 
 ; MIPS64R6:      ld $[[PTR:[0-9]+]], %got_disp(sui)(
 ; MIPS64R6:      lwu $2, 0($[[PTR]])
 
   %0 = load i32, i32* getelementptr inbounds (%struct.SUI, %struct.SUI* @sui, i64 0, i32 0), align 1
   %conv = zext i32 %0 to i64

test/CodeGen/Mips/mips64imm.ll

 ; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
 
 define i32 @foo1() nounwind readnone {
 entry:
 ; CHECK: foo1
 ; CHECK: lui ${{[0-9]+}}, 4660
 ; CHECK-NOT: ori
   ret i32 305397760
 }
 
 define i64 @foo3() nounwind readnone {
 entry:
 ; CHECK: foo3
 ; CHECK: lui $[[R0:[0-9]+]], 4660
-; CHECK: daddiu ${{[0-9]+}}, $[[R0]], 22136
+; CHECK: ori ${{[0-9]+}}, $[[R0]], 22136
   ret i64 305419896
 }
 
 define i64 @foo6() nounwind readnone {
 entry:
 ; CHECK: foo6
 ; CHECK: ori ${{[0-9]+}}, $zero, 33332
   ret i64 33332

test/MC/Mips/sext_64_32.ll

-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - | \
+; RUN:    llvm-objdump -disassemble -triple mips64el - | FileCheck %s
 
 ; Sign extend from 32 to 64 was creating nonsense opcodes
 
-; CHECK: sll ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
-
-define i64 @foo(i32 %ival) nounwind readnone {
+define i64 @foo(i32 zeroext %ival) nounwind readnone {
 entry:
+; CHECK-LABEL: foo:
+
+; CHECK: sll $2, $4, 0
   %conv = sext i32 %ival to i64
   ret i64 %conv
 }
 
-; CHECK: dsll32 ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
+define i64 @bar(i32 signext %ival_2) nounwind readnone {
+; CHECK-LABEL: bar:
 
-define i64 @foo_2(i32 %ival_2) nounwind readnone {
+; CHECK: lui $[[R0:[0-9]+]], 65535
+; CHECK: ori $[[R1:[0-9]+]], $[[R0]], 65535
+; CHECK: and $2, $4, $[[R1]]
 entry:
   %conv_2 = zext i32 %ival_2 to i64
   ret i64 %conv_2
 }
-