[SPIRV] Fix OpConstant float and double printing

[sudonatalie]

Summary

Print OpConstant floats as formatted decimal floating points, with
special case exceptions to print infinity and NaN as hexfloats.

This change follows from the fixes in
https://github.com/llvm/llvm-project/pull/66686 to correct how
constant values are printed generally.

[sudonatalie]

math.h -> APFloat

[mpaszkowski]

@sudonatalie Thank you for the patch! LGTM!

[sudonatalie]

This patch needs changes to interoperate correctly with the MCCodeEmitter (llc -filetype=obj) before landing.

[sudonatalie]

Remove changes to lowering logic and get context from the instruction type rather than operand for printing

[sudonatalie]

Requesting re-review since this patch has been substantially changed. There is no longer any change to ISel so the machine code accurately represents the number of operands in the SPIR-V, and it does not interfere with the behavior of the binary printer.

[Keenuts]

Thanks for fixing!

llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp

 //===-- SPIRVInstPrinter.cpp - Output SPIR-V MCInsts as ASM -----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This class prints a SPIR-V MCInst to a .s file.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SPIRVInstPrinter.h"
 #include "SPIRV.h"
 #include "SPIRVBaseInfo.h"
+#include "llvm/ADT/APFloat.h"
 #include "llvm/CodeGen/Register.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/ErrorHandling.h"
if (!SkipImmediates || !MI->getOperand(i).isImm()) {
       printOperand(MI, i, O);
     }
   }
 }
 
 void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI,
                                              unsigned StartIndex,
                                              raw_ostream &O) {
+  const unsigned NumVarOps = MI->getNumOperands() - StartIndex;
+
+  assert((NumVarOps == 1 || NumVarOps == 2) &&
+         "Unsupported number of bits for literal variable");
+
   O << ' ';
-  if (MI->getNumOperands() - StartIndex == 2) { // Handle 64 bit literals.
-    uint64_t Imm = MI->getOperand(StartIndex).getImm();
+
+
+  // Handle 64 bit literals.
+  if (NumVarOps == 2) {
     Imm |= (MI->getOperand(StartIndex + 1).getImm() << 32);
-    O << Imm;
-  } else {
-    printRemainingVariableOps(MI, StartIndex, O, true, false);
   }
+
+  // Format and print float values.
+  if (MI->getOpcode() == SPIRV::OpConstantF) {
+    APFloat FP = NumVarOps == 1 ? APFloat(APInt(32, Imm).bitsToFloat())
+                                : APFloat(APInt(64, Imm).bitsToDouble());
+
+    // Print infinity and NaN as hex floats.
+    // TODO: Make sure subnormal numbers are handled correctly as they may also
+    // require hex float notation.
+    if (FP.isInfinity()) {
+      if (FP.isNegative())
+        O << '-';
+      O << "0x1p+128";
+      return;
+    }
+    if (FP.isNaN()) {
+      O << "0x1.8p+128";
+      return;
+    }
+
+    // Format val as a decimal floating point or scientific notation (whichever
+    // is shorter), with enough digits of precision to produce the exact value.
+    O << format("%.*g", std::numeric_limits<double>::max_digits10,
+                FP.convertToDouble());
+
+    return;
+  }
+
+  // Print integer values directly.
+  O << Imm;
 }
 
 void SPIRVInstPrinter::recordOpExtInstImport(const MCInst *MI) {
   Register Reg = MI->getOperand(0).getReg();
   auto Name = getSPIRVStringOperand(*MI, 1);
   auto Set = getExtInstSetFromString(Name);
   ExtInstSetIDs.insert({Reg, Set});
 }

llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll

 ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
 
 ;; Types:
 ; CHECK:         %[[#F32:]] = OpTypeFloat 32
 ;; Constants:
-; CHECK:         %[[#CONST:]] = OpConstant %[[#F32]] 1065353216
+; CHECK:         %[[#CONST:]] = OpConstant %[[#F32]] 1
 ;; Atomic instructions:
 ; CHECK:         OpStore %[[#]] %[[#CONST]]
 ; CHECK-COUNT-3: OpAtomicStore
 ; CHECK-COUNT-3: OpAtomicLoad
 ; CHECK-COUNT-3: OpAtomicExchange
 
 define spir_kernel void @test_atomic_kernel(float addrspace(3)* %ff) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !6 !kernel_arg_type_qual !7 {
 entry:

llvm/test/CodeGen/SPIRV/atomicrmw.ll

 ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
 
 ; CHECK:     %[[#Int:]] = OpTypeInt 32 0
 ; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1{{$}}
 ; CHECK-DAG: %[[#MemSem_Relaxed:]] = OpConstant %[[#Int]] 0
 ; CHECK-DAG: %[[#MemSem_Acquire:]] = OpConstant %[[#Int]] 2
 ; CHECK-DAG: %[[#MemSem_Release:]] = OpConstant %[[#Int]] 4{{$}}
 ; CHECK-DAG: %[[#MemSem_AcquireRelease:]] = OpConstant %[[#Int]] 8
 ; CHECK-DAG: %[[#MemSem_SequentiallyConsistent:]] = OpConstant %[[#Int]] 16
 ; CHECK-DAG: %[[#Value:]] = OpConstant %[[#Int]] 42
 ; CHECK-DAG: %[[#Float:]] = OpTypeFloat 32
 ; CHECK-DAG: %[[#PointerType:]] = OpTypePointer CrossWorkgroup %[[#Int]]
 ; CHECK-DAG: %[[#FPPointerType:]] = OpTypePointer CrossWorkgroup %[[#Float]]
 ; CHECK-DAG: %[[#Pointer:]] = OpVariable %[[#PointerType]] CrossWorkgroup
 ; CHECK-DAG: %[[#FPPointer:]] = OpVariable %[[#FPPointerType]] CrossWorkgroup
-; CHECK-DAG: %[[#FPValue:]] = OpConstant %[[#Float]] 1109917696
+; CHECK-DAG: %[[#FPValue:]] = OpConstant %[[#Float]] 42
 
 @ui = common dso_local addrspace(1) global i32 0, align 4
 @f = common dso_local local_unnamed_addr addrspace(1) global float 0.000000e+00, align 4
 
 define dso_local spir_func void @test_atomicrmw() local_unnamed_addr {
 entry:
   %0 = atomicrmw xchg i32 addrspace(1)* @ui, i32 42 acq_rel
 ; CHECK: %[[#]] = OpAtomicExchange %[[#Int]] %[[#Pointer]] %[[#Scope_Device]] %[[#MemSem_AcquireRelease]] %[[#Value]]

llvm/test/CodeGen/SPIRV/literals.ll

+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+
+; CHECK: %[[#F32:]] = OpTypeFloat 32
+; CHECK: %[[#F64:]] = OpTypeFloat 64
+
+define void @main() {
+entry:
+
+; CHECK: OpConstant %[[#F32]] 0.5
+  %f = alloca float, align 4
+  store float 5.000000e-01, ptr %f, align 4
+
+; CHECK: OpConstant %[[#F64]] 0.5
+  %d = alloca double, align 8
+  store double 5.000000e-01, ptr %d, align 8
+
+; CHECK: OpConstant %[[#F32]] 1.0000016166037976e-39
+  %hexf = alloca float, align 4
+  store float 0x37D5C73200000000, ptr %hexf, align 4
+
+; CHECK: OpConstant %[[#F32]] 0x1p+128
+  %inf = alloca float, align 4
+  store float 0x7FF0000000000000, ptr %inf, align 4
+
+; CHECK: OpConstant %[[#F32]] -0x1p+128
+  %ninf = alloca float, align 4
+  store float 0xFFF0000000000000, ptr %ninf, align 4
+
+; CHECK: OpConstant %[[#F32]] 0x1.8p+128
+  %nan = alloca float, align 4
+  store float 0x7FF8000000000000, ptr %nan, align 4
+
+  ret void
+}