[llvm] Add assembly syntax highlighting for X86

[JDevlieghere]

Summary

Add support for syntax highlighting X86 assembly.

[JDevlieghere]

• Rebase and add Markup::Memory

llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp

 
 #define DEBUG_TYPE "asm-printer"
 
 // Include the auto-generated portion of the assembly writer.
 #define PRINT_ALIAS_INSTR
 #include "X86GenAsmWriter.inc"
 
 void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
-  OS << markup("<reg:") << '%' << getRegisterName(Reg) << markup(">");
+  markup(OS, Markup::Register) << '%' << getRegisterName(Reg);
 }
 
 void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                   StringRef Annot, const MCSubtargetInfo &STI,
                                   raw_ostream &OS) {
   // If verbose assembly is enabled, we can print some informative comments.
   if (CommentStream)
     HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII);

 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                      raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     printRegName(O, Op.getReg());
   } else if (Op.isImm()) {
     // Print immediates as signed values.
     int64_t Imm = Op.getImm();
-    O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
+    markup(O, Markup::Immediate) << '$' << formatImm(Imm);
 
     // TODO: This should be in a helper function in the base class, so it can
     // be used by other printers.
 
     // If there are no instruction-specific comments, add a comment clarifying
     // the hex value of the immediate operand when it isn't in the range
     // [-256,255].
     if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
       // Don't print unnecessary hex sign bits.
       if (Imm == (int16_t)(Imm))
         *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
       else if (Imm == (int32_t)(Imm))
         *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
       else
         *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
     }
   } else {
     assert(Op.isExpr() && "unknown operand kind in printOperand");
-    O << markup("<imm:") << '$';
+    WithMarkup M = markup(O, Markup::Immediate);
+    O << '$';
     Op.getExpr()->print(O, &MAI);
-    O << markup(">");
   }
 }
 
 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
                                           raw_ostream &O) {
   // Do not print the exact form of the memory operand if it references a known
   // binary object.
   if (SymbolizeOperands && MIA) {
     uint64_t Target;
     if (MIA->evaluateBranch(*MI, 0, 0, Target))
       return;
     if (MIA->evaluateMemoryOperandAddress(*MI, /*STI=*/nullptr, 0, 0))
       return;
   }
 
   const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
   const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
   const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
 
-  O << markup("<mem:");
+  WithMarkup M = markup(O, Markup::Memory);
 
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
 
   if (DispSpec.isImm()) {
     int64_t DispVal = DispSpec.getImm();
     if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
       O << formatImm(DispVal);
   } else {
     assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
     DispSpec.getExpr()->print(O, &MAI);
   }
 
   if (IndexReg.getReg() || BaseReg.getReg()) {
     O << '(';
     if (BaseReg.getReg())
       printOperand(MI, Op + X86::AddrBaseReg, O);
 
     if (IndexReg.getReg()) {
       O << ',';
       printOperand(MI, Op + X86::AddrIndexReg, O);
       unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
       if (ScaleVal != 1) {
-        O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
-          << markup(">");
+        O << ',';
+        markup(O, Markup::Immediate) << ScaleVal; // never printed in hex.
       }
     }
     O << ')';
   }
-
-  O << markup(">");
 }
 
 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
                                     raw_ostream &O) {
-  O << markup("<mem:");
+  WithMarkup M = markup(O, Markup::Memory);
 
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + 1, O);
 
   O << "(";
   printOperand(MI, Op, O);
   O << ")";
-
-  O << markup(">");
 }
 
 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
                                     raw_ostream &O) {
-  O << markup("<mem:");
+  WithMarkup M = markup(O, Markup::Memory);
 
   O << "%es:(";
   printOperand(MI, Op, O);
   O << ")";
-
-  O << markup(">");
 }
 
 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
                                        raw_ostream &O) {
   const MCOperand &DispSpec = MI->getOperand(Op);
 
-  O << markup("<mem:");
+  WithMarkup M = markup(O, Markup::Memory);
 
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + 1, O);
 
   if (DispSpec.isImm()) {
     O << formatImm(DispSpec.getImm());
   } else {
     assert(DispSpec.isExpr() && "non-immediate displacement?");
     DispSpec.getExpr()->print(O, &MAI);
   }
-
-  O << markup(">");
 }
 
 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
                                    raw_ostream &O) {
   if (MI->getOperand(Op).isExpr())
     return printOperand(MI, Op, O);
 
-  O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
-    << markup(">");
+  markup(O, Markup::Immediate)
+      << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff);
 }
 
 void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
                                            raw_ostream &OS) {
   const MCOperand &Op = MI->getOperand(OpNo);
   unsigned Reg = Op.getReg();
   // Override the default printing to print st(0) instead st.
   if (Reg == X86::ST0)
-    OS << markup("<reg:") << "%st(0)" << markup(">");
+    markup(OS, Markup::Register) << "%st(0)";
   else
     printRegName(OS, Reg);
 }

llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp

 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address,
                                          unsigned OpNo, raw_ostream &O) {
   // Do not print the numberic target address when symbolizing.
   if (SymbolizeOperands)
     return;
 
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isImm()) {
-    O << markup("<imm:");
     if (PrintBranchImmAsAddress) {
       uint64_t Target = Address + Op.getImm();
       if (MAI.getCodePointerSize() == 4)
         Target &= 0xffffffff;
-      O << formatHex(Target);
+      markup(O, Markup::Target) << formatHex(Target);
     } else
-      O << formatImm(Op.getImm());
-    O << markup(">");
+      markup(O, Markup::Immediate) << formatImm(Op.getImm());
   } else {
     assert(Op.isExpr() && "unknown pcrel immediate operand");
     // If a symbolic branch target was added as a constant expression then print
     // that address in hex.
     const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
     int64_t Address;
     if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
-      O << markup("<imm:") << formatHex((uint64_t)Address) << markup(">");
+      markup(O, Markup::Immediate) << formatHex((uint64_t)Address);
     } else {
       // Otherwise, just print the expression.
       Op.getExpr()->print(O, &MAI);
     }
   }
 }
 
 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo,

llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp

 
 #define DEBUG_TYPE "asm-printer"
 
 // Include the auto-generated portion of the assembly writer.
 #define PRINT_ALIAS_INSTR
 #include "X86GenAsmWriter1.inc"
 
 void X86IntelInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
-  OS << markup("<reg:") << getRegisterName(Reg) << markup(">");
+  markup(OS, Markup::Register) << getRegisterName(Reg);
 }
 
 void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                     StringRef Annot, const MCSubtargetInfo &STI,
                                     raw_ostream &OS) {
   printInstFlags(MI, OS, STI);
 
   // In 16-bit mode, print data16 as data32.

 }
 
 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     printRegName(O, Op.getReg());
   } else if (Op.isImm()) {
-    O << markup("<imm:") << formatImm((int64_t)Op.getImm()) << markup(">");
+    markup(O, Markup::Immediate) << formatImm((int64_t)Op.getImm());
   } else {
     assert(Op.isExpr() && "unknown operand kind in printOperand");
     O << "offset ";
     Op.getExpr()->print(O, &MAI);
   }
 }
 
 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
   const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
   unsigned ScaleVal         = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
   const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
   const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
 
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
 
-  O << markup("<mem:") << '[';
+  WithMarkup M = markup(O, Markup::Memory);
+  O << '[';
 
   bool NeedPlus = false;
   if (BaseReg.getReg()) {
     printOperand(MI, Op+X86::AddrBaseReg, O);
     NeedPlus = true;
   }
 
   if (IndexReg.getReg()) {
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
       if (NeedPlus) {
         if (DispVal > 0)
           O << " + ";
         else {
           O << " - ";
           DispVal = -DispVal;
         }
       }
-      O << markup("<imm:") << formatImm(DispVal) << markup(">");
+      markup(O, Markup::Immediate) << formatImm(DispVal);
     }
   }
 
-  O << ']' << markup(">");
+  O << ']';
 }
 
 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
                                       raw_ostream &O) {
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + 1, O);
-  O << markup("<mem:") << '[';
+
+  WithMarkup M = markup(O, Markup::Memory);
+  O << '[';
   printOperand(MI, Op, O);
-  O << ']' << markup(">");
+  O << ']';
 }
 
 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
                                       raw_ostream &O) {
   // DI accesses are always ES-based.
-  O << "es:" << markup("<mem:") << '[';
+  O << "es:";
+
+  WithMarkup M = markup(O, Markup::Memory);
+  O << '[';
   printOperand(MI, Op, O);
-  O << ']' << markup(">");
+  O << ']';
 }
 
 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
                                          raw_ostream &O) {
   const MCOperand &DispSpec = MI->getOperand(Op);
 
   // If this has a segment register, print it.
   printOptionalSegReg(MI, Op + 1, O);
 
-  O << markup("<mem:") << '[';
+  WithMarkup M = markup(O, Markup::Memory);
+  O << '[';
 
   if (DispSpec.isImm()) {
-    O << markup("<imm:") << formatImm(DispSpec.getImm()) << markup(">");
+    markup(O, Markup::Immediate) << formatImm(DispSpec.getImm());
   } else {
     assert(DispSpec.isExpr() && "non-immediate displacement?");
     DispSpec.getExpr()->print(O, &MAI);
   }
 
-  O << ']' << markup(">");
+  O << ']';
 }
 
 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
                                      raw_ostream &O) {
   if (MI->getOperand(Op).isExpr())
     return MI->getOperand(Op).getExpr()->print(O, &MAI);
 
-  O << markup("<imm:") << formatImm(MI->getOperand(Op).getImm() & 0xff)
-    << markup(">");
+  markup(O, Markup::Immediate) << formatImm(MI->getOperand(Op).getImm() & 0xff);
 }
 
 void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
                                             raw_ostream &OS) {
   const MCOperand &Op = MI->getOperand(OpNo);
   unsigned Reg = Op.getReg();
   // Override the default printing to print st(0) instead st.
   if (Reg == X86::ST0)
     OS << "st(0)";
   else
     printRegName(OS, Reg);
 }