AMDGPU: Drop unsafe 1/sqrt -> rsq combine

[arsenm]

Summary

AMDGPUCodeGenPrepare implements a safer version of this that handles
denormals correctly.

[arsenm]

c8eeee2be2db2bd7a469065878852a5833add9b9

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

if (CLHS->isExactlyValue(1.0)) {
       B.buildIntrinsic(Intrinsic::amdgcn_rcp, Res)
           .addUse(RHS)
           .setMIFlags(Flags);
 
       MI.eraseFromParent();
       return true;
     }
 
-    // TODO: Match rsq
-
     // -1 / x -> RCP( FNEG(x) )
     if (CLHS->isExactlyValue(-1.0)) {
       auto FNeg = B.buildFNeg(ResTy, RHS, Flags);
       B.buildIntrinsic(Intrinsic::amdgcn_rcp, Res)
           .addUse(FNeg.getReg(0))
           .setMIFlags(Flags);
 
       MI.eraseFromParent();

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

if (CLHS->isExactlyValue(1.0)) {
       // use it as long as we aren't trying to use denormals.
       //
       // v_rcp_f16 and v_rsq_f16 DO support denormals and 0.51ulp.
 
       // 1.0 / sqrt(x) -> rsq(x)
 
       // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
       // error seems really high at 2^29 ULP.
-
-      // XXX - do we need afn for this or is arcp sufficent?
-      if (RHS.getOpcode() == ISD::FSQRT)
-        return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
-
       // 1.0 / x -> rcp(x)
       return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
     }
 
     // Same as for 1.0, but expand the sign out of the constant.
     if (CLHS->isExactlyValue(-1.0)) {
       // -1.0 / x -> rcp (fneg x)
       SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);