[llvm][ARM][Neon][big-endian] Fix incorrect indexing of lanes

[amilendra]

Summary

Fixes #19762 (https://bugs.llvm.org/show_bug.cgi?id=1976)

vrev64.32 reverses the order of 32-bit elements in each doubleword.
This results in the ith lane in the operand register ending up in the
jth lane of the destination register as follows.

i=0 -> j=1
i=1 -> j=0
i=2 -> j=3
i=3 -> j=2

Take this into consideration in ARM Neon Big-Endian code generation.

[olista01]

I don't think this is the right way to fix this. Endianness shouldn't affect the ordering of lanes in registers, only when they are stored to memory. We've got some documentation on this at https://llvm.org/docs/BigEndianNEON.html.

If this is the right place to fix this, this patch only changes DSubReg_i32_reg, why do the rest not need to be modified too?

[amilendra]

Abandoning this revision because I don't think I will be working on this anytime soon.

llvm/lib/Target/ARM/ARMInstrInfo.td

 }]>;
 def DSubReg_i16_reg : SDNodeXForm<imm, [{
   assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
   return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N),
                                    MVT::i32);
 }]>;
 def DSubReg_i32_reg : SDNodeXForm<imm, [{
   assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
+  if (CurDAG->getDataLayout().isBigEndian())
+    return CurDAG->getTargetConstant(ARM::dsub_1 - N->getZExtValue()/2, SDLoc(N),
+                                    MVT::i32);
+  else
     return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N),
                                     MVT::i32);
 }]>;
 def DSubReg_f64_reg : SDNodeXForm<imm, [{
   assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
   return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N),
                                    MVT::i32);
 }]>;
 
 // Extract S sub-registers of Q/D registers.

llvm/test/CodeGen/ARM/legalize-bitcast.ll

 ; CHECK-NEXT:    vrev16.8 d16, d16
 ; CHECK-NEXT:    @ kill: def $d16 killed $d16 def $q8
 ; CHECK-NEXT:    vmov.f64 d17, d18
 ; CHECK-NEXT:    vstmia sp, {d16, d17} @ 16-byte Spill
 ; CHECK-NEXT:    b .LBB0_1
 ; CHECK-NEXT:  .LBB0_1: @ %bb.1
 ; CHECK-NEXT:    vldmia sp, {d16, d17} @ 16-byte Reload
 ; CHECK-NEXT:    vrev32.16 q8, q8
-; CHECK-NEXT:    vmov.f64 d16, d17
+; CHECK-NEXT:    @ kill: def $d16 killed $d16 killed $q8
 ; CHECK-NEXT:    vmov.32 r0, d16[0]
 ; CHECK-NEXT:    add sp, sp, #28
 ; CHECK-NEXT:    pop {r4}
 ; CHECK-NEXT:    bx lr
 bb.0:
   %vec6 = load <6 x i16>, ptr @vec6_p, align 1
   br label %bb.1
 

llvm/test/CodeGen/ARM/vget_lane-be.ll

+; RUN: llc < %s -mattr=+neon | FileCheck %s
+target triple = "armebv8a-arm-none-eabihf"
+
+define i32 @ele0(<4 x i32> %a) {
+entry:
+;CHECK-LABEL: ele0:
+;CHECK-NEXT: .fnstart
+;CHECK-NEXT: @ %bb.0:
+;CHECK-NEXT: vrev64.32 q8, q0
+;CHECK-NEXT: vmov.32   r0, d16[1]
+;CHECK-NEXT: bx        lr
+
+  %vget_lane = extractelement <4 x i32> %a, i64 3
+  ret i32 %vget_lane
+}
+
+define i32 @ele1(<4 x i32> %a) {
+entry:
+;CHECK-LABEL: ele1:
+;CHECK-NEXT: .fnstart
+;CHECK-NEXT: @ %bb.0:
+;CHECK-NEXT: vrev64.32 q8, q0
+;CHECK-NEXT: vmov.32   r0, d16[0]
+;CHECK-NEXT: bx        lr
+  %vget_lane = extractelement <4 x i32> %a, i64 2
+  ret i32 %vget_lane
+}
+
+define i32 @ele2(<4 x i32> %a) {
+entry:
+;CHECK-LABEL: ele2:
+;CHECK-NEXT: .fnstart
+;CHECK-NEXT: @ %bb.0:
+;CHECK-NEXT: vrev64.32 q8, q0
+;CHECK-NEXT: vmov.32   r0, d17[1]
+;CHECK-NEXT: bx        lr
+  %vget_lane = extractelement <4 x i32> %a, i64 1
+  ret i32 %vget_lane
+}
+
+define i32 @ele3(<4 x i32> %a) {
+entry:
+;CHECK-LABEL: ele3:
+;CHECK-NEXT: .fnstart
+;CHECK-NEXT: @ %bb.0:
+;CHECK-NEXT: vrev64.32 q8, q0
+;CHECK-NEXT: vmov.32   r0, d17[0]
+;CHECK-NEXT: bx        lr
+  %vget_lane = extractelement <4 x i32> %a, i64 0
+  ret i32 %vget_lane
+}