AMDGPU/SI: Simplify validation of flat instructions optional operands

[• tstellarAMD]

Summary

Use the target hook validateTargetOprandClass() for doing validation
on optional operands. This will help prevent us from getting "invalid
operand" errors in cases where we should see a different error mesaage.

[arsenm]

Typo in message: validateTargetOprandClass

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

1332

ArrayRef should be passed by value

[• tstellarAMD]

Pass ArrayRef by value.

[arsenm]

LGTM

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

void setForcedEncodingSize(unsigned Size) {
     ForcedEncodingSize = Size;
   }
 
   bool isForcedVOP3() const {
     return ForcedEncodingSize == 64;
   }
 
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
+  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
+                                      unsigned Kind) override;
   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
   bool ParseDirective(AsmToken DirectiveID) override;
   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
switch(getLexer().getKind()) {
         return MatchOperand_NoMatch;
     }
   }
 
   Operands.push_back(AMDGPUOperand::CreateImm(Bit, S, ImmTy));
   return MatchOperand_Success;
 }
 
+static bool isTokenValidOptionalOp(ArrayRef<OptionalOperand> Operands,
+                                   StringRef Token) {
+  for (const OptionalOperand &Op : Operands) {
+    if (Op.Name == Token)
+      return true;
+  }
+  return false;
+}
+
 static bool operandsHasOptionalOp(const OperandVector &Operands,
                                   const OptionalOperand &OOp) {
   for (unsigned i = 0; i < Operands.size(); i++) {
     const AMDGPUOperand &ParsedOp = ((const AMDGPUOperand &)*Operands[i]);
     if ((ParsedOp.isImm() && ParsedOp.getImmTy() == OOp.Type) ||
         (ParsedOp.isToken() && ParsedOp.getToken() == OOp.Name))
       return true;
 
static const OptionalOperand FlatOptionalOps [] = {
   {"tfe",    AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
 };
 
 static const OptionalOperand FlatAtomicOptionalOps [] = {
   {"slc",    AMDGPUOperand::ImmTySLC, true, 0, nullptr},
   {"tfe",    AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
 };
 
+static bool isTokenValidFlatOptionalOp(StringRef Token) {
+  return isTokenValidOptionalOp(FlatOptionalOps, Token);
+}
+
+static bool isTokenValidFlatAtomicOptionalOp(StringRef Token) {
+  return isTokenValidOptionalOp(FlatAtomicOptionalOps, Token);
+}
+
 AMDGPUAsmParser::OperandMatchResultTy
 AMDGPUAsmParser::parseFlatOptionalOps(OperandVector &Operands) {
   return parseOptionalOps(FlatOptionalOps, Operands);
 }
 
 AMDGPUAsmParser::OperandMatchResultTy
 AMDGPUAsmParser::parseFlatAtomicOptionalOps(OperandVector &Operands) {
   return parseOptionalOps(FlatAtomicOptionalOps, Operands);
extern "C" void LLVMInitializeAMDGPUAsmParser() {
   RegisterMCAsmParser<AMDGPUAsmParser> A(TheAMDGPUTarget);
   RegisterMCAsmParser<AMDGPUAsmParser> B(TheGCNTarget);
 }
 
 #define GET_REGISTER_MATCHER
 #define GET_MATCHER_IMPLEMENTATION
 #include "AMDGPUGenAsmMatcher.inc"
 
+unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
+                                                     unsigned Kind) {
+  AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(AsmOp);
+  if (!Op.isToken())
+    return MCTargetAsmParser::validateTargetOperandClass(Op, Kind);
+
+  StringRef Token = Op.getToken();
+
+  switch (Kind) {
+  default: break;
+  case MCK_FlatOptionalOps:
+    if (isTokenValidFlatOptionalOp(Token))
+      return Match_Success;
+    break;
+  case MCK_FlatAtomicOptionalOps:
+    if (isTokenValidFlatAtomicOptionalOp(Token))
+      return Match_Success;
+    break;
+  }
+
+  return MCTargetAsmParser::validateTargetOperandClass(Op, Kind);
+}
+

lib/Target/AMDGPU/SIInstrInfo.td

class GDSBaseMatchClass <string parser> : AsmOperandClass {
   let PredicateMethod = "isImm";
   let ParserMethod = parser;
   let RenderMethod = "addImmOperands";
 }
 
 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
 
+def FlatOptionalOpsMatchClass : AsmOperandClass {
+  let Name = "FlatOptionalOps";
+  let PredicateMethod = "isImm";
+  let ParserMethod = "parseFlatOptionalOps";
+  let RenderMethod = "addImmOperands";
+}
+
+def FlatAtomicOptionalOpsMatchClass : AsmOperandClass {
+  let Name = "FlatAtomicOptionalOps";
+  let PredicateMethod = "isImm";
+  let ParserMethod = "parseFlatAtomicOptionalOps";
+  let RenderMethod = "addImmOperands";
+}
+
 class GLCBaseMatchClass <string parser> : AsmOperandClass {
   let Name = "GLC"#parser;
   let PredicateMethod = "isImm";
   let ParserMethod = parser;
   let RenderMethod = "addImmOperands";
 }
 
 def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">;
-def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">;
 
 class SLCBaseMatchClass <string parser> : AsmOperandClass {
   let Name = "SLC"#parser;
   let PredicateMethod = "isImm";
   let ParserMethod = parser;
   let RenderMethod = "addImmOperands";
 }
 
 def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">;
-def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">;
-def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">;
 
 class TFEBaseMatchClass <string parser> : AsmOperandClass {
   let Name = "TFE"#parser;
   let PredicateMethod = "isImm";
   let ParserMethod = parser;
   let RenderMethod = "addImmOperands";
 }
 
 def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">;
-def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">;
-def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">;
 
 def OModMatchClass : AsmOperandClass {
   let Name = "OMod";
   let PredicateMethod = "isImm";
   let ParserMethod = "parseVOP3OptionalOps";
   let RenderMethod = "addImmOperands";
 }
 

 def gds01 : gds_base <GDS01MatchClass>;
 
 class glc_base <AsmOperandClass mc> : Operand <i1> {
   let PrintMethod = "printGLC";
   let ParserMatchClass = mc;
 }
 
 def glc : glc_base <GLCMubufMatchClass>;
-def glc_flat : glc_base <GLCFlatMatchClass>;
+def glc_flat : glc_base <FlatOptionalOpsMatchClass>;
 
 class slc_base <AsmOperandClass mc> : Operand <i1> {
   let PrintMethod = "printSLC";
   let ParserMatchClass = mc;
 }
 
 def slc : slc_base <SLCMubufMatchClass>;
-def slc_flat : slc_base <SLCFlatMatchClass>;
-def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>;
+def slc_flat : slc_base <FlatOptionalOpsMatchClass>;
+def slc_flat_atomic : slc_base <FlatAtomicOptionalOpsMatchClass>;
 
 class tfe_base <AsmOperandClass mc> : Operand <i1> {
   let PrintMethod = "printTFE";
   let ParserMatchClass = mc;
 }
 
 def tfe : tfe_base <TFEMubufMatchClass>;
-def tfe_flat : tfe_base <TFEFlatMatchClass>;
-def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>;
+def tfe_flat : tfe_base <FlatOptionalOpsMatchClass>;
+def tfe_flat_atomic : tfe_base <FlatAtomicOptionalOpsMatchClass>;
 
 def omod : Operand <i32> {
   let PrintMethod = "printOModSI";
   let ParserMatchClass = OModMatchClass;
 }
 
 def ClampMod : Operand <i1> {
   let PrintMethod = "printClampSI";