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Differential D15745

[mips] added support for trunc macro
ClosedPublic

Authored by obucina on Dec 23 2015, 6:32 AM.

Details

Reviewers
dsanders
vkalintiris
zoran.jovanovic
Commits
rGd665a66b0f09: [mips] added support for trunc macro
rL261529: [mips] added support for trunc macro
Summary

Continued from http://reviews.llvm.org/D14874

Diff Detail

Event Timeline

obucina updated this revision to Diff 43530.Dec 23 2015, 6:32 AM
obucina retitled this revision from to [mips] added support for trunc macro.
obucina updated this object.
obucina added reviewers: dsanders, zoran.jovanovic.
Herald added a subscriber: dsanders. · View Herald TranscriptDec 23 2015, 6:32 AM
obucina added a subscriber: llvm-commits.Dec 23 2015, 6:32 AM
dsanders accepted this revision.Feb 10 2016, 1:58 AM
dsanders edited edge metadata.

LGTM with a few nits

lib/Target/Mips/AsmParser/MipsAsmParser.cpp
3087

Shouldn't the `hasShortDelaySlot(Inst.getOpcode())` part be based on the properties of CFC1 rather than Inst? Also, it's not really a delay slot, it's a hazard. hasShortDelaySlot() will always return false for CFC1 and the trunc macros.
I think we should just hard code it to true/false (with a comment explaining why) until we represent hazards in tablegen

3091

Likewise

3096

Likewise

test/MC/Mips/mips64/valid.s
289–290

Indentation

test/MC/Mips/mips64r2/valid.s
315–316

Indentation

test/MC/Mips/mips64r3/valid.s
315–316

Indentation

test/MC/Mips/mips64r5/valid.s
316–317

Indentation

This revision is now accepted and ready to land.Feb 10 2016, 1:58 AM
obucina updated this revision to Diff 47645.Feb 11 2016, 7:23 AM
obucina edited edge metadata.
obucina marked 7 inline comments as done.

Changes according to last feedback

Herald added a reviewer: vkalintiris. · View Herald TranscriptFeb 11 2016, 7:23 AM
Closed by commit rL261529: [mips] added support for trunc macro (authored by zjovanovic). · Explain WhyFeb 22 2016, 8:04 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
50 lines
14 lines
test/
MC/
Mips/
mips1/
25 lines
mips2/
6 lines
mips3/
10 lines
mips32/
6 lines
mips32r2/
6 lines
mips32r3/
6 lines
mips32r5/
6 lines
mips4/
10 lines
mips5/
10 lines
mips64/
10 lines
mips64r2/
10 lines
mips64r3/
10 lines
mips64r5/
10 lines

Diff 47645

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 212 Lines • ▼ Show 20 Lines#include "MipsGenAsmMatcher.inc"
bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, bool expandCondBranches(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
bool expandDiv(MCInst &Inst, SMLoc IDLoc, bool expandDiv(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions, const bool IsMips64, SmallVectorImpl<MCInst> &Instructions, const bool IsMips64,
const bool Signed); const bool Signed);
bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
bool expandUlw(MCInst &Inst, SMLoc IDLoc, bool expandUlw(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
bool expandRotation(MCInst &Inst, SMLoc IDLoc, bool expandRotation(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
▲ Show 20 Lines • Show All 1,817 Lines • ▼ Show 20 Lines case Mips::DSDivMacro:
return expandDiv(Inst, IDLoc, Instructions, true, true) ? MER_Fail return expandDiv(Inst, IDLoc, Instructions, true, true) ? MER_Fail
: MER_Success; : MER_Success;
case Mips::UDivMacro: case Mips::UDivMacro:
return expandDiv(Inst, IDLoc, Instructions, false, false) ? MER_Fail return expandDiv(Inst, IDLoc, Instructions, false, false) ? MER_Fail
: MER_Success; : MER_Success;
case Mips::DUDivMacro: case Mips::DUDivMacro:
return expandDiv(Inst, IDLoc, Instructions, true, false) ? MER_Fail return expandDiv(Inst, IDLoc, Instructions, true, false) ? MER_Fail
: MER_Success; : MER_Success;
case Mips::PseudoTRUNC_W_S:
return expandTrunc(Inst, false, false, IDLoc, Instructions) ? MER_Fail
: MER_Success;
case Mips::PseudoTRUNC_W_D32:
return expandTrunc(Inst, true, false, IDLoc, Instructions) ? MER_Fail
: MER_Success;
case Mips::PseudoTRUNC_W_D:
return expandTrunc(Inst, true, true, IDLoc, Instructions) ? MER_Fail
: MER_Success;
case Mips::Ulh: case Mips::Ulh:
return expandUlh(Inst, true, IDLoc, Instructions) ? MER_Fail : MER_Success; return expandUlh(Inst, true, IDLoc, Instructions) ? MER_Fail : MER_Success;
case Mips::Ulhu: case Mips::Ulhu:
return expandUlh(Inst, false, IDLoc, Instructions) ? MER_Fail : MER_Success; return expandUlh(Inst, false, IDLoc, Instructions) ? MER_Fail : MER_Success;
case Mips::Ulw: case Mips::Ulw:
return expandUlw(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success; return expandUlw(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success;
case Mips::NORImm: case Mips::NORImm:
return expandAliasImmediate(Inst, IDLoc, Instructions) ? MER_Fail return expandAliasImmediate(Inst, IDLoc, Instructions) ? MER_Fail
▲ Show 20 Lines • Show All 987 Lines • ▼ Show 20 Lines else {
emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions); emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions);
emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions); emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions);
emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions); emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions);
} }
emitR(Mips::MFLO, RsReg, IDLoc, Instructions); emitR(Mips::MFLO, RsReg, IDLoc, Instructions);
return false; return false;
} }
bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
assert(Inst.getNumOperands() == 3 && "Invalid operand count");
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
Inst.getOperand(2).isReg() && "Invalid instruction operand.");
unsigned FirstReg = Inst.getOperand(0).getReg();
unsigned SecondReg = Inst.getOperand(1).getReg();
unsigned ThirdReg = Inst.getOperand(2).getReg();
if (hasMips1() && !hasMips2()) {
unsigned ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Instructions);
emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, Instructions);
createNop(false, IDLoc, Instructions);
dsandersUnsubmitted
Done
ReplyInline Actions

Shouldn't the `hasShortDelaySlot(Inst.getOpcode())` part be based on the properties of CFC1 rather than Inst? Also, it's not really a delay slot, it's a hazard. hasShortDelaySlot() will always return false for CFC1 and the trunc macros.
I think we should just hard code it to true/false (with a comment explaining why) until we represent hazards in tablegen

dsanders: Shouldn't the ``hasShortDelaySlot(Inst.getOpcode())`` part be based on the properties of CFC1…
emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, Instructions);
emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, Instructions);
emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, Instructions);
createNop(false, IDLoc, Instructions);
dsandersUnsubmitted
Done
ReplyInline Actions

Likewise

dsanders: Likewise
emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
: Mips::CVT_W_S,
FirstReg, SecondReg, IDLoc, Instructions);
emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, Instructions);
createNop(false, IDLoc, Instructions);
dsandersUnsubmitted
Done
ReplyInline Actions

Likewise

dsanders: Likewise
return false;
}
emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
: Mips::TRUNC_W_S,
FirstReg, SecondReg, IDLoc, Instructions);
return false;
}
bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) { SmallVectorImpl<MCInst> &Instructions) {
if (hasMips32r6() || hasMips64r6()) { if (hasMips32r6() || hasMips64r6()) {
Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
return false; return false;
} }
warnIfNoMacro(IDLoc); warnIfNoMacro(IDLoc);
▲ Show 20 Lines • Show All 3,187 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 545 Lines • ▼ Show 20 Lines
// if n is 1, higher part of src is extracted. // if n is 1, higher part of src is extracted.
class ExtractElementF64Base<RegisterOperand RO> : class ExtractElementF64Base<RegisterOperand RO> :
PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
[(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>; [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
(ins FGR32Opnd:$fs, GPR32Opnd:$rs),
"trunc.w.s\t$fd, $fs, $rs">;
def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
(ins AFGR64Opnd:$fs, GPR32Opnd:$rs),
"trunc.w.d\t$fd, $fs, $rs">,
FGR_32, HARDFLOAT;
def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
(ins FGR64Opnd:$fs, GPR32Opnd:$rs),
"trunc.w.d\t$fd, $fs, $rs">,
FGR_64, HARDFLOAT;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// InstAliases. // InstAliases.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT;
def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

test/MC/Mips/mips1/valid.s

Show First 20 Lines • Show All 118 Lines • ▼ Show 20 Linesa:
swr $s1,-26590($14) swr $s1,-26590($14)
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
.set at
trunc.w.s $f4,$f6,$4
# CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
# CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: ori $1, $4, 3 # encoding: [0x34,0x81,0x00,0x03]
# CHECK: xori $1, $1, 2 # encoding: [0x38,0x21,0x00,0x02]
# CHECK: ctc1 $1, $ra # encoding: [0x44,0xc1,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: cvt.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x24]
# CHECK: ctc1 $4, $ra # encoding: [0x44,0xc4,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
trunc.w.d $f4,$f6,$4
# CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
# CHECK: cfc1 $4, $ra # encoding: [0x44,0x44,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: ori $1, $4, 3 # encoding: [0x34,0x81,0x00,0x03]
# CHECK: xori $1, $1, 2 # encoding: [0x38,0x21,0x00,0x02]
# CHECK: ctc1 $1, $ra # encoding: [0x44,0xc1,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: cvt.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x24]
# CHECK: ctc1 $4, $ra # encoding: [0x44,0xc4,0xf8,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
1: 1:

test/MC/Mips/mips2/valid.s

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
1: 1:

test/MC/Mips/mips3/valid.s

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.l.d $f23,$f23 trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
trunc.l.s $f28,$f31 trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
1: 1:

test/MC/Mips/mips32/valid.s

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
1: 1:

test/MC/Mips/mips32r2/valid.s

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9 wsbh $k1,$9
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
1: 1:

test/MC/Mips/mips32r3/valid.s

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9 wsbh $k1,$9
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
1: 1:

test/MC/Mips/mips32r5/valid.s

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f14 # encoding: [0x46,0x20,0x75,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
wsbh $k1,$9 wsbh $k1,$9
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
1: 1:

test/MC/Mips/mips4/valid.s

Show First 20 Lines • Show All 255 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.l.d $f23,$f23 trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
trunc.l.s $f28,$f31 trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
1: 1:

test/MC/Mips/mips5/valid.s

Show First 20 Lines • Show All 257 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.l.d $f23,$f23 trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
trunc.l.s $f28,$f31 trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
1: 1:

test/MC/Mips/mips64/valid.s

Show First 20 Lines • Show All 276 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.l.d $f23,$f23 trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
trunc.l.s $f28,$f31 trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
dsandersUnsubmitted
Done
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Indentation

dsanders: Indentation
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
1: 1:

test/MC/Mips/mips64r2/valid.s

Show First 20 Lines • Show All 302 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.l.d $f23,$f23 trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
trunc.l.s $f28,$f31 trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
dsandersUnsubmitted
Done
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Indentation

dsanders: Indentation
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9 wsbh $k1,$9
1: 1:

test/MC/Mips/mips64r3/valid.s

Show First 20 Lines • Show All 302 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.l.d $f23,$f23 trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
trunc.l.s $f28,$f31 trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
dsandersUnsubmitted
Done
ReplyInline Actions

Indentation

dsanders: Indentation
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9 wsbh $k1,$9
1: 1:

test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 303 Lines • ▼ Show 20 Linesa:
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059 tlti $14,-21059
tltiu $ra,-5076 tltiu $ra,-5076
tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12,-29647 tnei $12,-29647
trunc.l.d $f23,$f23 trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
trunc.l.s $f28,$f31 trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
trunc.w.s $f28,$f30 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
dsandersUnsubmitted
Done
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Indentation

dsanders: Indentation
xor $s2,$a0,$s8 xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04] xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9 wsbh $k1,$9
1: 1: