[lldb][AArch64] Check SIMD save/restore in SVE SIMD test

[DavidSpickett]

Summary

While doing some refactoring I forgot to carry over the copying in of
SIMD data in normal mode, but no tests failed.

Turns out, it's very easy for us to get the restore wrong because
even if you forget the memcopy, setting the buffer to valid may
just read the data you had before the expression evaluation.

So I've extended the SVE SIMD testing (which includes the plain SIMD mode)
to check expression save/restore. This is the only test that fails
if you forget to do m_fpu_is_valid = true so I take from that, that
prior to this it wasn't tested at all.

As a bonus, we now have coverage of the same thing for SVE and SSVE modes.

[DavidSpickett]

MTE control needs a test too, I'm working on that as its own change.

[DavidSpickett]

Rebase

[omjavaid]

lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c

44

There is subtle difference between write_simd_regs and write_simd_regs_expr.

BTW, cant we avoid another function and just do something like

#define WRITE_SIMD(NUM, I)                                                      \
  asm volatile("MOV v" #NUM ".d[0], %0\n\t"                                     \
               "MOV v" #NUM ".d[1], %0\n\t" ::"r"(NUM + I))

[DavidSpickett]

Single function to set the simd values, that takes a base value.

[DavidSpickett]

lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c

44

Done. I also looked into some kind of for loop to generate the WRITE_SIMD but it ends up more complex and approaching the length of just repeating it anyway.

lldb/test/API/commands/register/register/aarch64_sve_simd_registers/TestSVESIMDRegisters.py

 """
-Test that LLDB correctly reads and writes AArch64 SIMD registers in SVE,
-streaming SVE and normal SIMD modes.
+Test that LLDB correctly reads and writes and restores AArch64 SIMD registers
+in SVE, streaming SVE and normal SIMD modes.
 
 There are a few operating modes and we use different strategies for each:
 * Without SVE, in SIMD mode - read the SIMD regset.
 * With SVE, but SVE is inactive - read the SVE regset, but get SIMD data from it.
 * With SVE, SVE is active - read the SVE regset, use the bottom 128 bits of the
   Z registers.
 * With streaming SVE active - read the SSVE regset, use the bottom 128 bits of
   the Z registers.
def skip_if_needed(self, mode):
 
         if (mode == Mode.SSVE) and not self.isAArch64SME():
             self.skipTest("SSVE registers must be supported.")
 
     def make_simd_value(self, n):
         pad = " ".join(["0x00"] * 7)
         return "{{0x{:02x} {} 0x{:02x} {}}}".format(n, pad, n, pad)
 
+    def check_simd_values(self, value_offset):
+        # These are 128 bit registers, so getting them from the API as unsigned
+        # values doesn't work. Check the command output instead.
+        for i in range(32):
+            self.expect("register read v{}".format(i),
+                substrs=[self.make_simd_value(i+value_offset)])
+
     def sve_simd_registers_impl(self, mode):
         self.skip_if_needed(mode)
 
         self.build(dictionary=self.get_build_flags(mode))
         self.line = line_number("main.c", "// Set a break point here.")
 
         exe = self.getBuildArtifact("a.out")
         self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
 
         lldbutil.run_break_set_by_file_and_line(
             self, "main.c", self.line, num_expected_locations=1
         )
         self.runCmd("run", RUN_SUCCEEDED)
 
         self.expect(
             "thread backtrace",
             STOPPED_DUE_TO_BREAKPOINT,
             substrs=["stop reason = breakpoint 1."],
         )
 
-        # These are 128 bit registers, so getting them from the API as unsigned
-        # values doesn't work. Check the command output instead.
-        for i in range(32):
-            self.expect(
-                "register read v{}".format(i), substrs=[self.make_simd_value(i)]
-            )
+        self.check_simd_values(0)
+        self.runCmd("expression write_simd_regs(1)")
+        self.check_simd_values(0)
 
         # Write a new set of values. The kernel will move the program back to
         # non-streaming mode here.
         for i in range(32):
             self.runCmd(
                 'register write v{} "{}"'.format(i, self.make_simd_value(i + 1))
             )
 
         # Should be visible within lldb.
-        for i in range(32):
-            self.expect(
-                "register read v{}".format(i), substrs=[self.make_simd_value(i + 1)]
-            )
+        self.check_simd_values(1)
 
         # The program should agree with lldb.
         self.expect("continue", substrs=["exited with status = 0"])
 
     @no_debug_info_test
     @skipIf(archs=no_match(["aarch64"]))
     @skipIf(oslist=no_match(["linux"]))
     def test_simd_registers_sve(self):

lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c

 #include <stdint.h>
 #include <sys/prctl.h>
 
-void write_simd_regs() {
+// base is added to each value. If base = 2, then v0 = 2, v1 = 3, etc.
+void write_simd_regs(unsigned base) {
 #define WRITE_SIMD(NUM)                                                        \
   asm volatile("MOV v" #NUM ".d[0], %0\n\t"                                    \
-               "MOV v" #NUM ".d[1], %0\n\t" ::"r"(NUM))
+               "MOV v" #NUM ".d[1], %0\n\t" ::"r"(base + NUM))
 
   WRITE_SIMD(0);
   WRITE_SIMD(1);
   WRITE_SIMD(2);
   WRITE_SIMD(3);
   WRITE_SIMD(4);
   WRITE_SIMD(5);
   WRITE_SIMD(6);
#define WRITE_SIMD(NUM)                                                        \
   WRITE_SIMD(26);
   WRITE_SIMD(27);
   WRITE_SIMD(28);
   WRITE_SIMD(29);
   WRITE_SIMD(30);
   WRITE_SIMD(31);
 }
 
 unsigned verify_simd_regs() {
   uint64_t got_low = 0;
   uint64_t got_high = 0;
   uint64_t target = 0;
 
 #define VERIFY_SIMD(NUM)                                                       \
   do {                                                                         \
     got_low = 0;                                                               \
     got_high = 0;                                                              \

 #ifdef SSVE
   asm volatile("msr  s0_3_c4_c7_3, xzr" /*smstart*/);
 #elif defined SVE
   // Make the non-streaming SVE registers active.
   asm volatile("cpy  z0.b, p0/z, #1\n\t");
 #endif
   // else test plain SIMD access.
 
-  write_simd_regs();
+  write_simd_regs(0);
 
   return verify_simd_regs(); // Set a break point here.
 }