[X86] Special handle for v1i1 during ExtractBitFromMaskVector

[pengfei]

Summary

Fixes #64322

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

17659

Why not put this inside the (!IdxC) if-block above?

[pengfei]

Put into (!IdxC) if-block.

[RKSimon]

LGTM - cheers

llvm/lib/Target/X86/X86ISelLowering.cpp

assert((VecVT.getVectorNumElements() <= 16 || Subtarget.hasBWI()) &&
          "Unexpected vector type in ExtractBitFromMaskVector");
 
   // variable index can't be handled in mask registers,
   // extend vector to VR512/128
   if (!IdxC) {
     unsigned NumElts = VecVT.getVectorNumElements();
     // Extending v8i1/v16i1 to 512-bit get better performance on KNL
     // than extending to 128/256bit.
+    if (NumElts == 1) {
+      if (Subtarget.hasDQI()) {
+        Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,
+                          DAG.getUNDEF(MVT::v8i1), Vec,
+                          DAG.getIntPtrConstant(0, dl));
+        return DAG.getBitcast(MVT::i8, Vec);
+      }
+      Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
+                        DAG.getUNDEF(MVT::v16i1), Vec,
+                        DAG.getIntPtrConstant(0, dl));
+      return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
+                         DAG.getBitcast(MVT::i16, Vec));
+    }
     MVT ExtEltVT = (NumElts <= 8) ? MVT::getIntegerVT(128 / NumElts) : MVT::i8;
     MVT ExtVecVT = MVT::getVectorVT(ExtEltVT, NumElts);
     SDValue Ext = DAG.getNode(ISD::SIGN_EXTEND, dl, ExtVecVT, Vec);
     SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ExtEltVT, Ext, Idx);
     return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
   }
 
   unsigned IdxVal = IdxC->getZExtValue();
   if (IdxVal == 0) // the operation is legal
     return Op;
 
   // Extend to natively supported kshift.
   unsigned NumElems = VecVT.getVectorNumElements();
   MVT WideVecVT = VecVT;
   if ((!Subtarget.hasDQI() && NumElems == 8) || NumElems < 8) {
     WideVecVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
     Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT,
                       DAG.getUNDEF(WideVecVT), Vec,
                       DAG.getIntPtrConstant(0, dl));
   }
 
   // Use kshiftr instruction to move to the lower element.
   Vec = DAG.getNode(X86ISD::KSHIFTR, dl, WideVecVT, Vec,
                     DAG.getTargetConstant(IdxVal, dl, MVT::i8));
 
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
                      DAG.getIntPtrConstant(0, dl));
 }
 
 // Helper to find all the extracted elements from a vector.
 static APInt getExtractedDemandedElts(SDNode *N) {
   MVT VT = N->getSimpleValueType(0);
   unsigned NumElts = VT.getVectorNumElements();

llvm/test/CodeGen/X86/pr64322.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s
+
+@G = global <1 x i1> <i1 true>
+@G.1 = global i1 false
+
+define void @foo(i32 %x) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq G@GOTPCREL(%rip), %rax
+; CHECK-NEXT:    kmovb (%rax), %k0
+; CHECK-NEXT:    kmovd %k0, %eax
+; CHECK-NEXT:    andb $1, %al
+; CHECK-NEXT:    movq G.1@GOTPCREL(%rip), %rcx
+; CHECK-NEXT:    movb %al, (%rcx)
+; CHECK-NEXT:    retq
+  %LGV = load <1 x i1>, ptr @G
+  %E = extractelement <1 x i1> %LGV, i32 %x
+  store i1 %E, ptr @G.1
+  ret void
+}