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Differential D156302

[AMDGPU][GlobalISel] Select G_ICMP with G_SELECT to avoid extra copies
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Authored by mbrkusanin on Jul 26 2023, 1:46 AM.

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foad
arsenm

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mbrkusanin created this revision.Jul 26 2023, 1:46 AM
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mbrkusanin added inline comments.Jul 26 2023, 1:56 AM
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
2076

Not sure if having a check for 'one use' is better or not. More lit tests will have improvements if it is removed but I was able to generate some cases where it was not beneficial.

Harbormaster completed remote builds in B248190: Diff 544259.Jul 26 2023, 6:43 AM
arsenm added inline comments.Jul 26 2023, 7:21 AM
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
2077

you don't know that there isn't an intervening def of SCC between the def and use point, which is the point of the copy. You could check computeRegisterLiveness for SCC, but I don't know if this is a scalable strategy. I think we'd be better off with some kind of general physreg def scheduler such that PeepholeOpt can deal with the copies

arsenm added inline comments.Jul 26 2023, 7:23 AM
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
2077

You'd also have to rely on computeRegisterLiveness only using live-out / backwards liveness. It won't see parent defs if they haven't been selected yet

arsenm requested changes to this revision.Jul 26 2023, 10:16 AM
This revision now requires changes to proceed.Jul 26 2023, 10:16 AM

Revision Contents

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llvm/
lib/
Target/
AMDGPU/
33 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
52 lines
838 lines
862 lines
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42 lines
8 lines
6 lines
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Diff 544259

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 2,059 Lines • ▼ Show 20 Linesbool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
Register DstReg = I.getOperand(0).getReg(); Register DstReg = I.getOperand(0).getReg();
unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
assert(Size <= 32 || Size == 64); assert(Size <= 32 || Size == 64);
const MachineOperand &CCOp = I.getOperand(1); const MachineOperand &CCOp = I.getOperand(1);
Register CCReg = CCOp.getReg(); Register CCReg = CCOp.getReg();
if (!isVCC(CCReg, *MRI)) { if (!isVCC(CCReg, *MRI)) {
unsigned SelectOpcode = Size == 64 ? AMDGPU::S_CSELECT_B64 : unsigned SelectOpcode = Size == 64 ? AMDGPU::S_CSELECT_B64 :
AMDGPU::S_CSELECT_B32; AMDGPU::S_CSELECT_B32;
MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
bool Ret = false;
MachineInstr *CopySCC = nullptr;
MachineInstr *CCDef = MRI->getVRegDef(CCReg);
// Try to localize def of SCC and avoid generating extra SCC -> SGPR -> SCC
// copies.
if (CCDef && CCDef->getOpcode() == TargetOpcode::G_ICMP &&
MRI->hasOneNonDBGUse(CCReg)) {
mbrkusaninAuthorUnsubmitted
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Not sure if having a check for 'one use' is better or not. More lit tests will have improvements if it is removed but I was able to generate some cases where it was not beneficial.

mbrkusanin: Not sure if having a check for 'one use' is better or not. More lit tests will have…
Register SrcReg = CCDef->getOperand(2).getReg();
arsenmUnsubmitted
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you don't know that there isn't an intervening def of SCC between the def and use point, which is the point of the copy. You could check computeRegisterLiveness for SCC, but I don't know if this is a scalable strategy. I think we'd be better off with some kind of general physreg def scheduler such that PeepholeOpt can deal with the copies

arsenm: you don't know that there isn't an intervening def of SCC between the def and use point, which…
arsenmUnsubmitted
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You'd also have to rely on computeRegisterLiveness only using live-out / backwards liveness. It won't see parent defs if they haven't been selected yet

arsenm: You'd also have to rely on computeRegisterLiveness only using live-out / backwards liveness. It…
unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI);
auto Pred = (CmpInst::Predicate)CCDef->getOperand(1).getPredicate();
int Opcode = getS_CMPOpcode(Pred, Size);
if (Opcode == -1)
return false;
MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode))
.add(CCDef->getOperand(2))
.add(CCDef->getOperand(3));
Ret |= constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) &&
RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);
} else {
CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
.addReg(CCReg); .addReg(CCReg);
}
// The generic constrainSelectedInstRegOperands doesn't work for the scc register // The generic constrainSelectedInstRegOperands doesn't work for the scc register
// bank, because it does not cover the register class that we used to represent // bank, because it does not cover the register class that we used to represent
// for it. So we need to manually set the register class here. // for it. So we need to manually set the register class here.
if (!MRI->getRegClassOrNull(CCReg)) if (!MRI->getRegClassOrNull(CCReg))
MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI));
MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg) MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg)
.add(I.getOperand(2)) .add(I.getOperand(2))
.add(I.getOperand(3)); .add(I.getOperand(3));
bool Ret = false;
Ret |= constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); Ret |= constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
if (CopySCC)
Ret |= constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI); Ret |= constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI);
I.eraseFromParent(); I.eraseFromParent();
return Ret; return Ret;
} }
// Wide VGPR select should have been split in RegBankSelect. // Wide VGPR select should have been split in RegBankSelect.
if (Size > 32) if (Size > 32)
return false; return false;
▲ Show 20 Lines • Show All 2,987 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

Show First 20 Lines • Show All 1,829 Lines • ▼ Show 20 Lines; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = ashr i65 %value, 33 %result = ashr i65 %value, 33
ret i65 %result ret i65 %result
} }
define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) { define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
; GCN-LABEL: s_ashr_i65: ; GCN-LABEL: s_ashr_i65:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000 ; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
; GCN-NEXT: s_sub_i32 s10, s3, 64 ; GCN-NEXT: s_sub_i32 s2, s3, 64
; GCN-NEXT: s_sub_i32 s8, 64, s3 ; GCN-NEXT: s_sub_i32 s10, 64, s3
; GCN-NEXT: s_cmp_lt_u32 s3, 64 ; GCN-NEXT: s_cmp_lt_u32 s3, 64
; GCN-NEXT: s_cselect_b32 s11, 1, 0
; GCN-NEXT: s_cmp_eq_u32 s3, 0
; GCN-NEXT: s_cselect_b32 s12, 1, 0 ; GCN-NEXT: s_cselect_b32 s12, 1, 0
; GCN-NEXT: s_lshr_b64 s[8:9], s[0:1], s3
; GCN-NEXT: s_lshl_b64 s[10:11], s[4:5], s10
; GCN-NEXT: s_ashr_i64 s[6:7], s[4:5], s3 ; GCN-NEXT: s_ashr_i64 s[6:7], s[4:5], s3
; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3 ; GCN-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 ; GCN-NEXT: s_ashr_i32 s10, s5, 31
; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], s2
; GCN-NEXT: s_ashr_i32 s8, s5, 31 ; GCN-NEXT: s_cmp_lg_u32 s12, 0
; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], s10 ; GCN-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
; GCN-NEXT: s_cmp_lg_u32 s11, 0 ; GCN-NEXT: s_cmp_eq_u32 s3, 0
; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] ; GCN-NEXT: s_mov_b32 s11, s10
; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_cmp_lg_u32 s12, 0
; GCN-NEXT: s_mov_b32 s9, s8 ; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], s[10:11]
; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s11, 0
; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], s[8:9]
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_ashr_i65: ; GFX10PLUS-LABEL: s_ashr_i65:
; GFX10PLUS: ; %bb.0: ; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000 ; GFX10PLUS-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
; GFX10PLUS-NEXT: s_sub_i32 s12, s3, 64 ; GFX10PLUS-NEXT: s_sub_i32 s12, s3, 64
; GFX10PLUS-NEXT: s_sub_i32 s8, 64, s3 ; GFX10PLUS-NEXT: s_sub_i32 s2, 64, s3
; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64 ; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64
; GFX10PLUS-NEXT: s_cselect_b32 s13, 1, 0 ; GFX10PLUS-NEXT: s_cselect_b32 s13, 1, 0
; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s3
; GFX10PLUS-NEXT: s_cselect_b32 s14, 1, 0 ; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s2
; GFX10PLUS-NEXT: s_ashr_i64 s[6:7], s[4:5], s3 ; GFX10PLUS-NEXT: s_ashr_i64 s[10:11], s[4:5], s3
; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[0:1], s3 ; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 ; GFX10PLUS-NEXT: s_ashr_i32 s2, s5, 31
; GFX10PLUS-NEXT: s_ashr_i32 s10, s5, 31
; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX10PLUS-NEXT: s_ashr_i64 s[4:5], s[4:5], s12 ; GFX10PLUS-NEXT: s_ashr_i64 s[4:5], s[4:5], s12
; GFX10PLUS-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10PLUS-NEXT: s_cmp_lg_u32 s13, 0
; GFX10PLUS-NEXT: s_mov_b32 s11, s10 ; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] ; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0
; GFX10PLUS-NEXT: s_cmp_lg_u32 s14, 0 ; GFX10PLUS-NEXT: s_mov_b32 s3, s2
; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10PLUS-NEXT: s_cmp_lg_u32 s13, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[6:7], s[10:11] ; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[10:11], s[2:3]
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10PLUS-NEXT: ; return to shader part epilog
%result = ashr i65 %value, %amount %result = ashr i65 %value, %amount
ret i65 %result ret i65 %result
} }
define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) { define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
; GCN-LABEL: s_ashr_i65_33: ; GCN-LABEL: s_ashr_i65_33:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
Show All 31 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,824 Lines • ▼ Show 20 Lines
; GFX6-LABEL: s_fshl_i128: ; GFX6-LABEL: s_fshl_i128:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b64 s[10:11], 0x7f ; GFX6-NEXT: s_mov_b64 s[10:11], 0x7f
; GFX6-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX6-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX6-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] ; GFX6-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX6-NEXT: s_sub_i32 s9, s12, 64 ; GFX6-NEXT: s_sub_i32 s9, s12, 64
; GFX6-NEXT: s_sub_i32 s10, 64, s12 ; GFX6-NEXT: s_sub_i32 s10, 64, s12
; GFX6-NEXT: s_cmp_lt_u32 s12, 64 ; GFX6-NEXT: s_cmp_lt_u32 s12, 64
; GFX6-NEXT: s_cselect_b32 s18, 1, 0 ; GFX6-NEXT: s_cselect_b32 s13, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s12, 0
; GFX6-NEXT: s_cselect_b32 s19, 1, 0
; GFX6-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
; GFX6-NEXT: s_lshr_b64 s[16:17], s[0:1], s10 ; GFX6-NEXT: s_lshr_b64 s[16:17], s[0:1], s10
; GFX6-NEXT: s_lshl_b64 s[12:13], s[2:3], s12 ; GFX6-NEXT: s_lshl_b64 s[18:19], s[2:3], s12
; GFX6-NEXT: s_or_b64 s[12:13], s[16:17], s[12:13] ; GFX6-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
; GFX6-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
; GFX6-NEXT: s_cmp_lg_u32 s18, 0 ; GFX6-NEXT: s_cmp_lg_u32 s13, 0
; GFX6-NEXT: s_cselect_b64 s[14:15], s[14:15], 0 ; GFX6-NEXT: s_cselect_b64 s[14:15], s[14:15], 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1]
; GFX6-NEXT: s_cmp_lg_u32 s19, 0 ; GFX6-NEXT: s_cmp_eq_u32 s12, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX6-NEXT: s_lshr_b64 s[0:1], s[4:5], 1 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX6-NEXT: s_lshl_b32 s5, s6, 31 ; GFX6-NEXT: s_lshl_b32 s5, s6, 31
; GFX6-NEXT: s_mov_b32 s4, s11 ; GFX6-NEXT: s_mov_b32 s4, s11
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] ; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], 1 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
; GFX6-NEXT: s_sub_i32 s12, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, s8, 64
; GFX6-NEXT: s_sub_i32 s10, 64, s8 ; GFX6-NEXT: s_sub_i32 s12, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s13, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b32 s16, 1, 0 ; GFX6-NEXT: s_cselect_b32 s16, 1, 0
; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s8
; GFX6-NEXT: s_lshl_b64 s[12:13], s[4:5], s12
; GFX6-NEXT: s_lshr_b64 s[6:7], s[4:5], s8 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[4:5], s8
; GFX6-NEXT: s_lshr_b64 s[8:9], s[0:1], s8 ; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GFX6-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s9
; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s12
; GFX6-NEXT: s_cmp_lg_u32 s13, 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[10:11], s[4:5]
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX6-NEXT: s_cmp_lg_u32 s13, 0 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[6:7], 0 ; GFX6-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
; GFX6-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1] ; GFX6-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_fshl_i128: ; GFX8-LABEL: s_fshl_i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_mov_b64 s[10:11], 0x7f ; GFX8-NEXT: s_mov_b64 s[10:11], 0x7f
; GFX8-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX8-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX8-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] ; GFX8-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX8-NEXT: s_sub_i32 s9, s12, 64 ; GFX8-NEXT: s_sub_i32 s9, s12, 64
; GFX8-NEXT: s_sub_i32 s10, 64, s12 ; GFX8-NEXT: s_sub_i32 s10, 64, s12
; GFX8-NEXT: s_cmp_lt_u32 s12, 64 ; GFX8-NEXT: s_cmp_lt_u32 s12, 64
; GFX8-NEXT: s_cselect_b32 s18, 1, 0 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s12, 0
; GFX8-NEXT: s_cselect_b32 s19, 1, 0
; GFX8-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
; GFX8-NEXT: s_lshr_b64 s[16:17], s[0:1], s10 ; GFX8-NEXT: s_lshr_b64 s[16:17], s[0:1], s10
; GFX8-NEXT: s_lshl_b64 s[12:13], s[2:3], s12 ; GFX8-NEXT: s_lshl_b64 s[18:19], s[2:3], s12
; GFX8-NEXT: s_or_b64 s[12:13], s[16:17], s[12:13] ; GFX8-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
; GFX8-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 ; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
; GFX8-NEXT: s_cmp_lg_u32 s18, 0 ; GFX8-NEXT: s_cmp_lg_u32 s13, 0
; GFX8-NEXT: s_cselect_b64 s[14:15], s[14:15], 0 ; GFX8-NEXT: s_cselect_b64 s[14:15], s[14:15], 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s19, 0 ; GFX8-NEXT: s_cmp_eq_u32 s12, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX8-NEXT: s_lshr_b64 s[0:1], s[4:5], 1 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX8-NEXT: s_lshl_b32 s5, s6, 31 ; GFX8-NEXT: s_lshl_b32 s5, s6, 31
; GFX8-NEXT: s_mov_b32 s4, s11 ; GFX8-NEXT: s_mov_b32 s4, s11
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] ; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX8-NEXT: s_lshr_b64 s[4:5], s[6:7], 1 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
; GFX8-NEXT: s_sub_i32 s12, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, s8, 64
; GFX8-NEXT: s_sub_i32 s10, 64, s8 ; GFX8-NEXT: s_sub_i32 s12, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s13, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_cselect_b32 s16, 1, 0
; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s8
; GFX8-NEXT: s_lshl_b64 s[12:13], s[4:5], s12
; GFX8-NEXT: s_lshr_b64 s[6:7], s[4:5], s8 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[4:5], s8
; GFX8-NEXT: s_lshr_b64 s[8:9], s[0:1], s8 ; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GFX8-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], s9
; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GFX8-NEXT: s_lshr_b64 s[4:5], s[4:5], s12
; GFX8-NEXT: s_cmp_lg_u32 s13, 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[10:11], s[4:5]
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX8-NEXT: s_cmp_lg_u32 s13, 0 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[6:7], 0 ; GFX8-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
; GFX8-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1] ; GFX8-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_fshl_i128: ; GFX9-LABEL: s_fshl_i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b64 s[10:11], 0x7f ; GFX9-NEXT: s_mov_b64 s[10:11], 0x7f
; GFX9-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX9-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX9-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] ; GFX9-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX9-NEXT: s_sub_i32 s9, s12, 64 ; GFX9-NEXT: s_sub_i32 s9, s12, 64
; GFX9-NEXT: s_sub_i32 s10, 64, s12 ; GFX9-NEXT: s_sub_i32 s10, 64, s12
; GFX9-NEXT: s_cmp_lt_u32 s12, 64 ; GFX9-NEXT: s_cmp_lt_u32 s12, 64
; GFX9-NEXT: s_cselect_b32 s18, 1, 0 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s12, 0
; GFX9-NEXT: s_cselect_b32 s19, 1, 0
; GFX9-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
; GFX9-NEXT: s_lshr_b64 s[16:17], s[0:1], s10 ; GFX9-NEXT: s_lshr_b64 s[16:17], s[0:1], s10
; GFX9-NEXT: s_lshl_b64 s[12:13], s[2:3], s12 ; GFX9-NEXT: s_lshl_b64 s[18:19], s[2:3], s12
; GFX9-NEXT: s_or_b64 s[12:13], s[16:17], s[12:13] ; GFX9-NEXT: s_lshl_b64 s[14:15], s[0:1], s12
; GFX9-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 ; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
; GFX9-NEXT: s_cmp_lg_u32 s18, 0 ; GFX9-NEXT: s_cmp_lg_u32 s13, 0
; GFX9-NEXT: s_cselect_b64 s[14:15], s[14:15], 0 ; GFX9-NEXT: s_cselect_b64 s[14:15], s[14:15], 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[12:13], s[0:1] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1]
; GFX9-NEXT: s_cmp_lg_u32 s19, 0 ; GFX9-NEXT: s_cmp_eq_u32 s12, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 1 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX9-NEXT: s_lshl_b32 s5, s6, 31 ; GFX9-NEXT: s_lshl_b32 s5, s6, 31
; GFX9-NEXT: s_mov_b32 s4, s11 ; GFX9-NEXT: s_mov_b32 s4, s11
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] ; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], 1 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
; GFX9-NEXT: s_sub_i32 s12, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, s8, 64
; GFX9-NEXT: s_sub_i32 s10, 64, s8 ; GFX9-NEXT: s_sub_i32 s12, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s13, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: s_cselect_b32 s16, 1, 0
; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s8
; GFX9-NEXT: s_lshl_b64 s[12:13], s[4:5], s12
; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], s8 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], s8
; GFX9-NEXT: s_lshr_b64 s[8:9], s[0:1], s8 ; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GFX9-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s9
; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s12
; GFX9-NEXT: s_cmp_lg_u32 s13, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[10:11], s[4:5]
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[6:7], 0 ; GFX9-NEXT: s_cselect_b64 s[4:5], s[6:7], 0
; GFX9-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1] ; GFX9-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_fshl_i128: ; GFX10-LABEL: s_fshl_i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b64 s[10:11], 0x7f ; GFX10-NEXT: s_mov_b64 s[10:11], 0x7f
; GFX10-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX10-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX10-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] ; GFX10-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX10-NEXT: s_sub_i32 s9, s12, 64 ; GFX10-NEXT: s_sub_i32 s9, s12, 64
; GFX10-NEXT: s_sub_i32 s10, 64, s12 ; GFX10-NEXT: s_sub_i32 s10, 64, s12
; GFX10-NEXT: s_cmp_lt_u32 s12, 64 ; GFX10-NEXT: s_cmp_lt_u32 s12, 64
; GFX10-NEXT: s_cselect_b32 s18, 1, 0 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s12, 0
; GFX10-NEXT: s_cselect_b32 s19, 1, 0
; GFX10-NEXT: s_lshr_b64 s[14:15], s[0:1], s10 ; GFX10-NEXT: s_lshr_b64 s[14:15], s[0:1], s10
; GFX10-NEXT: s_lshl_b64 s[16:17], s[2:3], s12 ; GFX10-NEXT: s_lshl_b64 s[16:17], s[2:3], s12
; GFX10-NEXT: s_lshl_b64 s[12:13], s[0:1], s12 ; GFX10-NEXT: s_lshl_b64 s[18:19], s[0:1], s12
; GFX10-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GFX10-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
; GFX10-NEXT: s_cmp_lg_u32 s18, 0 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: s_cselect_b64 s[12:13], s[12:13], 0 ; GFX10-NEXT: s_cselect_b64 s[16:17], s[18:19], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s19, 0 ; GFX10-NEXT: s_cmp_eq_u32 s12, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 1 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX10-NEXT: s_lshl_b32 s5, s6, 31 ; GFX10-NEXT: s_lshl_b32 s5, s6, 31
; GFX10-NEXT: s_mov_b32 s4, s11 ; GFX10-NEXT: s_mov_b32 s4, s11
; GFX10-NEXT: s_sub_i32 s14, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, s8, 64
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: s_lshr_b64 s[4:5], s[6:7], 1 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_sub_i32 s10, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: s_cselect_b32 s15, 1, 0 ; GFX10-NEXT: s_cselect_b32 s14, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: s_cselect_b32 s16, 1, 0
; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
; GFX10-NEXT: s_lshl_b64 s[10:11], s[4:5], s9 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[4:5], s10
; GFX10-NEXT: s_lshr_b64 s[8:9], s[4:5], s8 ; GFX10-NEXT: s_lshr_b64 s[12:13], s[4:5], s8
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s14 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s9
; GFX10-NEXT: s_cmp_lg_u32 s15, 0 ; GFX10-NEXT: s_cmp_lg_u32 s14, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: s_cmp_lg_u32 s15, 0 ; GFX10-NEXT: s_cmp_lg_u32 s14, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[8:9], 0 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[12:13], 0
; GFX10-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1] ; GFX10-NEXT: s_or_b64 s[0:1], s[16:17], s[0:1]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_fshl_i128: ; GFX11-LABEL: s_fshl_i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_mov_b64 s[10:11], 0x7f ; GFX11-NEXT: s_mov_b64 s[10:11], 0x7f
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX11-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX11-NEXT: s_and_not1_b64 s[8:9], s[10:11], s[8:9] ; GFX11-NEXT: s_and_not1_b64 s[8:9], s[10:11], s[8:9]
; GFX11-NEXT: s_sub_i32 s9, s12, 64 ; GFX11-NEXT: s_sub_i32 s9, s12, 64
; GFX11-NEXT: s_sub_i32 s10, 64, s12 ; GFX11-NEXT: s_sub_i32 s10, 64, s12
; GFX11-NEXT: s_cmp_lt_u32 s12, 64 ; GFX11-NEXT: s_cmp_lt_u32 s12, 64
; GFX11-NEXT: s_cselect_b32 s18, 1, 0 ; GFX11-NEXT: s_cselect_b32 s13, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s12, 0
; GFX11-NEXT: s_cselect_b32 s19, 1, 0
; GFX11-NEXT: s_lshr_b64 s[14:15], s[0:1], s10 ; GFX11-NEXT: s_lshr_b64 s[14:15], s[0:1], s10
; GFX11-NEXT: s_lshl_b64 s[16:17], s[2:3], s12 ; GFX11-NEXT: s_lshl_b64 s[16:17], s[2:3], s12
; GFX11-NEXT: s_lshl_b64 s[12:13], s[0:1], s12 ; GFX11-NEXT: s_lshl_b64 s[18:19], s[0:1], s12
; GFX11-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GFX11-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
; GFX11-NEXT: s_cmp_lg_u32 s18, 0 ; GFX11-NEXT: s_cmp_lg_u32 s13, 0
; GFX11-NEXT: s_cselect_b64 s[12:13], s[12:13], 0 ; GFX11-NEXT: s_cselect_b64 s[16:17], s[18:19], 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s19, 0 ; GFX11-NEXT: s_cmp_eq_u32 s12, 0
; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX11-NEXT: s_lshr_b64 s[0:1], s[4:5], 1 ; GFX11-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX11-NEXT: s_lshl_b32 s5, s6, 31 ; GFX11-NEXT: s_lshl_b32 s5, s6, 31
; GFX11-NEXT: s_mov_b32 s4, s11 ; GFX11-NEXT: s_mov_b32 s4, s11
; GFX11-NEXT: s_sub_i32 s14, s8, 64 ; GFX11-NEXT: s_sub_i32 s9, s8, 64
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] ; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX11-NEXT: s_lshr_b64 s[4:5], s[6:7], 1 ; GFX11-NEXT: s_lshr_b64 s[4:5], s[6:7], 1
; GFX11-NEXT: s_sub_i32 s9, 64, s8 ; GFX11-NEXT: s_sub_i32 s10, 64, s8
; GFX11-NEXT: s_cmp_lt_u32 s8, 64 ; GFX11-NEXT: s_cmp_lt_u32 s8, 64
; GFX11-NEXT: s_cselect_b32 s15, 1, 0 ; GFX11-NEXT: s_cselect_b32 s14, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: s_cselect_b32 s16, 1, 0
; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 ; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
; GFX11-NEXT: s_lshl_b64 s[10:11], s[4:5], s9 ; GFX11-NEXT: s_lshl_b64 s[10:11], s[4:5], s10
; GFX11-NEXT: s_lshr_b64 s[8:9], s[4:5], s8 ; GFX11-NEXT: s_lshr_b64 s[12:13], s[4:5], s8
; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s14 ; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s9
; GFX11-NEXT: s_cmp_lg_u32 s15, 0 ; GFX11-NEXT: s_cmp_lg_u32 s14, 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5] ; GFX11-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
; GFX11-NEXT: s_cmp_lg_u32 s16, 0 ; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX11-NEXT: s_cmp_lg_u32 s15, 0 ; GFX11-NEXT: s_cmp_lg_u32 s14, 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[8:9], 0 ; GFX11-NEXT: s_cselect_b64 s[4:5], s[12:13], 0
; GFX11-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1] ; GFX11-NEXT: s_or_b64 s[0:1], s[16:17], s[0:1]
; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt) %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result ret i128 %result
} }
define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) { define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX6-LABEL: v_fshl_i128: ; GFX6-LABEL: v_fshl_i128:
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; GFX6-LABEL: v_fshl_i128_svs: ; GFX6-LABEL: v_fshl_i128_svs:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX6-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX6-NEXT: s_sub_i32 s5, s8, 64 ; GFX6-NEXT: s_sub_i32 s5, s8, 64
; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_sub_i32 s9, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s12, 1, 0 ; GFX6-NEXT: s_cselect_b32 s14, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b32 s13, 1, 0
; GFX6-NEXT: s_lshl_b64 s[6:7], s[0:1], s8
; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s9
; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX6-NEXT: s_lshl_b64 s[12:13], s[2:3], s8
; GFX6-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GFX6-NEXT: s_lshl_b64 s[6:7], s[0:1], s8
; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_cmp_lg_u32 s14, 0
; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1]
; GFX6-NEXT: s_cmp_lg_u32 s13, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 1 ; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 1
; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 31, v2 ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 31, v2
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 1 ; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 1
; GFX6-NEXT: s_sub_i32 s2, s4, 64 ; GFX6-NEXT: s_sub_i32 s2, s4, 64
; GFX6-NEXT: s_sub_i32 s3, 64, s4 ; GFX6-NEXT: s_sub_i32 s3, 64, s4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v4
; GFX6-NEXT: s_cmp_lt_u32 s4, 64 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64
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; GFX8-LABEL: v_fshl_i128_svs: ; GFX8-LABEL: v_fshl_i128_svs:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX8-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX8-NEXT: s_sub_i32 s5, s8, 64 ; GFX8-NEXT: s_sub_i32 s5, s8, 64
; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_sub_i32 s9, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: s_cselect_b32 s14, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s13, 1, 0
; GFX8-NEXT: s_lshl_b64 s[6:7], s[0:1], s8
; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s9
; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX8-NEXT: s_lshl_b64 s[12:13], s[2:3], s8
; GFX8-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GFX8-NEXT: s_lshl_b64 s[6:7], s[0:1], s8
; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 ; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX8-NEXT: s_cmp_lg_u32 s12, 0 ; GFX8-NEXT: s_cmp_lg_u32 s14, 0
; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s13, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1] ; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX8-NEXT: v_lshlrev_b32_e32 v4, 31, v2 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 31, v2
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3] ; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX8-NEXT: s_sub_i32 s2, s4, 64 ; GFX8-NEXT: s_sub_i32 s2, s4, 64
; GFX8-NEXT: s_sub_i32 s3, 64, s4 ; GFX8-NEXT: s_sub_i32 s3, 64, s4
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
; GFX8-NEXT: s_cmp_lt_u32 s4, 64 ; GFX8-NEXT: s_cmp_lt_u32 s4, 64
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; GFX9-LABEL: v_fshl_i128_svs: ; GFX9-LABEL: v_fshl_i128_svs:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX9-NEXT: s_sub_i32 s5, s8, 64 ; GFX9-NEXT: s_sub_i32 s5, s8, 64
; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_sub_i32 s9, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s12, 1, 0 ; GFX9-NEXT: s_cselect_b32 s14, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b32 s13, 1, 0
; GFX9-NEXT: s_lshl_b64 s[6:7], s[0:1], s8
; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s9
; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX9-NEXT: s_lshl_b64 s[12:13], s[2:3], s8
; GFX9-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GFX9-NEXT: s_lshl_b64 s[6:7], s[0:1], s8
; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 ; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX9-NEXT: s_cmp_lg_u32 s12, 0 ; GFX9-NEXT: s_cmp_lg_u32 s14, 0
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1] ; GFX9-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1]
; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 31, v1 ; GFX9-NEXT: v_lshl_or_b32 v1, v2, 31, v1
; GFX9-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3] ; GFX9-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX9-NEXT: s_sub_i32 s2, s4, 64 ; GFX9-NEXT: s_sub_i32 s2, s4, 64
; GFX9-NEXT: s_sub_i32 s3, 64, s4 ; GFX9-NEXT: s_sub_i32 s3, 64, s4
; GFX9-NEXT: s_cmp_lt_u32 s4, 64 ; GFX9-NEXT: s_cmp_lt_u32 s4, 64
; GFX9-NEXT: s_cselect_b32 s5, 1, 0 ; GFX9-NEXT: s_cselect_b32 s5, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s4, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0
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; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX10-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX10-NEXT: s_sub_i32 s5, s8, 64 ; GFX10-NEXT: s_sub_i32 s5, s8, 64
; GFX10-NEXT: s_sub_i32 s6, 64, s8 ; GFX10-NEXT: s_sub_i32 s6, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_lshl_or_b32 v1, v2, 31, v1 ; GFX10-NEXT: v_lshl_or_b32 v1, v2, 31, v1
; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: s_cselect_b32 s13, 1, 0
; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s6 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s8 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s8
; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 ; GFX10-NEXT: s_lshl_b64 s[12:13], s[0:1], s8
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0
; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX10-NEXT: s_cselect_b64 s[10:11], s[12:13], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX10-NEXT: s_sub_i32 s0, 64, s4 ; GFX10-NEXT: s_sub_i32 s0, 64, s4
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3]
; GFX10-NEXT: s_sub_i32 s0, s4, 64 ; GFX10-NEXT: s_sub_i32 s0, s4, 64
; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: s_cmp_lt_u32 s4, 64
; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] ; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3]
; GFX10-NEXT: s_cselect_b32 s1, 1, 0 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s4, 0 ; GFX10-NEXT: s_cmp_eq_u32 s4, 0
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: s_cselect_b32 s5, 1, 0 ; GFX10-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-NEXT: s_and_b32 s0, 1, s1 ; GFX10-NEXT: s_and_b32 s0, 1, s1
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_and_b32 s0, 1, s5 ; GFX10-NEXT: s_and_b32 s0, 1, s5
; GFX10-NEXT: s_and_b32 s1, 1, s1 ; GFX10-NEXT: s_and_b32 s1, 1, s1
; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0
; GFX10-NEXT: v_or_b32_e32 v0, s8, v0 ; GFX10-NEXT: v_or_b32_e32 v0, s10, v0
; GFX10-NEXT: v_or_b32_e32 v1, s9, v1 ; GFX10-NEXT: v_or_b32_e32 v1, s11, v1
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v2, s2, v2
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX10-NEXT: v_or_b32_e32 v3, s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshl_i128_svs: ; GFX11-LABEL: v_fshl_i128_svs:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX11-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX11-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1] ; GFX11-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX11-NEXT: s_and_not1_b64 s[4:5], s[6:7], s[4:5] ; GFX11-NEXT: s_and_not1_b64 s[4:5], s[6:7], s[4:5]
; GFX11-NEXT: s_sub_i32 s5, s8, 64 ; GFX11-NEXT: s_sub_i32 s5, s8, 64
; GFX11-NEXT: s_sub_i32 s6, 64, s8 ; GFX11-NEXT: s_sub_i32 s6, 64, s8
; GFX11-NEXT: s_cmp_lt_u32 s8, 64 ; GFX11-NEXT: s_cmp_lt_u32 s8, 64
; GFX11-NEXT: v_lshl_or_b32 v1, v2, 31, v1 ; GFX11-NEXT: v_lshl_or_b32 v1, v2, 31, v1
; GFX11-NEXT: s_cselect_b32 s12, 1, 0 ; GFX11-NEXT: s_cselect_b32 s9, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX11-NEXT: s_cselect_b32 s13, 1, 0
; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s6 ; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], s8 ; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], s8
; GFX11-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 ; GFX11-NEXT: s_lshl_b64 s[12:13], s[0:1], s8
; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s5 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX11-NEXT: s_cmp_lg_u32 s12, 0 ; GFX11-NEXT: s_cmp_lg_u32 s9, 0
; GFX11-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX11-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX11-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX11-NEXT: s_cselect_b64 s[10:11], s[12:13], 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s13, 0 ; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1]
; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX11-NEXT: s_sub_i32 s0, 64, s4 ; GFX11-NEXT: s_sub_i32 s0, 64, s4
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3]
; GFX11-NEXT: s_sub_i32 s0, s4, 64 ; GFX11-NEXT: s_sub_i32 s0, s4, 64
; GFX11-NEXT: s_cmp_lt_u32 s4, 64 ; GFX11-NEXT: s_cmp_lt_u32 s4, 64
; GFX11-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] ; GFX11-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3]
; GFX11-NEXT: s_cselect_b32 s1, 1, 0 ; GFX11-NEXT: s_cselect_b32 s1, 1, 0
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; GFX11-NEXT: v_dual_cndmask_b32 v4, v8, v4 :: v_dual_cndmask_b32 v5, v9, v5 ; GFX11-NEXT: v_dual_cndmask_b32 v4, v8, v4 :: v_dual_cndmask_b32 v5, v9, v5
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 ; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v0, s8, v0 ; GFX11-NEXT: v_or_b32_e32 v0, s10, v0
; GFX11-NEXT: v_or_b32_e32 v1, s9, v1 ; GFX11-NEXT: v_or_b32_e32 v1, s11, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX11-NEXT: v_or_b32_e32 v2, s2, v2
; GFX11-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX11-NEXT: v_or_b32_e32 v3, s3, v3
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt) %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float> %cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result ret <4 x float> %cast.result
} }
define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 inreg %amt) { define amdgpu_ps <4 x float> @v_fshl_i128_vss(i128 %lhs, i128 inreg %rhs, i128 inreg %amt) {
; GFX6-LABEL: v_fshl_i128_vss: ; GFX6-LABEL: v_fshl_i128_vss:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX6-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX6-NEXT: s_sub_i32 s5, s8, 64 ; GFX6-NEXT: s_sub_i32 s5, s8, 64
; GFX6-NEXT: s_sub_i32 s6, 64, s8 ; GFX6-NEXT: s_sub_i32 s6, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s9, 1, 0 ; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b32 s10, 1, 0
; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s6 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s6
; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s8 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s8
; GFX6-NEXT: s_cselect_b32 s10, 1, 0
; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], s8 ; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], s8
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s5 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s5
; GFX6-NEXT: s_and_b32 s5, 1, s9 ; GFX6-NEXT: s_and_b32 s5, 1, s9
; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX6-NEXT: s_and_b32 s5, 1, s10
; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX6-NEXT: s_lshl_b32 s9, s2, 31 ; GFX6-NEXT: s_lshl_b32 s9, s2, 31
; GFX6-NEXT: s_mov_b32 s8, s7 ; GFX6-NEXT: s_mov_b32 s8, s7
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX6-NEXT: s_and_b32 s5, 1, s10
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX6-NEXT: s_sub_i32 s10, s4, 64
; GFX6-NEXT: s_sub_i32 s8, 64, s4
; GFX6-NEXT: s_cmp_lt_u32 s4, 64
; GFX6-NEXT: v_or_b32_e32 v4, v4, v6
; GFX6-NEXT: v_or_b32_e32 v5, v5, v7
; GFX6-NEXT: s_cselect_b32 s11, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s4, 0
; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX6-NEXT: s_sub_i32 s5, s4, 64
; GFX6-NEXT: s_sub_i32 s10, 64, s4
; GFX6-NEXT: s_cmp_lt_u32 s4, 64
; GFX6-NEXT: s_cselect_b32 s12, 1, 0 ; GFX6-NEXT: s_cselect_b32 s12, 1, 0
; GFX6-NEXT: s_lshr_b64 s[8:9], s[0:1], s4
; GFX6-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX6-NEXT: s_lshr_b64 s[6:7], s[2:3], s4 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[2:3], s4
; GFX6-NEXT: s_lshr_b64 s[4:5], s[0:1], s4 ; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX6-NEXT: s_cmp_lg_u32 s11, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3]
; GFX6-NEXT: s_cmp_eq_u32 s4, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX6-NEXT: s_cmp_lg_u32 s11, 0 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GFX6-NEXT: s_cselect_b64 s[2:3], s[6:7], 0
; GFX6-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX6-NEXT: v_or_b32_e32 v0, s0, v6
; GFX6-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX6-NEXT: v_or_b32_e32 v1, s1, v7
; GFX6-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX6-NEXT: v_or_b32_e32 v2, s2, v2
; GFX6-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX6-NEXT: v_or_b32_e32 v3, s3, v3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: v_fshl_i128_vss: ; GFX8-LABEL: v_fshl_i128_vss:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX8-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX8-NEXT: s_sub_i32 s5, s8, 64 ; GFX8-NEXT: s_sub_i32 s5, s8, 64
; GFX8-NEXT: s_sub_i32 s6, 64, s8 ; GFX8-NEXT: s_sub_i32 s6, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s10, 1, 0
; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
; GFX8-NEXT: s_cselect_b32 s10, 1, 0
; GFX8-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] ; GFX8-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
; GFX8-NEXT: s_and_b32 s5, 1, s9 ; GFX8-NEXT: s_and_b32 s5, 1, s9
; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX8-NEXT: s_and_b32 s5, 1, s10
; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX8-NEXT: s_lshl_b32 s9, s2, 31 ; GFX8-NEXT: s_lshl_b32 s9, s2, 31
; GFX8-NEXT: s_mov_b32 s8, s7 ; GFX8-NEXT: s_mov_b32 s8, s7
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX8-NEXT: s_and_b32 s5, 1, s10
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX8-NEXT: s_sub_i32 s10, s4, 64
; GFX8-NEXT: s_sub_i32 s8, 64, s4
; GFX8-NEXT: s_cmp_lt_u32 s4, 64
; GFX8-NEXT: v_or_b32_e32 v4, v4, v6
; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: s_cselect_b32 s11, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s4, 0
; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX8-NEXT: s_sub_i32 s5, s4, 64
; GFX8-NEXT: s_sub_i32 s10, 64, s4
; GFX8-NEXT: s_cmp_lt_u32 s4, 64
; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0
; GFX8-NEXT: s_lshr_b64 s[8:9], s[0:1], s4
; GFX8-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX8-NEXT: s_lshr_b64 s[6:7], s[2:3], s4 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[2:3], s4
; GFX8-NEXT: s_lshr_b64 s[4:5], s[0:1], s4 ; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX8-NEXT: s_cmp_lg_u32 s11, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX8-NEXT: s_cmp_lg_u32 s12, 0 ; GFX8-NEXT: s_cmp_lg_u32 s12, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3]
; GFX8-NEXT: s_cmp_eq_u32 s4, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: s_cmp_lg_u32 s12, 0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX8-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GFX8-NEXT: s_cselect_b64 s[2:3], s[6:7], 0
; GFX8-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX8-NEXT: v_or_b32_e32 v0, s0, v6
; GFX8-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX8-NEXT: v_or_b32_e32 v1, s1, v7
; GFX8-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX8-NEXT: v_or_b32_e32 v2, s2, v2
; GFX8-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX8-NEXT: v_or_b32_e32 v3, s3, v3
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: v_fshl_i128_vss: ; GFX9-LABEL: v_fshl_i128_vss:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX9-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX9-NEXT: s_sub_i32 s5, s8, 64 ; GFX9-NEXT: s_sub_i32 s5, s8, 64
; GFX9-NEXT: s_sub_i32 s6, 64, s8 ; GFX9-NEXT: s_sub_i32 s6, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b32 s10, 1, 0
; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
; GFX9-NEXT: s_cselect_b32 s10, 1, 0
; GFX9-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
; GFX9-NEXT: s_and_b32 s5, 1, s9 ; GFX9-NEXT: s_and_b32 s5, 1, s9
; GFX9-NEXT: v_or_b32_e32 v4, v4, v6
; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX9-NEXT: s_and_b32 s5, 1, s10
; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX9-NEXT: s_lshl_b32 s9, s2, 31 ; GFX9-NEXT: s_lshl_b32 s9, s2, 31
; GFX9-NEXT: s_mov_b32 s8, s7 ; GFX9-NEXT: s_mov_b32 s8, s7
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX9-NEXT: s_and_b32 s5, 1, s10
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX9-NEXT: s_sub_i32 s10, s4, 64
; GFX9-NEXT: s_sub_i32 s8, 64, s4
; GFX9-NEXT: s_cmp_lt_u32 s4, 64
; GFX9-NEXT: v_or_b32_e32 v4, v4, v6
; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: s_cselect_b32 s11, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s4, 0
; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX9-NEXT: s_sub_i32 s5, s4, 64
; GFX9-NEXT: s_sub_i32 s10, 64, s4
; GFX9-NEXT: s_cmp_lt_u32 s4, 64
; GFX9-NEXT: s_cselect_b32 s12, 1, 0 ; GFX9-NEXT: s_cselect_b32 s12, 1, 0
; GFX9-NEXT: s_lshr_b64 s[8:9], s[0:1], s4
; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX9-NEXT: s_lshr_b64 s[6:7], s[2:3], s4 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[2:3], s4
; GFX9-NEXT: s_lshr_b64 s[4:5], s[0:1], s4 ; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX9-NEXT: s_cmp_lg_u32 s11, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX9-NEXT: s_cmp_lg_u32 s12, 0 ; GFX9-NEXT: s_cmp_lg_u32 s12, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[8:9], s[2:3]
; GFX9-NEXT: s_cmp_eq_u32 s4, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX9-NEXT: s_cmp_lg_u32 s11, 0 ; GFX9-NEXT: s_cmp_lg_u32 s12, 0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX9-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GFX9-NEXT: s_cselect_b64 s[2:3], s[6:7], 0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX9-NEXT: v_or_b32_e32 v0, s0, v6
; GFX9-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX9-NEXT: v_or_b32_e32 v1, s1, v7
; GFX9-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX9-NEXT: v_or_b32_e32 v2, s2, v2
; GFX9-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX9-NEXT: v_or_b32_e32 v3, s3, v3
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: v_fshl_i128_vss: ; GFX10-LABEL: v_fshl_i128_vss:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX10-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX10-NEXT: s_sub_i32 s5, s8, 64
; GFX10-NEXT: s_sub_i32 s6, 64, s8 ; GFX10-NEXT: s_sub_i32 s6, 64, s8
; GFX10-NEXT: s_sub_i32 s5, s8, 64
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
; GFX10-NEXT: s_cselect_b32 s9, 1, 0 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1]
; GFX10-NEXT: s_cselect_b32 s10, 1, 0 ; GFX10-NEXT: s_cselect_b32 s10, 1, 0
; GFX10-NEXT: s_and_b32 s6, 1, s9 ; GFX10-NEXT: s_and_b32 s6, 1, s9
; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_lshl_b32 s9, s2, 31 ; GFX10-NEXT: s_lshl_b32 s9, s2, 31
; GFX10-NEXT: s_mov_b32 s8, s7 ; GFX10-NEXT: s_mov_b32 s8, s7
; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7
; GFX10-NEXT: s_and_b32 s5, 1, s10 ; GFX10-NEXT: s_and_b32 s5, 1, s10
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1 ; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_sub_i32 s10, s4, 64 ; GFX10-NEXT: s_sub_i32 s12, s4, 64
; GFX10-NEXT: s_sub_i32 s8, 64, s4 ; GFX10-NEXT: s_sub_i32 s8, 64, s4
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7
; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: s_cmp_lt_u32 s4, 64
; GFX10-NEXT: s_cselect_b32 s11, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s4, 0
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo
; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0
; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s4 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s4
; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; GFX10-NEXT: s_lshr_b64 s[4:5], s[2:3], s4 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[2:3], s4
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s12
; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cmp_eq_u32 s4, 0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX10-NEXT: v_or_b32_e32 v0, s0, v6
; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 ; GFX10-NEXT: s_cselect_b64 s[2:3], s[10:11], 0
; GFX10-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX10-NEXT: v_or_b32_e32 v1, s1, v7
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v2, s2, v2
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX10-NEXT: v_or_b32_e32 v3, s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshl_i128_vss: ; GFX11-LABEL: v_fshl_i128_vss:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_mov_b64 s[6:7], 0x7f ; GFX11-NEXT: s_mov_b64 s[6:7], 0x7f
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX11-NEXT: s_and_not1_b64 s[4:5], s[6:7], s[4:5] ; GFX11-NEXT: s_and_not1_b64 s[4:5], s[6:7], s[4:5]
; GFX11-NEXT: s_sub_i32 s5, s8, 64
; GFX11-NEXT: s_sub_i32 s6, 64, s8 ; GFX11-NEXT: s_sub_i32 s6, 64, s8
; GFX11-NEXT: s_sub_i32 s5, s8, 64
; GFX11-NEXT: s_cmp_lt_u32 s8, 64 ; GFX11-NEXT: s_cmp_lt_u32 s8, 64
; GFX11-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX11-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1]
; GFX11-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3]
; GFX11-NEXT: s_cselect_b32 s9, 1, 0 ; GFX11-NEXT: s_cselect_b32 s9, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s8, 0 ; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1]
; GFX11-NEXT: s_cselect_b32 s10, 1, 0 ; GFX11-NEXT: s_cselect_b32 s10, 1, 0
; GFX11-NEXT: s_and_b32 s6, 1, s9 ; GFX11-NEXT: s_and_b32 s6, 1, s9
; GFX11-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], 1 ; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX11-NEXT: s_lshl_b32 s9, s2, 31 ; GFX11-NEXT: s_lshl_b32 s9, s2, 31
; GFX11-NEXT: s_mov_b32 s8, s7 ; GFX11-NEXT: s_mov_b32 s8, s7
; GFX11-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6
; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-NEXT: s_and_b32 s5, 1, s10 ; GFX11-NEXT: s_and_b32 s5, 1, s10
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] ; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1 ; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX11-NEXT: s_sub_i32 s10, s4, 64 ; GFX11-NEXT: s_sub_i32 s12, s4, 64
; GFX11-NEXT: s_sub_i32 s8, 64, s4 ; GFX11-NEXT: s_sub_i32 s8, 64, s4
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6
; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-NEXT: s_cmp_lt_u32 s4, 64 ; GFX11-NEXT: s_cmp_lt_u32 s4, 64
; GFX11-NEXT: s_cselect_b32 s11, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s4, 0
; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9 ; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9
; GFX11-NEXT: s_cselect_b32 s12, 1, 0 ; GFX11-NEXT: s_cselect_b32 s13, 1, 0
; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s4 ; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s4
; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 ; GFX11-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; GFX11-NEXT: s_lshr_b64 s[4:5], s[2:3], s4 ; GFX11-NEXT: s_lshr_b64 s[10:11], s[2:3], s4
; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s12
; GFX11-NEXT: s_cmp_lg_u32 s11, 0 ; GFX11-NEXT: s_cmp_lg_u32 s13, 0
; GFX11-NEXT: v_dual_cndmask_b32 v2, v0, v2 :: v_dual_cndmask_b32 v3, v1, v3 ; GFX11-NEXT: v_dual_cndmask_b32 v2, v0, v2 :: v_dual_cndmask_b32 v3, v1, v3
; GFX11-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3] ; GFX11-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX11-NEXT: s_cmp_lg_u32 s12, 0 ; GFX11-NEXT: s_cmp_eq_u32 s4, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX11-NEXT: s_cmp_lg_u32 s11, 0 ; GFX11-NEXT: s_cmp_lg_u32 s13, 0
; GFX11-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX11-NEXT: v_or_b32_e32 v0, s0, v6
; GFX11-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 ; GFX11-NEXT: s_cselect_b64 s[2:3], s[10:11], 0
; GFX11-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX11-NEXT: v_or_b32_e32 v1, s1, v7
; GFX11-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX11-NEXT: v_or_b32_e32 v2, s2, v2
; GFX11-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX11-NEXT: v_or_b32_e32 v3, s3, v3
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt) %result = call i128 @llvm.fshl.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float> %cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result ret <4 x float> %cast.result
} }
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GFX6-LABEL: s_fshl_v2i128: ; GFX6-LABEL: s_fshl_v2i128:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b64 s[18:19], 0x7f ; GFX6-NEXT: s_mov_b64 s[18:19], 0x7f
; GFX6-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX6-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX6-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] ; GFX6-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX6-NEXT: s_sub_i32 s17, s22, 64 ; GFX6-NEXT: s_sub_i32 s17, s22, 64
; GFX6-NEXT: s_sub_i32 s23, 64, s22 ; GFX6-NEXT: s_sub_i32 s23, 64, s22
; GFX6-NEXT: s_cmp_lt_u32 s22, 64 ; GFX6-NEXT: s_cmp_lt_u32 s22, 64
; GFX6-NEXT: s_cselect_b32 s28, 1, 0 ; GFX6-NEXT: s_cselect_b32 s30, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s22, 0
; GFX6-NEXT: s_cselect_b32 s29, 1, 0
; GFX6-NEXT: s_lshl_b64 s[24:25], s[0:1], s22
; GFX6-NEXT: s_lshr_b64 s[26:27], s[0:1], s23 ; GFX6-NEXT: s_lshr_b64 s[26:27], s[0:1], s23
; GFX6-NEXT: s_lshl_b64 s[22:23], s[2:3], s22 ; GFX6-NEXT: s_lshl_b64 s[28:29], s[2:3], s22
; GFX6-NEXT: s_or_b64 s[22:23], s[26:27], s[22:23] ; GFX6-NEXT: s_lshl_b64 s[24:25], s[0:1], s22
; GFX6-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29]
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s17 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], s17
; GFX6-NEXT: s_cmp_lg_u32 s28, 0 ; GFX6-NEXT: s_cmp_lg_u32 s30, 0
; GFX6-NEXT: s_cselect_b64 s[24:25], s[24:25], 0 ; GFX6-NEXT: s_cselect_b64 s[24:25], s[24:25], 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[26:27], s[0:1]
; GFX6-NEXT: s_cmp_lg_u32 s29, 0 ; GFX6-NEXT: s_cmp_eq_u32 s22, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX6-NEXT: s_lshr_b64 s[0:1], s[8:9], 1 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
; GFX6-NEXT: s_lshl_b32 s9, s10, 31 ; GFX6-NEXT: s_lshl_b32 s9, s10, 31
; GFX6-NEXT: s_mov_b32 s8, s19 ; GFX6-NEXT: s_mov_b32 s8, s19
; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] ; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX6-NEXT: s_lshr_b64 s[8:9], s[10:11], 1 ; GFX6-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
; GFX6-NEXT: s_sub_i32 s26, s16, 64 ; GFX6-NEXT: s_sub_i32 s17, s16, 64
; GFX6-NEXT: s_sub_i32 s22, 64, s16 ; GFX6-NEXT: s_sub_i32 s26, 64, s16
; GFX6-NEXT: s_cmp_lt_u32 s16, 64 ; GFX6-NEXT: s_cmp_lt_u32 s16, 64
; GFX6-NEXT: s_cselect_b32 s27, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s16, 0
; GFX6-NEXT: s_cselect_b32 s28, 1, 0 ; GFX6-NEXT: s_cselect_b32 s28, 1, 0
; GFX6-NEXT: s_lshr_b64 s[22:23], s[0:1], s16
; GFX6-NEXT: s_lshl_b64 s[26:27], s[8:9], s26
; GFX6-NEXT: s_lshr_b64 s[10:11], s[8:9], s16 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[8:9], s16
; GFX6-NEXT: s_lshr_b64 s[16:17], s[0:1], s16 ; GFX6-NEXT: s_or_b64 s[22:23], s[22:23], s[26:27]
; GFX6-NEXT: s_lshl_b64 s[22:23], s[8:9], s22 ; GFX6-NEXT: s_lshr_b64 s[8:9], s[8:9], s17
; GFX6-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
; GFX6-NEXT: s_lshr_b64 s[8:9], s[8:9], s26
; GFX6-NEXT: s_cmp_lg_u32 s27, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9]
; GFX6-NEXT: s_cmp_lg_u32 s28, 0 ; GFX6-NEXT: s_cmp_lg_u32 s28, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[22:23], s[8:9]
; GFX6-NEXT: s_cmp_eq_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX6-NEXT: s_cmp_lg_u32 s27, 0 ; GFX6-NEXT: s_cmp_lg_u32 s28, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[10:11], 0 ; GFX6-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX6-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX6-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX6-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX6-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX6-NEXT: s_or_b64 s[0:1], s[24:25], s[0:1] ; GFX6-NEXT: s_or_b64 s[0:1], s[24:25], s[0:1]
; GFX6-NEXT: s_sub_i32 s11, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, s8, 64
; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_sub_i32 s11, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s18, 1, 0 ; GFX6-NEXT: s_cselect_b32 s18, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0 ; GFX6-NEXT: s_lshr_b64 s[20:21], s[4:5], s11
; GFX6-NEXT: s_cselect_b32 s22, 1, 0 ; GFX6-NEXT: s_lshl_b64 s[22:23], s[6:7], s8
; GFX6-NEXT: s_lshl_b64 s[16:17], s[4:5], s8 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[4:5], s8
; GFX6-NEXT: s_lshr_b64 s[20:21], s[4:5], s9 ; GFX6-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23]
; GFX6-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
; GFX6-NEXT: s_or_b64 s[8:9], s[20:21], s[8:9]
; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], s11
; GFX6-NEXT: s_cmp_lg_u32 s18, 0 ; GFX6-NEXT: s_cmp_lg_u32 s18, 0
; GFX6-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 ; GFX6-NEXT: s_cselect_b64 s[16:17], s[16:17], 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5] ; GFX6-NEXT: s_cselect_b64 s[4:5], s[20:21], s[4:5]
; GFX6-NEXT: s_cmp_lg_u32 s22, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] ; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX6-NEXT: s_lshr_b64 s[4:5], s[12:13], 1 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
; GFX6-NEXT: s_lshl_b32 s9, s14, 31 ; GFX6-NEXT: s_lshl_b32 s9, s14, 31
; GFX6-NEXT: s_mov_b32 s8, s19 ; GFX6-NEXT: s_mov_b32 s8, s19
; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX6-NEXT: s_lshr_b64 s[8:9], s[14:15], 1 ; GFX6-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
; GFX6-NEXT: s_sub_i32 s18, s10, 64 ; GFX6-NEXT: s_sub_i32 s11, s10, 64
; GFX6-NEXT: s_sub_i32 s14, 64, s10 ; GFX6-NEXT: s_sub_i32 s18, 64, s10
; GFX6-NEXT: s_cmp_lt_u32 s10, 64 ; GFX6-NEXT: s_cmp_lt_u32 s10, 64
; GFX6-NEXT: s_cselect_b32 s19, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s10, 0
; GFX6-NEXT: s_cselect_b32 s20, 1, 0 ; GFX6-NEXT: s_cselect_b32 s20, 1, 0
; GFX6-NEXT: s_lshr_b64 s[14:15], s[4:5], s10
; GFX6-NEXT: s_lshl_b64 s[18:19], s[8:9], s18
; GFX6-NEXT: s_lshr_b64 s[12:13], s[8:9], s10 ; GFX6-NEXT: s_lshr_b64 s[12:13], s[8:9], s10
; GFX6-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 ; GFX6-NEXT: s_or_b64 s[14:15], s[14:15], s[18:19]
; GFX6-NEXT: s_lshl_b64 s[14:15], s[8:9], s14 ; GFX6-NEXT: s_lshr_b64 s[8:9], s[8:9], s11
; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GFX6-NEXT: s_lshr_b64 s[8:9], s[8:9], s18
; GFX6-NEXT: s_cmp_lg_u32 s19, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
; GFX6-NEXT: s_cmp_lg_u32 s20, 0 ; GFX6-NEXT: s_cmp_lg_u32 s20, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[14:15], s[8:9]
; GFX6-NEXT: s_cmp_eq_u32 s10, 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] ; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
; GFX6-NEXT: s_cmp_lg_u32 s19, 0 ; GFX6-NEXT: s_cmp_lg_u32 s20, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[12:13], 0 ; GFX6-NEXT: s_cselect_b64 s[8:9], s[12:13], 0
; GFX6-NEXT: s_or_b64 s[4:5], s[16:17], s[4:5] ; GFX6-NEXT: s_or_b64 s[4:5], s[16:17], s[4:5]
; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_fshl_v2i128: ; GFX8-LABEL: s_fshl_v2i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_mov_b64 s[18:19], 0x7f ; GFX8-NEXT: s_mov_b64 s[18:19], 0x7f
; GFX8-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX8-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX8-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] ; GFX8-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX8-NEXT: s_sub_i32 s17, s22, 64 ; GFX8-NEXT: s_sub_i32 s17, s22, 64
; GFX8-NEXT: s_sub_i32 s23, 64, s22 ; GFX8-NEXT: s_sub_i32 s23, 64, s22
; GFX8-NEXT: s_cmp_lt_u32 s22, 64 ; GFX8-NEXT: s_cmp_lt_u32 s22, 64
; GFX8-NEXT: s_cselect_b32 s28, 1, 0 ; GFX8-NEXT: s_cselect_b32 s30, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s22, 0
; GFX8-NEXT: s_cselect_b32 s29, 1, 0
; GFX8-NEXT: s_lshl_b64 s[24:25], s[0:1], s22
; GFX8-NEXT: s_lshr_b64 s[26:27], s[0:1], s23 ; GFX8-NEXT: s_lshr_b64 s[26:27], s[0:1], s23
; GFX8-NEXT: s_lshl_b64 s[22:23], s[2:3], s22 ; GFX8-NEXT: s_lshl_b64 s[28:29], s[2:3], s22
; GFX8-NEXT: s_or_b64 s[22:23], s[26:27], s[22:23] ; GFX8-NEXT: s_lshl_b64 s[24:25], s[0:1], s22
; GFX8-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29]
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s17 ; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], s17
; GFX8-NEXT: s_cmp_lg_u32 s28, 0 ; GFX8-NEXT: s_cmp_lg_u32 s30, 0
; GFX8-NEXT: s_cselect_b64 s[24:25], s[24:25], 0 ; GFX8-NEXT: s_cselect_b64 s[24:25], s[24:25], 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[26:27], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s29, 0 ; GFX8-NEXT: s_cmp_eq_u32 s22, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX8-NEXT: s_lshr_b64 s[0:1], s[8:9], 1 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
; GFX8-NEXT: s_lshl_b32 s9, s10, 31 ; GFX8-NEXT: s_lshl_b32 s9, s10, 31
; GFX8-NEXT: s_mov_b32 s8, s19 ; GFX8-NEXT: s_mov_b32 s8, s19
; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] ; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_lshr_b64 s[8:9], s[10:11], 1 ; GFX8-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
; GFX8-NEXT: s_sub_i32 s26, s16, 64 ; GFX8-NEXT: s_sub_i32 s17, s16, 64
; GFX8-NEXT: s_sub_i32 s22, 64, s16 ; GFX8-NEXT: s_sub_i32 s26, 64, s16
; GFX8-NEXT: s_cmp_lt_u32 s16, 64 ; GFX8-NEXT: s_cmp_lt_u32 s16, 64
; GFX8-NEXT: s_cselect_b32 s27, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s16, 0
; GFX8-NEXT: s_cselect_b32 s28, 1, 0 ; GFX8-NEXT: s_cselect_b32 s28, 1, 0
; GFX8-NEXT: s_lshr_b64 s[22:23], s[0:1], s16
; GFX8-NEXT: s_lshl_b64 s[26:27], s[8:9], s26
; GFX8-NEXT: s_lshr_b64 s[10:11], s[8:9], s16 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[8:9], s16
; GFX8-NEXT: s_lshr_b64 s[16:17], s[0:1], s16 ; GFX8-NEXT: s_or_b64 s[22:23], s[22:23], s[26:27]
; GFX8-NEXT: s_lshl_b64 s[22:23], s[8:9], s22 ; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], s17
; GFX8-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], s26
; GFX8-NEXT: s_cmp_lg_u32 s27, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9]
; GFX8-NEXT: s_cmp_lg_u32 s28, 0 ; GFX8-NEXT: s_cmp_lg_u32 s28, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[22:23], s[8:9]
; GFX8-NEXT: s_cmp_eq_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX8-NEXT: s_cmp_lg_u32 s27, 0 ; GFX8-NEXT: s_cmp_lg_u32 s28, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[10:11], 0 ; GFX8-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX8-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX8-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX8-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX8-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX8-NEXT: s_or_b64 s[0:1], s[24:25], s[0:1] ; GFX8-NEXT: s_or_b64 s[0:1], s[24:25], s[0:1]
; GFX8-NEXT: s_sub_i32 s11, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, s8, 64
; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_sub_i32 s11, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s18, 1, 0 ; GFX8-NEXT: s_cselect_b32 s18, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0 ; GFX8-NEXT: s_lshr_b64 s[20:21], s[4:5], s11
; GFX8-NEXT: s_cselect_b32 s22, 1, 0 ; GFX8-NEXT: s_lshl_b64 s[22:23], s[6:7], s8
; GFX8-NEXT: s_lshl_b64 s[16:17], s[4:5], s8 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[4:5], s8
; GFX8-NEXT: s_lshr_b64 s[20:21], s[4:5], s9 ; GFX8-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23]
; GFX8-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 ; GFX8-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
; GFX8-NEXT: s_or_b64 s[8:9], s[20:21], s[8:9]
; GFX8-NEXT: s_lshl_b64 s[4:5], s[4:5], s11
; GFX8-NEXT: s_cmp_lg_u32 s18, 0 ; GFX8-NEXT: s_cmp_lg_u32 s18, 0
; GFX8-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 ; GFX8-NEXT: s_cselect_b64 s[16:17], s[16:17], 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5] ; GFX8-NEXT: s_cselect_b64 s[4:5], s[20:21], s[4:5]
; GFX8-NEXT: s_cmp_lg_u32 s22, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] ; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX8-NEXT: s_lshr_b64 s[4:5], s[12:13], 1 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
; GFX8-NEXT: s_lshl_b32 s9, s14, 31 ; GFX8-NEXT: s_lshl_b32 s9, s14, 31
; GFX8-NEXT: s_mov_b32 s8, s19 ; GFX8-NEXT: s_mov_b32 s8, s19
; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX8-NEXT: s_lshr_b64 s[8:9], s[14:15], 1 ; GFX8-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
; GFX8-NEXT: s_sub_i32 s18, s10, 64 ; GFX8-NEXT: s_sub_i32 s11, s10, 64
; GFX8-NEXT: s_sub_i32 s14, 64, s10 ; GFX8-NEXT: s_sub_i32 s18, 64, s10
; GFX8-NEXT: s_cmp_lt_u32 s10, 64 ; GFX8-NEXT: s_cmp_lt_u32 s10, 64
; GFX8-NEXT: s_cselect_b32 s19, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s10, 0
; GFX8-NEXT: s_cselect_b32 s20, 1, 0 ; GFX8-NEXT: s_cselect_b32 s20, 1, 0
; GFX8-NEXT: s_lshr_b64 s[14:15], s[4:5], s10
; GFX8-NEXT: s_lshl_b64 s[18:19], s[8:9], s18
; GFX8-NEXT: s_lshr_b64 s[12:13], s[8:9], s10 ; GFX8-NEXT: s_lshr_b64 s[12:13], s[8:9], s10
; GFX8-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 ; GFX8-NEXT: s_or_b64 s[14:15], s[14:15], s[18:19]
; GFX8-NEXT: s_lshl_b64 s[14:15], s[8:9], s14 ; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], s11
; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GFX8-NEXT: s_lshr_b64 s[8:9], s[8:9], s18
; GFX8-NEXT: s_cmp_lg_u32 s19, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
; GFX8-NEXT: s_cmp_lg_u32 s20, 0 ; GFX8-NEXT: s_cmp_lg_u32 s20, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[14:15], s[8:9]
; GFX8-NEXT: s_cmp_eq_u32 s10, 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] ; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
; GFX8-NEXT: s_cmp_lg_u32 s19, 0 ; GFX8-NEXT: s_cmp_lg_u32 s20, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[12:13], 0 ; GFX8-NEXT: s_cselect_b64 s[8:9], s[12:13], 0
; GFX8-NEXT: s_or_b64 s[4:5], s[16:17], s[4:5] ; GFX8-NEXT: s_or_b64 s[4:5], s[16:17], s[4:5]
; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_fshl_v2i128: ; GFX9-LABEL: s_fshl_v2i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b64 s[18:19], 0x7f ; GFX9-NEXT: s_mov_b64 s[18:19], 0x7f
; GFX9-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX9-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX9-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] ; GFX9-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX9-NEXT: s_sub_i32 s17, s22, 64 ; GFX9-NEXT: s_sub_i32 s17, s22, 64
; GFX9-NEXT: s_sub_i32 s23, 64, s22 ; GFX9-NEXT: s_sub_i32 s23, 64, s22
; GFX9-NEXT: s_cmp_lt_u32 s22, 64 ; GFX9-NEXT: s_cmp_lt_u32 s22, 64
; GFX9-NEXT: s_cselect_b32 s28, 1, 0 ; GFX9-NEXT: s_cselect_b32 s30, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s22, 0
; GFX9-NEXT: s_cselect_b32 s29, 1, 0
; GFX9-NEXT: s_lshl_b64 s[24:25], s[0:1], s22
; GFX9-NEXT: s_lshr_b64 s[26:27], s[0:1], s23 ; GFX9-NEXT: s_lshr_b64 s[26:27], s[0:1], s23
; GFX9-NEXT: s_lshl_b64 s[22:23], s[2:3], s22 ; GFX9-NEXT: s_lshl_b64 s[28:29], s[2:3], s22
; GFX9-NEXT: s_or_b64 s[22:23], s[26:27], s[22:23] ; GFX9-NEXT: s_lshl_b64 s[24:25], s[0:1], s22
; GFX9-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29]
; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s17 ; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], s17
; GFX9-NEXT: s_cmp_lg_u32 s28, 0 ; GFX9-NEXT: s_cmp_lg_u32 s30, 0
; GFX9-NEXT: s_cselect_b64 s[24:25], s[24:25], 0 ; GFX9-NEXT: s_cselect_b64 s[24:25], s[24:25], 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[22:23], s[0:1] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[26:27], s[0:1]
; GFX9-NEXT: s_cmp_lg_u32 s29, 0 ; GFX9-NEXT: s_cmp_eq_u32 s22, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX9-NEXT: s_lshr_b64 s[0:1], s[8:9], 1 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
; GFX9-NEXT: s_lshl_b32 s9, s10, 31 ; GFX9-NEXT: s_lshl_b32 s9, s10, 31
; GFX9-NEXT: s_mov_b32 s8, s19 ; GFX9-NEXT: s_mov_b32 s8, s19
; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] ; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX9-NEXT: s_lshr_b64 s[8:9], s[10:11], 1 ; GFX9-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
; GFX9-NEXT: s_sub_i32 s26, s16, 64 ; GFX9-NEXT: s_sub_i32 s17, s16, 64
; GFX9-NEXT: s_sub_i32 s22, 64, s16 ; GFX9-NEXT: s_sub_i32 s26, 64, s16
; GFX9-NEXT: s_cmp_lt_u32 s16, 64 ; GFX9-NEXT: s_cmp_lt_u32 s16, 64
; GFX9-NEXT: s_cselect_b32 s27, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s16, 0
; GFX9-NEXT: s_cselect_b32 s28, 1, 0 ; GFX9-NEXT: s_cselect_b32 s28, 1, 0
; GFX9-NEXT: s_lshr_b64 s[22:23], s[0:1], s16
; GFX9-NEXT: s_lshl_b64 s[26:27], s[8:9], s26
; GFX9-NEXT: s_lshr_b64 s[10:11], s[8:9], s16 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[8:9], s16
; GFX9-NEXT: s_lshr_b64 s[16:17], s[0:1], s16 ; GFX9-NEXT: s_or_b64 s[22:23], s[22:23], s[26:27]
; GFX9-NEXT: s_lshl_b64 s[22:23], s[8:9], s22 ; GFX9-NEXT: s_lshr_b64 s[8:9], s[8:9], s17
; GFX9-NEXT: s_or_b64 s[16:17], s[16:17], s[22:23]
; GFX9-NEXT: s_lshr_b64 s[8:9], s[8:9], s26
; GFX9-NEXT: s_cmp_lg_u32 s27, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9]
; GFX9-NEXT: s_cmp_lg_u32 s28, 0 ; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[22:23], s[8:9]
; GFX9-NEXT: s_cmp_eq_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX9-NEXT: s_cmp_lg_u32 s27, 0 ; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[10:11], 0 ; GFX9-NEXT: s_cselect_b64 s[8:9], s[10:11], 0
; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX9-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX9-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX9-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX9-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX9-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX9-NEXT: s_or_b64 s[0:1], s[24:25], s[0:1] ; GFX9-NEXT: s_or_b64 s[0:1], s[24:25], s[0:1]
; GFX9-NEXT: s_sub_i32 s11, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, s8, 64
; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_sub_i32 s11, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s18, 1, 0 ; GFX9-NEXT: s_cselect_b32 s18, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0 ; GFX9-NEXT: s_lshr_b64 s[20:21], s[4:5], s11
; GFX9-NEXT: s_cselect_b32 s22, 1, 0 ; GFX9-NEXT: s_lshl_b64 s[22:23], s[6:7], s8
; GFX9-NEXT: s_lshl_b64 s[16:17], s[4:5], s8 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[4:5], s8
; GFX9-NEXT: s_lshr_b64 s[20:21], s[4:5], s9 ; GFX9-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23]
; GFX9-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 ; GFX9-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
; GFX9-NEXT: s_or_b64 s[8:9], s[20:21], s[8:9]
; GFX9-NEXT: s_lshl_b64 s[4:5], s[4:5], s11
; GFX9-NEXT: s_cmp_lg_u32 s18, 0 ; GFX9-NEXT: s_cmp_lg_u32 s18, 0
; GFX9-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 ; GFX9-NEXT: s_cselect_b64 s[16:17], s[16:17], 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5] ; GFX9-NEXT: s_cselect_b64 s[4:5], s[20:21], s[4:5]
; GFX9-NEXT: s_cmp_lg_u32 s22, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] ; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX9-NEXT: s_lshr_b64 s[4:5], s[12:13], 1 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
; GFX9-NEXT: s_lshl_b32 s9, s14, 31 ; GFX9-NEXT: s_lshl_b32 s9, s14, 31
; GFX9-NEXT: s_mov_b32 s8, s19 ; GFX9-NEXT: s_mov_b32 s8, s19
; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9] ; GFX9-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX9-NEXT: s_lshr_b64 s[8:9], s[14:15], 1 ; GFX9-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
; GFX9-NEXT: s_sub_i32 s18, s10, 64 ; GFX9-NEXT: s_sub_i32 s11, s10, 64
; GFX9-NEXT: s_sub_i32 s14, 64, s10 ; GFX9-NEXT: s_sub_i32 s18, 64, s10
; GFX9-NEXT: s_cmp_lt_u32 s10, 64 ; GFX9-NEXT: s_cmp_lt_u32 s10, 64
; GFX9-NEXT: s_cselect_b32 s19, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s10, 0
; GFX9-NEXT: s_cselect_b32 s20, 1, 0 ; GFX9-NEXT: s_cselect_b32 s20, 1, 0
; GFX9-NEXT: s_lshr_b64 s[14:15], s[4:5], s10
; GFX9-NEXT: s_lshl_b64 s[18:19], s[8:9], s18
; GFX9-NEXT: s_lshr_b64 s[12:13], s[8:9], s10 ; GFX9-NEXT: s_lshr_b64 s[12:13], s[8:9], s10
; GFX9-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 ; GFX9-NEXT: s_or_b64 s[14:15], s[14:15], s[18:19]
; GFX9-NEXT: s_lshl_b64 s[14:15], s[8:9], s14 ; GFX9-NEXT: s_lshr_b64 s[8:9], s[8:9], s11
; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GFX9-NEXT: s_lshr_b64 s[8:9], s[8:9], s18
; GFX9-NEXT: s_cmp_lg_u32 s19, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
; GFX9-NEXT: s_cmp_lg_u32 s20, 0 ; GFX9-NEXT: s_cmp_lg_u32 s20, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[14:15], s[8:9]
; GFX9-NEXT: s_cmp_eq_u32 s10, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9] ; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
; GFX9-NEXT: s_cmp_lg_u32 s19, 0 ; GFX9-NEXT: s_cmp_lg_u32 s20, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[12:13], 0 ; GFX9-NEXT: s_cselect_b64 s[8:9], s[12:13], 0
; GFX9-NEXT: s_or_b64 s[4:5], s[16:17], s[4:5] ; GFX9-NEXT: s_or_b64 s[4:5], s[16:17], s[4:5]
; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_fshl_v2i128: ; GFX10-LABEL: s_fshl_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b64 s[18:19], 0x7f ; GFX10-NEXT: s_mov_b64 s[18:19], 0x7f
; GFX10-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX10-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX10-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] ; GFX10-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX10-NEXT: s_sub_i32 s17, s22, 64 ; GFX10-NEXT: s_sub_i32 s17, s22, 64
; GFX10-NEXT: s_sub_i32 s23, 64, s22 ; GFX10-NEXT: s_sub_i32 s23, 64, s22
; GFX10-NEXT: s_cmp_lt_u32 s22, 64 ; GFX10-NEXT: s_cmp_lt_u32 s22, 64
; GFX10-NEXT: s_cselect_b32 s28, 1, 0 ; GFX10-NEXT: s_cselect_b32 s30, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s22, 0
; GFX10-NEXT: s_cselect_b32 s29, 1, 0
; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s23 ; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s23
; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], s22 ; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], s22
; GFX10-NEXT: s_lshl_b64 s[22:23], s[0:1], s22 ; GFX10-NEXT: s_lshl_b64 s[28:29], s[0:1], s22
; GFX10-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27] ; GFX10-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s17 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s17
; GFX10-NEXT: s_cmp_lg_u32 s28, 0 ; GFX10-NEXT: s_cmp_lg_u32 s30, 0
; GFX10-NEXT: s_cselect_b64 s[22:23], s[22:23], 0 ; GFX10-NEXT: s_cselect_b64 s[26:27], s[28:29], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s29, 0 ; GFX10-NEXT: s_cmp_eq_u32 s22, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], 1 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
; GFX10-NEXT: s_lshl_b32 s9, s10, 31 ; GFX10-NEXT: s_lshl_b32 s9, s10, 31
; GFX10-NEXT: s_mov_b32 s8, s19 ; GFX10-NEXT: s_mov_b32 s8, s19
; GFX10-NEXT: s_sub_i32 s26, s16, 64 ; GFX10-NEXT: s_sub_i32 s17, s16, 64
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[8:9], s[10:11], 1 ; GFX10-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
; GFX10-NEXT: s_sub_i32 s17, 64, s16 ; GFX10-NEXT: s_sub_i32 s22, 64, s16
; GFX10-NEXT: s_cmp_lt_u32 s16, 64 ; GFX10-NEXT: s_cmp_lt_u32 s16, 64
; GFX10-NEXT: s_cselect_b32 s27, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s16, 0
; GFX10-NEXT: s_cselect_b32 s28, 1, 0 ; GFX10-NEXT: s_cselect_b32 s28, 1, 0
; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s16 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s16
; GFX10-NEXT: s_lshl_b64 s[24:25], s[8:9], s17 ; GFX10-NEXT: s_lshl_b64 s[22:23], s[8:9], s22
; GFX10-NEXT: s_lshr_b64 s[16:17], s[8:9], s16 ; GFX10-NEXT: s_lshr_b64 s[24:25], s[8:9], s16
; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[24:25] ; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[22:23]
; GFX10-NEXT: s_lshr_b64 s[8:9], s[8:9], s26 ; GFX10-NEXT: s_lshr_b64 s[8:9], s[8:9], s17
; GFX10-NEXT: s_cmp_lg_u32 s27, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
; GFX10-NEXT: s_cmp_lg_u32 s28, 0 ; GFX10-NEXT: s_cmp_lg_u32 s28, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
; GFX10-NEXT: s_cmp_eq_u32 s16, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX10-NEXT: s_cmp_lg_u32 s27, 0 ; GFX10-NEXT: s_cmp_lg_u32 s28, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[16:17], 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[24:25], 0
; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX10-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX10-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX10-NEXT: s_or_b64 s[0:1], s[22:23], s[0:1] ; GFX10-NEXT: s_or_b64 s[0:1], s[26:27], s[0:1]
; GFX10-NEXT: s_sub_i32 s11, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, s8, 64
; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_sub_i32 s11, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: s_cselect_b32 s18, 1, 0 ; GFX10-NEXT: s_cselect_b32 s18, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s11
; GFX10-NEXT: s_cselect_b32 s22, 1, 0
; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s9
; GFX10-NEXT: s_lshl_b64 s[20:21], s[6:7], s8 ; GFX10-NEXT: s_lshl_b64 s[20:21], s[6:7], s8
; GFX10-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 ; GFX10-NEXT: s_lshl_b64 s[22:23], s[4:5], s8
; GFX10-NEXT: s_or_b64 s[16:17], s[16:17], s[20:21] ; GFX10-NEXT: s_or_b64 s[16:17], s[16:17], s[20:21]
; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], s11 ; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
; GFX10-NEXT: s_cmp_lg_u32 s18, 0 ; GFX10-NEXT: s_cmp_lg_u32 s18, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX10-NEXT: s_cselect_b64 s[20:21], s[22:23], 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] ; GFX10-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5]
; GFX10-NEXT: s_cmp_lg_u32 s22, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: s_mov_b32 s8, s19
; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] ; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX10-NEXT: s_lshr_b64 s[4:5], s[12:13], 1 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
; GFX10-NEXT: s_lshl_b32 s13, s14, 31 ; GFX10-NEXT: s_lshl_b32 s9, s14, 31
; GFX10-NEXT: s_mov_b32 s12, s19 ; GFX10-NEXT: s_sub_i32 s11, s10, 64
; GFX10-NEXT: s_sub_i32 s18, s10, 64 ; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13] ; GFX10-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
; GFX10-NEXT: s_lshr_b64 s[12:13], s[14:15], 1 ; GFX10-NEXT: s_sub_i32 s14, 64, s10
; GFX10-NEXT: s_sub_i32 s11, 64, s10
; GFX10-NEXT: s_cmp_lt_u32 s10, 64 ; GFX10-NEXT: s_cmp_lt_u32 s10, 64
; GFX10-NEXT: s_cselect_b32 s19, 1, 0 ; GFX10-NEXT: s_cselect_b32 s18, 1, 0
; GFX10-NEXT: s_lshr_b64 s[12:13], s[4:5], s10
; GFX10-NEXT: s_lshl_b64 s[14:15], s[8:9], s14
; GFX10-NEXT: s_lshr_b64 s[16:17], s[8:9], s10
; GFX10-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
; GFX10-NEXT: s_lshr_b64 s[8:9], s[8:9], s11
; GFX10-NEXT: s_cmp_lg_u32 s18, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
; GFX10-NEXT: s_cmp_eq_u32 s10, 0 ; GFX10-NEXT: s_cmp_eq_u32 s10, 0
; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[14:15], s[4:5], s10 ; GFX10-NEXT: s_cmp_lg_u32 s18, 0
; GFX10-NEXT: s_lshl_b64 s[16:17], s[12:13], s11 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
; GFX10-NEXT: s_lshr_b64 s[10:11], s[12:13], s10 ; GFX10-NEXT: s_or_b64 s[4:5], s[20:21], s[4:5]
; GFX10-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[12:13], s[12:13], s18
; GFX10-NEXT: s_cmp_lg_u32 s19, 0
; GFX10-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13]
; GFX10-NEXT: s_cmp_lg_u32 s20, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[12:13]
; GFX10-NEXT: s_cmp_lg_u32 s19, 0
; GFX10-NEXT: s_cselect_b64 s[10:11], s[10:11], 0
; GFX10-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_fshl_v2i128: ; GFX11-LABEL: s_fshl_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_mov_b64 s[18:19], 0x7f ; GFX11-NEXT: s_mov_b64 s[18:19], 0x7f
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX11-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX11-NEXT: s_and_not1_b64 s[16:17], s[18:19], s[16:17] ; GFX11-NEXT: s_and_not1_b64 s[16:17], s[18:19], s[16:17]
; GFX11-NEXT: s_sub_i32 s17, s22, 64 ; GFX11-NEXT: s_sub_i32 s17, s22, 64
; GFX11-NEXT: s_sub_i32 s23, 64, s22 ; GFX11-NEXT: s_sub_i32 s23, 64, s22
; GFX11-NEXT: s_cmp_lt_u32 s22, 64 ; GFX11-NEXT: s_cmp_lt_u32 s22, 64
; GFX11-NEXT: s_cselect_b32 s28, 1, 0 ; GFX11-NEXT: s_cselect_b32 s30, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s22, 0
; GFX11-NEXT: s_cselect_b32 s29, 1, 0
; GFX11-NEXT: s_lshr_b64 s[24:25], s[0:1], s23 ; GFX11-NEXT: s_lshr_b64 s[24:25], s[0:1], s23
; GFX11-NEXT: s_lshl_b64 s[26:27], s[2:3], s22 ; GFX11-NEXT: s_lshl_b64 s[26:27], s[2:3], s22
; GFX11-NEXT: s_lshl_b64 s[22:23], s[0:1], s22 ; GFX11-NEXT: s_lshl_b64 s[28:29], s[0:1], s22
; GFX11-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27] ; GFX11-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s17 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s17
; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_cmp_lg_u32 s30, 0
; GFX11-NEXT: s_cselect_b64 s[22:23], s[22:23], 0 ; GFX11-NEXT: s_cselect_b64 s[26:27], s[28:29], 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s29, 0 ; GFX11-NEXT: s_cmp_eq_u32 s22, 0
; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], 1 ; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
; GFX11-NEXT: s_lshl_b32 s9, s10, 31 ; GFX11-NEXT: s_lshl_b32 s9, s10, 31
; GFX11-NEXT: s_mov_b32 s8, s19 ; GFX11-NEXT: s_mov_b32 s8, s19
; GFX11-NEXT: s_sub_i32 s26, s16, 64 ; GFX11-NEXT: s_sub_i32 s17, s16, 64
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] ; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX11-NEXT: s_lshr_b64 s[8:9], s[10:11], 1 ; GFX11-NEXT: s_lshr_b64 s[8:9], s[10:11], 1
; GFX11-NEXT: s_sub_i32 s17, 64, s16 ; GFX11-NEXT: s_sub_i32 s22, 64, s16
; GFX11-NEXT: s_cmp_lt_u32 s16, 64 ; GFX11-NEXT: s_cmp_lt_u32 s16, 64
; GFX11-NEXT: s_cselect_b32 s27, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s16, 0
; GFX11-NEXT: s_cselect_b32 s28, 1, 0 ; GFX11-NEXT: s_cselect_b32 s28, 1, 0
; GFX11-NEXT: s_lshr_b64 s[10:11], s[0:1], s16 ; GFX11-NEXT: s_lshr_b64 s[10:11], s[0:1], s16
; GFX11-NEXT: s_lshl_b64 s[24:25], s[8:9], s17 ; GFX11-NEXT: s_lshl_b64 s[22:23], s[8:9], s22
; GFX11-NEXT: s_lshr_b64 s[16:17], s[8:9], s16 ; GFX11-NEXT: s_lshr_b64 s[24:25], s[8:9], s16
; GFX11-NEXT: s_or_b64 s[10:11], s[10:11], s[24:25] ; GFX11-NEXT: s_or_b64 s[10:11], s[10:11], s[22:23]
; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s26 ; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s17
; GFX11-NEXT: s_cmp_lg_u32 s27, 0
; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9]
; GFX11-NEXT: s_cmp_eq_u32 s16, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[8:9]
; GFX11-NEXT: s_cmp_lg_u32 s27, 0 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0 ; GFX11-NEXT: s_cselect_b64 s[8:9], s[24:25], 0
; GFX11-NEXT: s_and_not1_b64 s[10:11], s[18:19], s[20:21] ; GFX11-NEXT: s_and_not1_b64 s[10:11], s[18:19], s[20:21]
; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX11-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX11-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX11-NEXT: s_or_b64 s[0:1], s[22:23], s[0:1] ; GFX11-NEXT: s_or_b64 s[0:1], s[26:27], s[0:1]
; GFX11-NEXT: s_sub_i32 s11, s8, 64 ; GFX11-NEXT: s_sub_i32 s9, s8, 64
; GFX11-NEXT: s_sub_i32 s9, 64, s8 ; GFX11-NEXT: s_sub_i32 s11, 64, s8
; GFX11-NEXT: s_cmp_lt_u32 s8, 64 ; GFX11-NEXT: s_cmp_lt_u32 s8, 64
; GFX11-NEXT: s_cselect_b32 s18, 1, 0 ; GFX11-NEXT: s_cselect_b32 s18, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s8, 0 ; GFX11-NEXT: s_lshr_b64 s[16:17], s[4:5], s11
; GFX11-NEXT: s_cselect_b32 s22, 1, 0
; GFX11-NEXT: s_lshr_b64 s[16:17], s[4:5], s9
; GFX11-NEXT: s_lshl_b64 s[20:21], s[6:7], s8 ; GFX11-NEXT: s_lshl_b64 s[20:21], s[6:7], s8
; GFX11-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 ; GFX11-NEXT: s_lshl_b64 s[22:23], s[4:5], s8
; GFX11-NEXT: s_or_b64 s[16:17], s[16:17], s[20:21] ; GFX11-NEXT: s_or_b64 s[16:17], s[16:17], s[20:21]
; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s11 ; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
; GFX11-NEXT: s_cmp_lg_u32 s18, 0 ; GFX11-NEXT: s_cmp_lg_u32 s18, 0
; GFX11-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX11-NEXT: s_cselect_b64 s[20:21], s[22:23], 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] ; GFX11-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5]
; GFX11-NEXT: s_cmp_lg_u32 s22, 0 ; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: s_mov_b32 s8, s19
; GFX11-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] ; GFX11-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX11-NEXT: s_lshr_b64 s[4:5], s[12:13], 1 ; GFX11-NEXT: s_lshr_b64 s[4:5], s[12:13], 1
; GFX11-NEXT: s_lshl_b32 s13, s14, 31 ; GFX11-NEXT: s_lshl_b32 s9, s14, 31
; GFX11-NEXT: s_mov_b32 s12, s19 ; GFX11-NEXT: s_sub_i32 s11, s10, 64
; GFX11-NEXT: s_sub_i32 s18, s10, 64 ; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13] ; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
; GFX11-NEXT: s_lshr_b64 s[12:13], s[14:15], 1 ; GFX11-NEXT: s_sub_i32 s14, 64, s10
; GFX11-NEXT: s_sub_i32 s11, 64, s10
; GFX11-NEXT: s_cmp_lt_u32 s10, 64 ; GFX11-NEXT: s_cmp_lt_u32 s10, 64
; GFX11-NEXT: s_cselect_b32 s19, 1, 0 ; GFX11-NEXT: s_cselect_b32 s18, 1, 0
; GFX11-NEXT: s_lshr_b64 s[12:13], s[4:5], s10
; GFX11-NEXT: s_lshl_b64 s[14:15], s[8:9], s14
; GFX11-NEXT: s_lshr_b64 s[16:17], s[8:9], s10
; GFX11-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15]
; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s11
; GFX11-NEXT: s_cmp_lg_u32 s18, 0
; GFX11-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
; GFX11-NEXT: s_cmp_eq_u32 s10, 0 ; GFX11-NEXT: s_cmp_eq_u32 s10, 0
; GFX11-NEXT: s_cselect_b32 s20, 1, 0 ; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], s[8:9]
; GFX11-NEXT: s_lshr_b64 s[14:15], s[4:5], s10 ; GFX11-NEXT: s_cmp_lg_u32 s18, 0
; GFX11-NEXT: s_lshl_b64 s[16:17], s[12:13], s11 ; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
; GFX11-NEXT: s_lshr_b64 s[10:11], s[12:13], s10 ; GFX11-NEXT: s_or_b64 s[4:5], s[20:21], s[4:5]
; GFX11-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX11-NEXT: s_lshr_b64 s[12:13], s[12:13], s18
; GFX11-NEXT: s_cmp_lg_u32 s19, 0
; GFX11-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13]
; GFX11-NEXT: s_cmp_lg_u32 s20, 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], s[12:13]
; GFX11-NEXT: s_cmp_lg_u32 s19, 0
; GFX11-NEXT: s_cselect_b64 s[10:11], s[10:11], 0
; GFX11-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) %result = call <2 x i128> @llvm.fshl.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result ret <2 x i128> %result
} }
define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) { define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) {
; GFX6-LABEL: v_fshl_v2i128: ; GFX6-LABEL: v_fshl_v2i128:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
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llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

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; GFX6-NEXT: s_movk_i32 s10, 0x7f ; GFX6-NEXT: s_movk_i32 s10, 0x7f
; GFX6-NEXT: s_mov_b32 s11, 0 ; GFX6-NEXT: s_mov_b32 s11, 0
; GFX6-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX6-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX6-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] ; GFX6-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX6-NEXT: s_lshr_b32 s10, s1, 31 ; GFX6-NEXT: s_lshr_b32 s10, s1, 31
; GFX6-NEXT: s_lshl_b64 s[14:15], s[0:1], 1 ; GFX6-NEXT: s_lshl_b64 s[14:15], s[0:1], 1
; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[10:11] ; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[10:11]
; GFX6-NEXT: s_sub_i32 s13, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, s8, 64
; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_sub_i32 s10, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s16, 1, 0 ; GFX6-NEXT: s_cselect_b32 s13, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[14:15], s10
; GFX6-NEXT: s_cselect_b32 s17, 1, 0 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[0:1], s8
; GFX6-NEXT: s_lshl_b64 s[2:3], s[14:15], s8 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[14:15], s8
; GFX6-NEXT: s_lshr_b64 s[10:11], s[14:15], s9 ; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
; GFX6-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 ; GFX6-NEXT: s_lshl_b64 s[14:15], s[14:15], s9
; GFX6-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GFX6-NEXT: s_cmp_lg_u32 s13, 0
; GFX6-NEXT: s_lshl_b64 s[10:11], s[14:15], s13
; GFX6-NEXT: s_cmp_lg_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX6-NEXT: s_cselect_b64 s[10:11], s[10:11], s[14:15]
; GFX6-NEXT: s_cmp_lg_u32 s17, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[0:1], s[8:9] ; GFX6-NEXT: s_cselect_b64 s[8:9], s[0:1], s[10:11]
; GFX6-NEXT: s_sub_i32 s14, s12, 64 ; GFX6-NEXT: s_sub_i32 s13, s12, 64
; GFX6-NEXT: s_sub_i32 s13, 64, s12 ; GFX6-NEXT: s_sub_i32 s14, 64, s12
; GFX6-NEXT: s_cmp_lt_u32 s12, 64 ; GFX6-NEXT: s_cmp_lt_u32 s12, 64
; GFX6-NEXT: s_cselect_b32 s15, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s12, 0
; GFX6-NEXT: s_cselect_b32 s16, 1, 0 ; GFX6-NEXT: s_cselect_b32 s16, 1, 0
; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], s12
; GFX6-NEXT: s_lshr_b64 s[10:11], s[4:5], s12 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[4:5], s12
; GFX6-NEXT: s_lshl_b64 s[12:13], s[6:7], s13 ; GFX6-NEXT: s_lshl_b64 s[14:15], s[6:7], s14
; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] ; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], s12
; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 ; GFX6-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GFX6-NEXT: s_cmp_lg_u32 s15, 0 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[6:7], s13
; GFX6-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7]
; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7]
; GFX6-NEXT: s_cmp_eq_u32 s12, 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] ; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
; GFX6-NEXT: s_cmp_lg_u32 s15, 0 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[6:7], s[0:1], 0 ; GFX6-NEXT: s_cselect_b64 s[6:7], s[0:1], 0
; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] ; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
; GFX6-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7] ; GFX6-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7]
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_fshr_i128: ; GFX8-LABEL: s_fshr_i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_movk_i32 s10, 0x7f ; GFX8-NEXT: s_movk_i32 s10, 0x7f
; GFX8-NEXT: s_mov_b32 s11, 0 ; GFX8-NEXT: s_mov_b32 s11, 0
; GFX8-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX8-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX8-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] ; GFX8-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX8-NEXT: s_lshr_b32 s10, s1, 31 ; GFX8-NEXT: s_lshr_b32 s10, s1, 31
; GFX8-NEXT: s_lshl_b64 s[14:15], s[0:1], 1 ; GFX8-NEXT: s_lshl_b64 s[14:15], s[0:1], 1
; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[10:11] ; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[10:11]
; GFX8-NEXT: s_sub_i32 s13, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, s8, 64
; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_sub_i32 s10, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_cselect_b32 s13, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[14:15], s10
; GFX8-NEXT: s_cselect_b32 s17, 1, 0 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[0:1], s8
; GFX8-NEXT: s_lshl_b64 s[2:3], s[14:15], s8 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[14:15], s8
; GFX8-NEXT: s_lshr_b64 s[10:11], s[14:15], s9 ; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
; GFX8-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 ; GFX8-NEXT: s_lshl_b64 s[14:15], s[14:15], s9
; GFX8-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GFX8-NEXT: s_cmp_lg_u32 s13, 0
; GFX8-NEXT: s_lshl_b64 s[10:11], s[14:15], s13
; GFX8-NEXT: s_cmp_lg_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], s[14:15]
; GFX8-NEXT: s_cmp_lg_u32 s17, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[0:1], s[8:9] ; GFX8-NEXT: s_cselect_b64 s[8:9], s[0:1], s[10:11]
; GFX8-NEXT: s_sub_i32 s14, s12, 64 ; GFX8-NEXT: s_sub_i32 s13, s12, 64
; GFX8-NEXT: s_sub_i32 s13, 64, s12 ; GFX8-NEXT: s_sub_i32 s14, 64, s12
; GFX8-NEXT: s_cmp_lt_u32 s12, 64 ; GFX8-NEXT: s_cmp_lt_u32 s12, 64
; GFX8-NEXT: s_cselect_b32 s15, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s12, 0
; GFX8-NEXT: s_cselect_b32 s16, 1, 0 ; GFX8-NEXT: s_cselect_b32 s16, 1, 0
; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], s12
; GFX8-NEXT: s_lshr_b64 s[10:11], s[4:5], s12 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[4:5], s12
; GFX8-NEXT: s_lshl_b64 s[12:13], s[6:7], s13 ; GFX8-NEXT: s_lshl_b64 s[14:15], s[6:7], s14
; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] ; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], s12
; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 ; GFX8-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GFX8-NEXT: s_cmp_lg_u32 s15, 0 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[6:7], s13
; GFX8-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7]
; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7]
; GFX8-NEXT: s_cmp_eq_u32 s12, 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] ; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
; GFX8-NEXT: s_cmp_lg_u32 s15, 0 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[6:7], s[0:1], 0 ; GFX8-NEXT: s_cselect_b64 s[6:7], s[0:1], 0
; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] ; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
; GFX8-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7] ; GFX8-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7]
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_fshr_i128: ; GFX9-LABEL: s_fshr_i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_movk_i32 s10, 0x7f ; GFX9-NEXT: s_movk_i32 s10, 0x7f
; GFX9-NEXT: s_mov_b32 s11, 0 ; GFX9-NEXT: s_mov_b32 s11, 0
; GFX9-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX9-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX9-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] ; GFX9-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX9-NEXT: s_lshr_b32 s10, s1, 31 ; GFX9-NEXT: s_lshr_b32 s10, s1, 31
; GFX9-NEXT: s_lshl_b64 s[14:15], s[0:1], 1 ; GFX9-NEXT: s_lshl_b64 s[14:15], s[0:1], 1
; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[10:11] ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[10:11]
; GFX9-NEXT: s_sub_i32 s13, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, s8, 64
; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_sub_i32 s10, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: s_cselect_b32 s13, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[14:15], s10
; GFX9-NEXT: s_cselect_b32 s17, 1, 0 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[0:1], s8
; GFX9-NEXT: s_lshl_b64 s[2:3], s[14:15], s8 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[14:15], s8
; GFX9-NEXT: s_lshr_b64 s[10:11], s[14:15], s9 ; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[16:17]
; GFX9-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 ; GFX9-NEXT: s_lshl_b64 s[14:15], s[14:15], s9
; GFX9-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GFX9-NEXT: s_cmp_lg_u32 s13, 0
; GFX9-NEXT: s_lshl_b64 s[10:11], s[14:15], s13
; GFX9-NEXT: s_cmp_lg_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX9-NEXT: s_cselect_b64 s[10:11], s[10:11], s[14:15]
; GFX9-NEXT: s_cmp_lg_u32 s17, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[0:1], s[8:9] ; GFX9-NEXT: s_cselect_b64 s[8:9], s[0:1], s[10:11]
; GFX9-NEXT: s_sub_i32 s14, s12, 64 ; GFX9-NEXT: s_sub_i32 s13, s12, 64
; GFX9-NEXT: s_sub_i32 s13, 64, s12 ; GFX9-NEXT: s_sub_i32 s14, 64, s12
; GFX9-NEXT: s_cmp_lt_u32 s12, 64 ; GFX9-NEXT: s_cmp_lt_u32 s12, 64
; GFX9-NEXT: s_cselect_b32 s15, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s12, 0
; GFX9-NEXT: s_cselect_b32 s16, 1, 0 ; GFX9-NEXT: s_cselect_b32 s16, 1, 0
; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], s12
; GFX9-NEXT: s_lshr_b64 s[10:11], s[4:5], s12 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[4:5], s12
; GFX9-NEXT: s_lshl_b64 s[12:13], s[6:7], s13 ; GFX9-NEXT: s_lshl_b64 s[14:15], s[6:7], s14
; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] ; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], s12
; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 ; GFX9-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GFX9-NEXT: s_cmp_lg_u32 s15, 0 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], s13
; GFX9-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7]
; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7]
; GFX9-NEXT: s_cmp_eq_u32 s12, 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] ; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
; GFX9-NEXT: s_cmp_lg_u32 s15, 0 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[6:7], s[0:1], 0 ; GFX9-NEXT: s_cselect_b64 s[6:7], s[0:1], 0
; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
; GFX9-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7] ; GFX9-NEXT: s_or_b64 s[2:3], s[8:9], s[6:7]
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_fshr_i128: ; GFX10-LABEL: s_fshr_i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_movk_i32 s10, 0x7f ; GFX10-NEXT: s_movk_i32 s10, 0x7f
; GFX10-NEXT: s_mov_b32 s11, 0 ; GFX10-NEXT: s_mov_b32 s11, 0
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX10-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX10-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9] ; GFX10-NEXT: s_andn2_b64 s[8:9], s[10:11], s[8:9]
; GFX10-NEXT: s_lshr_b32 s10, s1, 31 ; GFX10-NEXT: s_lshr_b32 s10, s1, 31
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
; GFX10-NEXT: s_sub_i32 s13, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, s8, 64
; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_sub_i32 s10, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_cselect_b32 s13, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s10
; GFX10-NEXT: s_cselect_b32 s17, 1, 0
; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s9
; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], s8 ; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], s8
; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 ; GFX10-NEXT: s_lshl_b64 s[16:17], s[0:1], s8
; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15] ; GFX10-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s13 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_cmp_lg_u32 s13, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX10-NEXT: s_cselect_b64 s[14:15], s[16:17], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s17, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX10-NEXT: s_sub_i32 s14, s12, 64 ; GFX10-NEXT: s_sub_i32 s13, s12, 64
; GFX10-NEXT: s_sub_i32 s10, 64, s12 ; GFX10-NEXT: s_sub_i32 s8, 64, s12
; GFX10-NEXT: s_cmp_lt_u32 s12, 64 ; GFX10-NEXT: s_cmp_lt_u32 s12, 64
; GFX10-NEXT: s_cselect_b32 s15, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s12, 0
; GFX10-NEXT: s_cselect_b32 s16, 1, 0 ; GFX10-NEXT: s_cselect_b32 s16, 1, 0
; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], s12 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], s12
; GFX10-NEXT: s_lshl_b64 s[10:11], s[6:7], s10 ; GFX10-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
; GFX10-NEXT: s_lshr_b64 s[12:13], s[6:7], s12 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[6:7], s12
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11] ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[6:7], s13
; GFX10-NEXT: s_cmp_lg_u32 s15, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_cmp_lg_u32 s16, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
; GFX10-NEXT: s_cmp_eq_u32 s12, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s15, 0 ; GFX10-NEXT: s_cmp_lg_u32 s16, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[12:13], 0 ; GFX10-NEXT: s_cselect_b64 s[4:5], s[10:11], 0
; GFX10-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GFX10-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_fshr_i128: ; GFX11-LABEL: s_fshr_i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_movk_i32 s10, 0x7f ; GFX11-NEXT: s_movk_i32 s10, 0x7f
; GFX11-NEXT: s_mov_b32 s11, 0 ; GFX11-NEXT: s_mov_b32 s11, 0
; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX11-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11] ; GFX11-NEXT: s_and_b64 s[12:13], s[8:9], s[10:11]
; GFX11-NEXT: s_and_not1_b64 s[8:9], s[10:11], s[8:9] ; GFX11-NEXT: s_and_not1_b64 s[8:9], s[10:11], s[8:9]
; GFX11-NEXT: s_lshr_b32 s10, s1, 31 ; GFX11-NEXT: s_lshr_b32 s10, s1, 31
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11] ; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[10:11]
; GFX11-NEXT: s_sub_i32 s13, s8, 64 ; GFX11-NEXT: s_sub_i32 s9, s8, 64
; GFX11-NEXT: s_sub_i32 s9, 64, s8 ; GFX11-NEXT: s_sub_i32 s10, 64, s8
; GFX11-NEXT: s_cmp_lt_u32 s8, 64 ; GFX11-NEXT: s_cmp_lt_u32 s8, 64
; GFX11-NEXT: s_cselect_b32 s16, 1, 0 ; GFX11-NEXT: s_cselect_b32 s13, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s8, 0 ; GFX11-NEXT: s_lshr_b64 s[10:11], s[0:1], s10
; GFX11-NEXT: s_cselect_b32 s17, 1, 0
; GFX11-NEXT: s_lshr_b64 s[10:11], s[0:1], s9
; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], s8 ; GFX11-NEXT: s_lshl_b64 s[14:15], s[2:3], s8
; GFX11-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 ; GFX11-NEXT: s_lshl_b64 s[16:17], s[0:1], s8
; GFX11-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15] ; GFX11-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s13 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s9
; GFX11-NEXT: s_cmp_lg_u32 s16, 0 ; GFX11-NEXT: s_cmp_lg_u32 s13, 0
; GFX11-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX11-NEXT: s_cselect_b64 s[14:15], s[16:17], 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s17, 0 ; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX11-NEXT: s_sub_i32 s14, s12, 64 ; GFX11-NEXT: s_sub_i32 s13, s12, 64
; GFX11-NEXT: s_sub_i32 s10, 64, s12 ; GFX11-NEXT: s_sub_i32 s8, 64, s12
; GFX11-NEXT: s_cmp_lt_u32 s12, 64 ; GFX11-NEXT: s_cmp_lt_u32 s12, 64
; GFX11-NEXT: s_cselect_b32 s15, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s12, 0
; GFX11-NEXT: s_cselect_b32 s16, 1, 0 ; GFX11-NEXT: s_cselect_b32 s16, 1, 0
; GFX11-NEXT: s_lshr_b64 s[0:1], s[4:5], s12 ; GFX11-NEXT: s_lshr_b64 s[0:1], s[4:5], s12
; GFX11-NEXT: s_lshl_b64 s[10:11], s[6:7], s10 ; GFX11-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
; GFX11-NEXT: s_lshr_b64 s[12:13], s[6:7], s12 ; GFX11-NEXT: s_lshr_b64 s[10:11], s[6:7], s12
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[10:11] ; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s14 ; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s13
; GFX11-NEXT: s_cmp_lg_u32 s15, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
; GFX11-NEXT: s_cmp_lg_u32 s16, 0 ; GFX11-NEXT: s_cmp_lg_u32 s16, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
; GFX11-NEXT: s_cmp_eq_u32 s12, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[4:5], s[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s15, 0 ; GFX11-NEXT: s_cmp_lg_u32 s16, 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[12:13], 0 ; GFX11-NEXT: s_cselect_b64 s[4:5], s[10:11], 0
; GFX11-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GFX11-NEXT: s_or_b64 s[0:1], s[14:15], s[0:1]
; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] ; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt) %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
ret i128 %result ret i128 %result
} }
define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) { define i128 @v_fshr_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX6-LABEL: v_fshr_i128: ; GFX6-LABEL: v_fshr_i128:
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; GFX6-NEXT: s_movk_i32 s6, 0x7f ; GFX6-NEXT: s_movk_i32 s6, 0x7f
; GFX6-NEXT: s_mov_b32 s7, 0 ; GFX6-NEXT: s_mov_b32 s7, 0
; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX6-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX6-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX6-NEXT: s_lshr_b32 s6, s1, 31 ; GFX6-NEXT: s_lshr_b32 s6, s1, 31
; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], 1 ; GFX6-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7] ; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7]
; GFX6-NEXT: s_sub_i32 s9, s4, 64 ; GFX6-NEXT: s_sub_i32 s5, s4, 64
; GFX6-NEXT: s_sub_i32 s5, 64, s4 ; GFX6-NEXT: s_sub_i32 s6, 64, s4
; GFX6-NEXT: s_cmp_lt_u32 s4, 64 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64
; GFX6-NEXT: s_cselect_b32 s12, 1, 0 ; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s4, 0 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], s6
; GFX6-NEXT: s_cselect_b32 s13, 1, 0 ; GFX6-NEXT: s_lshl_b64 s[12:13], s[0:1], s4
; GFX6-NEXT: s_lshl_b64 s[2:3], s[10:11], s4 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[10:11], s4
; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], s5 ; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[12:13]
; GFX6-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 ; GFX6-NEXT: s_lshl_b64 s[10:11], s[10:11], s5
; GFX6-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5] ; GFX6-NEXT: s_cmp_lg_u32 s9, 0
; GFX6-NEXT: s_lshl_b64 s[6:7], s[10:11], s9
; GFX6-NEXT: s_cmp_lg_u32 s12, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX6-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] ; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
; GFX6-NEXT: s_cmp_lg_u32 s13, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
; GFX6-NEXT: s_sub_i32 s4, s8, 64 ; GFX6-NEXT: s_sub_i32 s4, s8, 64
; GFX6-NEXT: s_sub_i32 s5, 64, s8 ; GFX6-NEXT: s_sub_i32 s5, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s6, 1, 0 ; GFX6-NEXT: s_cselect_b32 s6, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s8 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s8
; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5
; GFX6-NEXT: s_cselect_b32 s7, 1, 0 ; GFX6-NEXT: s_cselect_b32 s7, 1, 0
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; GFX8-NEXT: s_movk_i32 s6, 0x7f ; GFX8-NEXT: s_movk_i32 s6, 0x7f
; GFX8-NEXT: s_mov_b32 s7, 0 ; GFX8-NEXT: s_mov_b32 s7, 0
; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX8-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX8-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX8-NEXT: s_lshr_b32 s6, s1, 31 ; GFX8-NEXT: s_lshr_b32 s6, s1, 31
; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], 1 ; GFX8-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7] ; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7]
; GFX8-NEXT: s_sub_i32 s9, s4, 64 ; GFX8-NEXT: s_sub_i32 s5, s4, 64
; GFX8-NEXT: s_sub_i32 s5, 64, s4 ; GFX8-NEXT: s_sub_i32 s6, 64, s4
; GFX8-NEXT: s_cmp_lt_u32 s4, 64 ; GFX8-NEXT: s_cmp_lt_u32 s4, 64
; GFX8-NEXT: s_cselect_b32 s12, 1, 0 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s4, 0 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[10:11], s6
; GFX8-NEXT: s_cselect_b32 s13, 1, 0 ; GFX8-NEXT: s_lshl_b64 s[12:13], s[0:1], s4
; GFX8-NEXT: s_lshl_b64 s[2:3], s[10:11], s4 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[10:11], s4
; GFX8-NEXT: s_lshr_b64 s[6:7], s[10:11], s5 ; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[12:13]
; GFX8-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 ; GFX8-NEXT: s_lshl_b64 s[10:11], s[10:11], s5
; GFX8-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5] ; GFX8-NEXT: s_cmp_lg_u32 s9, 0
; GFX8-NEXT: s_lshl_b64 s[6:7], s[10:11], s9
; GFX8-NEXT: s_cmp_lg_u32 s12, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX8-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] ; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
; GFX8-NEXT: s_cmp_lg_u32 s13, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
; GFX8-NEXT: s_sub_i32 s4, s8, 64 ; GFX8-NEXT: s_sub_i32 s4, s8, 64
; GFX8-NEXT: s_sub_i32 s5, 64, s8 ; GFX8-NEXT: s_sub_i32 s5, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s6, 1, 0 ; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] ; GFX8-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
; GFX8-NEXT: s_cselect_b32 s7, 1, 0 ; GFX8-NEXT: s_cselect_b32 s7, 1, 0
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; GFX9-NEXT: s_movk_i32 s6, 0x7f ; GFX9-NEXT: s_movk_i32 s6, 0x7f
; GFX9-NEXT: s_mov_b32 s7, 0 ; GFX9-NEXT: s_mov_b32 s7, 0
; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX9-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX9-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX9-NEXT: s_lshr_b32 s6, s1, 31 ; GFX9-NEXT: s_lshr_b32 s6, s1, 31
; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], 1 ; GFX9-NEXT: s_lshl_b64 s[10:11], s[0:1], 1
; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7] ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7]
; GFX9-NEXT: s_sub_i32 s9, s4, 64 ; GFX9-NEXT: s_sub_i32 s5, s4, 64
; GFX9-NEXT: s_sub_i32 s5, 64, s4 ; GFX9-NEXT: s_sub_i32 s6, 64, s4
; GFX9-NEXT: s_cmp_lt_u32 s4, 64 ; GFX9-NEXT: s_cmp_lt_u32 s4, 64
; GFX9-NEXT: s_cselect_b32 s12, 1, 0 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s4, 0 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[10:11], s6
; GFX9-NEXT: s_cselect_b32 s13, 1, 0 ; GFX9-NEXT: s_lshl_b64 s[12:13], s[0:1], s4
; GFX9-NEXT: s_lshl_b64 s[2:3], s[10:11], s4 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[10:11], s4
; GFX9-NEXT: s_lshr_b64 s[6:7], s[10:11], s5 ; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[12:13]
; GFX9-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 ; GFX9-NEXT: s_lshl_b64 s[10:11], s[10:11], s5
; GFX9-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5] ; GFX9-NEXT: s_cmp_lg_u32 s9, 0
; GFX9-NEXT: s_lshl_b64 s[6:7], s[10:11], s9
; GFX9-NEXT: s_cmp_lg_u32 s12, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX9-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] ; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], s[10:11]
; GFX9-NEXT: s_cmp_lg_u32 s13, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[6:7]
; GFX9-NEXT: s_sub_i32 s4, s8, 64 ; GFX9-NEXT: s_sub_i32 s4, s8, 64
; GFX9-NEXT: s_sub_i32 s5, 64, s8 ; GFX9-NEXT: s_sub_i32 s5, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s6, 1, 0 ; GFX9-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] ; GFX9-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3]
; GFX9-NEXT: s_cselect_b32 s7, 1, 0 ; GFX9-NEXT: s_cselect_b32 s7, 1, 0
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; GFX10-NEXT: s_movk_i32 s6, 0x7f ; GFX10-NEXT: s_movk_i32 s6, 0x7f
; GFX10-NEXT: s_mov_b32 s7, 0 ; GFX10-NEXT: s_mov_b32 s7, 0
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX10-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] ; GFX10-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5]
; GFX10-NEXT: s_lshr_b32 s6, s1, 31 ; GFX10-NEXT: s_lshr_b32 s6, s1, 31
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX10-NEXT: s_sub_i32 s9, s4, 64 ; GFX10-NEXT: s_sub_i32 s5, s4, 64
; GFX10-NEXT: s_sub_i32 s5, 64, s4 ; GFX10-NEXT: s_sub_i32 s6, 64, s4
; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: s_cmp_lt_u32 s4, 64
; GFX10-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1]
; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s4, 0 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
; GFX10-NEXT: s_cselect_b32 s13, 1, 0
; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s5
; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s4 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s4
; GFX10-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 ; GFX10-NEXT: s_lshl_b64 s[12:13], s[0:1], s4
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], 0 ; GFX10-NEXT: s_cselect_b64 s[10:11], s[12:13], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s13, 0 ; GFX10-NEXT: s_cmp_eq_u32 s4, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX10-NEXT: s_sub_i32 s0, 64, s8 ; GFX10-NEXT: s_sub_i32 s0, 64, s8
; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3]
; GFX10-NEXT: s_sub_i32 s0, s8, 64 ; GFX10-NEXT: s_sub_i32 s0, s8, 64
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] ; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3]
; GFX10-NEXT: s_cselect_b32 s1, 1, 0 ; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_and_b32 s0, 1, s1 ; GFX10-NEXT: s_and_b32 s0, 1, s1
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_and_b32 s0, 1, s6 ; GFX10-NEXT: s_and_b32 s0, 1, s4
; GFX10-NEXT: s_and_b32 s1, 1, s1 ; GFX10-NEXT: s_and_b32 s1, 1, s1
; GFX10-NEXT: v_lshrrev_b64 v[2:3], s8, v[2:3] ; GFX10-NEXT: v_lshrrev_b64 v[2:3], s8, v[2:3]
; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0
; GFX10-NEXT: v_or_b32_e32 v0, s4, v0 ; GFX10-NEXT: v_or_b32_e32 v0, s10, v0
; GFX10-NEXT: v_or_b32_e32 v1, s5, v1 ; GFX10-NEXT: v_or_b32_e32 v1, s11, v1
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v2, s2, v2
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX10-NEXT: v_or_b32_e32 v3, s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshr_i128_svs: ; GFX11-LABEL: v_fshr_i128_svs:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_movk_i32 s6, 0x7f ; GFX11-NEXT: s_movk_i32 s6, 0x7f
; GFX11-NEXT: s_mov_b32 s7, 0 ; GFX11-NEXT: s_mov_b32 s7, 0
; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7] ; GFX11-NEXT: s_and_b64 s[8:9], s[4:5], s[6:7]
; GFX11-NEXT: s_and_not1_b64 s[4:5], s[6:7], s[4:5] ; GFX11-NEXT: s_and_not1_b64 s[4:5], s[6:7], s[4:5]
; GFX11-NEXT: s_lshr_b32 s6, s1, 31 ; GFX11-NEXT: s_lshr_b32 s6, s1, 31
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7] ; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX11-NEXT: s_sub_i32 s9, s4, 64 ; GFX11-NEXT: s_sub_i32 s5, s4, 64
; GFX11-NEXT: s_sub_i32 s5, 64, s4 ; GFX11-NEXT: s_sub_i32 s6, 64, s4
; GFX11-NEXT: s_cmp_lt_u32 s4, 64 ; GFX11-NEXT: s_cmp_lt_u32 s4, 64
; GFX11-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] ; GFX11-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1]
; GFX11-NEXT: s_cselect_b32 s12, 1, 0 ; GFX11-NEXT: s_cselect_b32 s9, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s4, 0 ; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
; GFX11-NEXT: s_cselect_b32 s13, 1, 0
; GFX11-NEXT: s_lshr_b64 s[6:7], s[0:1], s5
; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], s4 ; GFX11-NEXT: s_lshl_b64 s[10:11], s[2:3], s4
; GFX11-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 ; GFX11-NEXT: s_lshl_b64 s[12:13], s[0:1], s4
; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s9 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s5
; GFX11-NEXT: s_cmp_lg_u32 s12, 0 ; GFX11-NEXT: s_cmp_lg_u32 s9, 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], 0 ; GFX11-NEXT: s_cselect_b64 s[10:11], s[12:13], 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[6:7], s[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s13, 0 ; GFX11-NEXT: s_cmp_eq_u32 s4, 0
; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX11-NEXT: s_sub_i32 s0, 64, s8 ; GFX11-NEXT: s_sub_i32 s0, 64, s8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[6:7], s0, v[2:3]
; GFX11-NEXT: s_sub_i32 s0, s8, 64 ; GFX11-NEXT: s_sub_i32 s0, s8, 64
; GFX11-NEXT: s_cmp_lt_u32 s8, 64 ; GFX11-NEXT: s_cmp_lt_u32 s8, 64
; GFX11-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] ; GFX11-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3]
; GFX11-NEXT: s_cselect_b32 s1, 1, 0 ; GFX11-NEXT: s_cselect_b32 s1, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s8, 0 ; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
; GFX11-NEXT: s_cselect_b32 s6, 1, 0 ; GFX11-NEXT: s_cselect_b32 s4, 1, 0
; GFX11-NEXT: s_and_b32 s0, 1, s1 ; GFX11-NEXT: s_and_b32 s0, 1, s1
; GFX11-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX11-NEXT: s_and_b32 s0, 1, s6 ; GFX11-NEXT: s_and_b32 s0, 1, s4
; GFX11-NEXT: s_and_b32 s1, 1, s1 ; GFX11-NEXT: s_and_b32 s1, 1, s1
; GFX11-NEXT: v_lshrrev_b64 v[2:3], s8, v[2:3] ; GFX11-NEXT: v_lshrrev_b64 v[2:3], s8, v[2:3]
; GFX11-NEXT: v_dual_cndmask_b32 v4, v8, v4 :: v_dual_cndmask_b32 v5, v9, v5 ; GFX11-NEXT: v_dual_cndmask_b32 v4, v8, v4 :: v_dual_cndmask_b32 v5, v9, v5
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, s1 ; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v0 :: v_dual_cndmask_b32 v1, v5, v1
; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, v2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, v3, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v0, s4, v0 ; GFX11-NEXT: v_or_b32_e32 v0, s10, v0
; GFX11-NEXT: v_or_b32_e32 v1, s5, v1 ; GFX11-NEXT: v_or_b32_e32 v1, s11, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX11-NEXT: v_or_b32_e32 v2, s2, v2
; GFX11-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX11-NEXT: v_or_b32_e32 v3, s3, v3
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt) %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float> %cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result ret <4 x float> %cast.result
} }
Show All 15 Lines
; GFX6-NEXT: s_cmp_eq_u32 s4, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0
; GFX6-NEXT: s_cselect_b32 s9, 1, 0 ; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s6 ; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s6
; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s4 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s4
; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], s4 ; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], s4
; GFX6-NEXT: s_and_b32 s4, 1, s7 ; GFX6-NEXT: s_and_b32 s4, 1, s7
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX6-NEXT: s_and_b32 s4, 1, s9 ; GFX6-NEXT: s_and_b32 s4, 1, s9
; GFX6-NEXT: s_sub_i32 s10, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, s8, 64
; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_sub_i32 s10, 64, s8
; GFX6-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX6-NEXT: v_or_b32_e32 v6, v0, v6
; GFX6-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX6-NEXT: v_or_b32_e32 v7, v1, v7
; GFX6-NEXT: v_lshl_b64 v[0:1], v[4:5], s5 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[4:5], s5
; GFX6-NEXT: s_cmp_lt_u32 s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s11, 1, 0 ; GFX6-NEXT: s_cselect_b32 s12, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
; GFX6-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX6-NEXT: s_cselect_b32 s12, 1, 0
; GFX6-NEXT: s_lshr_b64 s[4:5], s[2:3], s8 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[2:3], s8
; GFX6-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 ; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s9 ; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], s9
; GFX6-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX6-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX6-NEXT: s_cmp_lg_u32 s11, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX6-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX6-NEXT: s_cmp_lg_u32 s11, 0 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0
; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX6-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 ; GFX6-NEXT: s_cselect_b64 s[2:3], s[4:5], 0
; GFX6-NEXT: v_or_b32_e32 v0, s0, v4 ; GFX6-NEXT: v_or_b32_e32 v0, s0, v4
; GFX6-NEXT: v_or_b32_e32 v1, s1, v5 ; GFX6-NEXT: v_or_b32_e32 v1, s1, v5
; GFX6-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX6-NEXT: v_or_b32_e32 v2, s2, v2
; GFX6-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX6-NEXT: v_or_b32_e32 v3, s3, v3
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
Show All 14 Lines
; GFX8-NEXT: s_cmp_eq_u32 s4, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0
; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: v_lshrrev_b64 v[0:1], s6, v[4:5] ; GFX8-NEXT: v_lshrrev_b64 v[0:1], s6, v[4:5]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
; GFX8-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5] ; GFX8-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5]
; GFX8-NEXT: s_and_b32 s4, 1, s7 ; GFX8-NEXT: s_and_b32 s4, 1, s7
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_and_b32 s4, 1, s9 ; GFX8-NEXT: s_and_b32 s4, 1, s9
; GFX8-NEXT: s_sub_i32 s10, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, s8, 64
; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_sub_i32 s10, 64, s8
; GFX8-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX8-NEXT: v_or_b32_e32 v6, v0, v6
; GFX8-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX8-NEXT: v_or_b32_e32 v7, v1, v7
; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[4:5] ; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[4:5]
; GFX8-NEXT: s_cmp_lt_u32 s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s11, 1, 0 ; GFX8-NEXT: s_cselect_b32 s12, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
; GFX8-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_cselect_b32 s12, 1, 0
; GFX8-NEXT: s_lshr_b64 s[4:5], s[2:3], s8 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[2:3], s8
; GFX8-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 ; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s9 ; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s9
; GFX8-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX8-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX8-NEXT: s_cmp_lg_u32 s11, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX8-NEXT: s_cmp_lg_u32 s12, 0 ; GFX8-NEXT: s_cmp_lg_u32 s12, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX8-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX8-NEXT: s_cmp_lg_u32 s11, 0 ; GFX8-NEXT: s_cmp_lg_u32 s12, 0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX8-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 ; GFX8-NEXT: s_cselect_b64 s[2:3], s[4:5], 0
; GFX8-NEXT: v_or_b32_e32 v0, s0, v4 ; GFX8-NEXT: v_or_b32_e32 v0, s0, v4
; GFX8-NEXT: v_or_b32_e32 v1, s1, v5 ; GFX8-NEXT: v_or_b32_e32 v1, s1, v5
; GFX8-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX8-NEXT: v_or_b32_e32 v2, s2, v2
; GFX8-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX8-NEXT: v_or_b32_e32 v3, s3, v3
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
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; GFX9-NEXT: s_cmp_eq_u32 s4, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0
; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: v_lshrrev_b64 v[0:1], s6, v[4:5] ; GFX9-NEXT: v_lshrrev_b64 v[0:1], s6, v[4:5]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3]
; GFX9-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5] ; GFX9-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5]
; GFX9-NEXT: s_and_b32 s4, 1, s7 ; GFX9-NEXT: s_and_b32 s4, 1, s7
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_and_b32 s4, 1, s9 ; GFX9-NEXT: s_and_b32 s4, 1, s9
; GFX9-NEXT: s_sub_i32 s10, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, s8, 64
; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_sub_i32 s10, 64, s8
; GFX9-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX9-NEXT: v_or_b32_e32 v6, v0, v6
; GFX9-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX9-NEXT: v_or_b32_e32 v7, v1, v7
; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[4:5] ; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[4:5]
; GFX9-NEXT: s_cmp_lt_u32 s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s11, 1, 0 ; GFX9-NEXT: s_cselect_b32 s12, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[0:1], s8
; GFX9-NEXT: s_lshl_b64 s[10:11], s[2:3], s10
; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_cselect_b32 s12, 1, 0
; GFX9-NEXT: s_lshr_b64 s[4:5], s[2:3], s8 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[2:3], s8
; GFX9-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 ; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s9 ; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s9
; GFX9-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
; GFX9-NEXT: s_cmp_lg_u32 s11, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX9-NEXT: s_cmp_lg_u32 s12, 0 ; GFX9-NEXT: s_cmp_lg_u32 s12, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[6:7], s[2:3]
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX9-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX9-NEXT: s_cmp_lg_u32 s11, 0 ; GFX9-NEXT: s_cmp_lg_u32 s12, 0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX9-NEXT: s_cselect_b64 s[2:3], s[4:5], 0 ; GFX9-NEXT: s_cselect_b64 s[2:3], s[4:5], 0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v4 ; GFX9-NEXT: v_or_b32_e32 v0, s0, v4
; GFX9-NEXT: v_or_b32_e32 v1, s1, v5 ; GFX9-NEXT: v_or_b32_e32 v1, s1, v5
; GFX9-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX9-NEXT: v_or_b32_e32 v2, s2, v2
; GFX9-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX9-NEXT: v_or_b32_e32 v3, s3, v3
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
Show All 17 Lines
; GFX10-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1]
; GFX10-NEXT: s_cselect_b32 s9, 1, 0 ; GFX10-NEXT: s_cselect_b32 s9, 1, 0
; GFX10-NEXT: s_and_b32 s4, 1, s7 ; GFX10-NEXT: s_and_b32 s4, 1, s7
; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7
; GFX10-NEXT: s_and_b32 s4, 1, s9 ; GFX10-NEXT: s_and_b32 s4, 1, s9
; GFX10-NEXT: s_sub_i32 s10, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, s8, 64
; GFX10-NEXT: s_sub_i32 s6, 64, s8 ; GFX10-NEXT: s_sub_i32 s6, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo
; GFX10-NEXT: s_cselect_b32 s11, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX10-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10-NEXT: s_cselect_b32 s12, 1, 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s8 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s8
; GFX10-NEXT: s_lshl_b64 s[6:7], s[2:3], s6 ; GFX10-NEXT: s_lshl_b64 s[6:7], s[2:3], s6
; GFX10-NEXT: s_lshr_b64 s[8:9], s[2:3], s8 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[2:3], s8
; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s9
; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v0, v2, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v3, vcc_lo
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX10-NEXT: v_or_b32_e32 v0, s0, v6
; GFX10-NEXT: s_cselect_b64 s[2:3], s[8:9], 0 ; GFX10-NEXT: s_cselect_b64 s[2:3], s[10:11], 0
; GFX10-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX10-NEXT: v_or_b32_e32 v1, s1, v7
; GFX10-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX10-NEXT: v_or_b32_e32 v2, s2, v2
; GFX10-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX10-NEXT: v_or_b32_e32 v3, s3, v3
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: v_fshr_i128_vss: ; GFX11-LABEL: v_fshr_i128_vss:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3] ; GFX11-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
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; GFX11-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[8:9], s4, v[0:1]
; GFX11-NEXT: s_cselect_b32 s9, 1, 0 ; GFX11-NEXT: s_cselect_b32 s9, 1, 0
; GFX11-NEXT: s_and_b32 s4, 1, s7 ; GFX11-NEXT: s_and_b32 s4, 1, s7
; GFX11-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1]
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX11-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX11-NEXT: v_or_b32_e32 v4, v4, v6
; GFX11-NEXT: v_or_b32_e32 v5, v5, v7 ; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-NEXT: s_and_b32 s4, 1, s9 ; GFX11-NEXT: s_and_b32 s4, 1, s9
; GFX11-NEXT: s_sub_i32 s10, s8, 64 ; GFX11-NEXT: s_sub_i32 s9, s8, 64
; GFX11-NEXT: s_sub_i32 s6, 64, s8 ; GFX11-NEXT: s_sub_i32 s6, 64, s8
; GFX11-NEXT: s_cmp_lt_u32 s8, 64 ; GFX11-NEXT: s_cmp_lt_u32 s8, 64
; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9 ; GFX11-NEXT: v_dual_cndmask_b32 v6, 0, v8 :: v_dual_cndmask_b32 v7, 0, v9
; GFX11-NEXT: s_cselect_b32 s11, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_cndmask_b32 v1, v1, v5
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX11-NEXT: s_cselect_b32 s12, 1, 0 ; GFX11-NEXT: s_cselect_b32 s12, 1, 0
; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX11-NEXT: s_lshr_b64 s[4:5], s[0:1], s8 ; GFX11-NEXT: s_lshr_b64 s[4:5], s[0:1], s8
; GFX11-NEXT: s_lshl_b64 s[6:7], s[2:3], s6 ; GFX11-NEXT: s_lshl_b64 s[6:7], s[2:3], s6
; GFX11-NEXT: s_lshr_b64 s[8:9], s[2:3], s8 ; GFX11-NEXT: s_lshr_b64 s[10:11], s[2:3], s8
; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s10 ; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s9
; GFX11-NEXT: s_cmp_lg_u32 s11, 0 ; GFX11-NEXT: s_cmp_lg_u32 s12, 0
; GFX11-NEXT: v_dual_cndmask_b32 v2, v0, v2 :: v_dual_cndmask_b32 v3, v1, v3 ; GFX11-NEXT: v_dual_cndmask_b32 v2, v0, v2 :: v_dual_cndmask_b32 v3, v1, v3
; GFX11-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3] ; GFX11-NEXT: s_cselect_b64 s[2:3], s[4:5], s[2:3]
; GFX11-NEXT: s_cmp_lg_u32 s12, 0 ; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GFX11-NEXT: s_cmp_lg_u32 s11, 0 ; GFX11-NEXT: s_cmp_lg_u32 s12, 0
; GFX11-NEXT: v_or_b32_e32 v0, s0, v6 ; GFX11-NEXT: v_or_b32_e32 v0, s0, v6
; GFX11-NEXT: s_cselect_b64 s[2:3], s[8:9], 0 ; GFX11-NEXT: s_cselect_b64 s[2:3], s[10:11], 0
; GFX11-NEXT: v_or_b32_e32 v1, s1, v7 ; GFX11-NEXT: v_or_b32_e32 v1, s1, v7
; GFX11-NEXT: v_or_b32_e32 v2, s2, v2 ; GFX11-NEXT: v_or_b32_e32 v2, s2, v2
; GFX11-NEXT: v_or_b32_e32 v3, s3, v3 ; GFX11-NEXT: v_or_b32_e32 v3, s3, v3
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt) %result = call i128 @llvm.fshr.i128(i128 %lhs, i128 %rhs, i128 %amt)
%cast.result = bitcast i128 %result to <4 x float> %cast.result = bitcast i128 %result to <4 x float>
ret <4 x float> %cast.result ret <4 x float> %cast.result
} }
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_mov_b32 s19, 0 ; GFX6-NEXT: s_mov_b32 s19, 0
; GFX6-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX6-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX6-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] ; GFX6-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX6-NEXT: s_lshl_b64 s[24:25], s[0:1], 1 ; GFX6-NEXT: s_lshl_b64 s[24:25], s[0:1], 1
; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX6-NEXT: s_lshr_b32 s0, s1, 31 ; GFX6-NEXT: s_lshr_b32 s0, s1, 31
; GFX6-NEXT: s_mov_b32 s1, s19 ; GFX6-NEXT: s_mov_b32 s1, s19
; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; GFX6-NEXT: s_sub_i32 s23, s16, 64 ; GFX6-NEXT: s_sub_i32 s17, s16, 64
; GFX6-NEXT: s_sub_i32 s17, 64, s16 ; GFX6-NEXT: s_sub_i32 s23, 64, s16
; GFX6-NEXT: s_cmp_lt_u32 s16, 64 ; GFX6-NEXT: s_cmp_lt_u32 s16, 64
; GFX6-NEXT: s_cselect_b32 s28, 1, 0 ; GFX6-NEXT: s_cselect_b32 s30, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s16, 0 ; GFX6-NEXT: s_lshr_b64 s[26:27], s[24:25], s23
; GFX6-NEXT: s_cselect_b32 s29, 1, 0 ; GFX6-NEXT: s_lshl_b64 s[28:29], s[0:1], s16
; GFX6-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[24:25], s16
; GFX6-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX6-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29]
; GFX6-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 ; GFX6-NEXT: s_lshl_b64 s[24:25], s[24:25], s17
; GFX6-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17] ; GFX6-NEXT: s_cmp_lg_u32 s30, 0
; GFX6-NEXT: s_lshl_b64 s[24:25], s[24:25], s23
; GFX6-NEXT: s_cmp_lg_u32 s28, 0
; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX6-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX6-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25] ; GFX6-NEXT: s_cselect_b64 s[24:25], s[26:27], s[24:25]
; GFX6-NEXT: s_cmp_lg_u32 s29, 0 ; GFX6-NEXT: s_cmp_eq_u32 s16, 0
; GFX6-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17] ; GFX6-NEXT: s_cselect_b64 s[16:17], s[0:1], s[24:25]
; GFX6-NEXT: s_sub_i32 s26, s22, 64 ; GFX6-NEXT: s_sub_i32 s23, s22, 64
; GFX6-NEXT: s_sub_i32 s24, 64, s22 ; GFX6-NEXT: s_sub_i32 s26, 64, s22
; GFX6-NEXT: s_cmp_lt_u32 s22, 64 ; GFX6-NEXT: s_cmp_lt_u32 s22, 64
; GFX6-NEXT: s_cselect_b32 s27, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s22, 0
; GFX6-NEXT: s_cselect_b32 s28, 1, 0 ; GFX6-NEXT: s_cselect_b32 s28, 1, 0
; GFX6-NEXT: s_lshr_b64 s[24:25], s[8:9], s22
; GFX6-NEXT: s_lshl_b64 s[26:27], s[10:11], s26
; GFX6-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[10:11], s22
; GFX6-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 ; GFX6-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
; GFX6-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[10:11], s23
; GFX6-NEXT: s_or_b64 s[22:23], s[22:23], s[24:25]
; GFX6-NEXT: s_lshr_b64 s[10:11], s[10:11], s26
; GFX6-NEXT: s_cmp_lg_u32 s27, 0
; GFX6-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11]
; GFX6-NEXT: s_cmp_lg_u32 s28, 0 ; GFX6-NEXT: s_cmp_lg_u32 s28, 0
; GFX6-NEXT: s_cselect_b64 s[10:11], s[24:25], s[10:11]
; GFX6-NEXT: s_cmp_eq_u32 s22, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
; GFX6-NEXT: s_cmp_lg_u32 s27, 0 ; GFX6-NEXT: s_cmp_lg_u32 s28, 0
; GFX6-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 ; GFX6-NEXT: s_cselect_b64 s[10:11], s[0:1], 0
; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9] ; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9]
; GFX6-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11] ; GFX6-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11]
; GFX6-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX6-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX6-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX6-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GFX6-NEXT: s_lshr_b32 s18, s5, 31 ; GFX6-NEXT: s_lshr_b32 s18, s5, 31
; GFX6-NEXT: s_lshl_b64 s[16:17], s[4:5], 1 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[4:5], 1
; GFX6-NEXT: s_or_b64 s[4:5], s[6:7], s[18:19] ; GFX6-NEXT: s_or_b64 s[4:5], s[6:7], s[18:19]
; GFX6-NEXT: s_sub_i32 s9, s10, 64 ; GFX6-NEXT: s_sub_i32 s9, s10, 64
; GFX6-NEXT: s_sub_i32 s11, 64, s10 ; GFX6-NEXT: s_sub_i32 s11, 64, s10
; GFX6-NEXT: s_cmp_lt_u32 s10, 64 ; GFX6-NEXT: s_cmp_lt_u32 s10, 64
; GFX6-NEXT: s_cselect_b32 s20, 1, 0 ; GFX6-NEXT: s_cselect_b32 s22, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s10, 0
; GFX6-NEXT: s_cselect_b32 s21, 1, 0
; GFX6-NEXT: s_lshl_b64 s[6:7], s[16:17], s10
; GFX6-NEXT: s_lshr_b64 s[18:19], s[16:17], s11 ; GFX6-NEXT: s_lshr_b64 s[18:19], s[16:17], s11
; GFX6-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX6-NEXT: s_lshl_b64 s[20:21], s[4:5], s10
; GFX6-NEXT: s_or_b64 s[10:11], s[18:19], s[10:11] ; GFX6-NEXT: s_lshl_b64 s[6:7], s[16:17], s10
; GFX6-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21]
; GFX6-NEXT: s_lshl_b64 s[16:17], s[16:17], s9 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[16:17], s9
; GFX6-NEXT: s_cmp_lg_u32 s20, 0 ; GFX6-NEXT: s_cmp_lg_u32 s22, 0
; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX6-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX6-NEXT: s_cselect_b64 s[10:11], s[10:11], s[16:17] ; GFX6-NEXT: s_cselect_b64 s[16:17], s[18:19], s[16:17]
; GFX6-NEXT: s_cmp_lg_u32 s21, 0 ; GFX6-NEXT: s_cmp_eq_u32 s10, 0
; GFX6-NEXT: s_cselect_b64 s[10:11], s[4:5], s[10:11] ; GFX6-NEXT: s_cselect_b64 s[10:11], s[4:5], s[16:17]
; GFX6-NEXT: s_sub_i32 s18, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, s8, 64
; GFX6-NEXT: s_sub_i32 s16, 64, s8 ; GFX6-NEXT: s_sub_i32 s18, 64, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64
; GFX6-NEXT: s_cselect_b32 s19, 1, 0
; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b32 s20, 1, 0 ; GFX6-NEXT: s_cselect_b32 s20, 1, 0
; GFX6-NEXT: s_lshr_b64 s[16:17], s[12:13], s8
; GFX6-NEXT: s_lshl_b64 s[18:19], s[14:15], s18
; GFX6-NEXT: s_lshr_b64 s[4:5], s[14:15], s8 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[14:15], s8
; GFX6-NEXT: s_lshr_b64 s[8:9], s[12:13], s8 ; GFX6-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GFX6-NEXT: s_lshl_b64 s[16:17], s[14:15], s16 ; GFX6-NEXT: s_lshr_b64 s[14:15], s[14:15], s9
; GFX6-NEXT: s_or_b64 s[8:9], s[8:9], s[16:17] ; GFX6-NEXT: s_cmp_lg_u32 s20, 0
; GFX6-NEXT: s_lshr_b64 s[14:15], s[14:15], s18 ; GFX6-NEXT: s_cselect_b64 s[14:15], s[16:17], s[14:15]
; GFX6-NEXT: s_cmp_lg_u32 s19, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[8:9], s[14:15] ; GFX6-NEXT: s_cselect_b64 s[8:9], s[12:13], s[14:15]
; GFX6-NEXT: s_cmp_lg_u32 s20, 0 ; GFX6-NEXT: s_cmp_lg_u32 s20, 0
; GFX6-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
; GFX6-NEXT: s_cmp_lg_u32 s19, 0
; GFX6-NEXT: s_cselect_b64 s[12:13], s[4:5], 0 ; GFX6-NEXT: s_cselect_b64 s[12:13], s[4:5], 0
; GFX6-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9] ; GFX6-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
; GFX6-NEXT: s_or_b64 s[6:7], s[10:11], s[12:13] ; GFX6-NEXT: s_or_b64 s[6:7], s[10:11], s[12:13]
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_fshr_v2i128: ; GFX8-LABEL: s_fshr_v2i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_movk_i32 s18, 0x7f ; GFX8-NEXT: s_movk_i32 s18, 0x7f
; GFX8-NEXT: s_mov_b32 s19, 0 ; GFX8-NEXT: s_mov_b32 s19, 0
; GFX8-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX8-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX8-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] ; GFX8-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX8-NEXT: s_lshl_b64 s[24:25], s[0:1], 1 ; GFX8-NEXT: s_lshl_b64 s[24:25], s[0:1], 1
; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX8-NEXT: s_lshr_b32 s0, s1, 31 ; GFX8-NEXT: s_lshr_b32 s0, s1, 31
; GFX8-NEXT: s_mov_b32 s1, s19 ; GFX8-NEXT: s_mov_b32 s1, s19
; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; GFX8-NEXT: s_sub_i32 s23, s16, 64 ; GFX8-NEXT: s_sub_i32 s17, s16, 64
; GFX8-NEXT: s_sub_i32 s17, 64, s16 ; GFX8-NEXT: s_sub_i32 s23, 64, s16
; GFX8-NEXT: s_cmp_lt_u32 s16, 64 ; GFX8-NEXT: s_cmp_lt_u32 s16, 64
; GFX8-NEXT: s_cselect_b32 s28, 1, 0 ; GFX8-NEXT: s_cselect_b32 s30, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s16, 0 ; GFX8-NEXT: s_lshr_b64 s[26:27], s[24:25], s23
; GFX8-NEXT: s_cselect_b32 s29, 1, 0 ; GFX8-NEXT: s_lshl_b64 s[28:29], s[0:1], s16
; GFX8-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[24:25], s16
; GFX8-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX8-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29]
; GFX8-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 ; GFX8-NEXT: s_lshl_b64 s[24:25], s[24:25], s17
; GFX8-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17] ; GFX8-NEXT: s_cmp_lg_u32 s30, 0
; GFX8-NEXT: s_lshl_b64 s[24:25], s[24:25], s23
; GFX8-NEXT: s_cmp_lg_u32 s28, 0
; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX8-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX8-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25] ; GFX8-NEXT: s_cselect_b64 s[24:25], s[26:27], s[24:25]
; GFX8-NEXT: s_cmp_lg_u32 s29, 0 ; GFX8-NEXT: s_cmp_eq_u32 s16, 0
; GFX8-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17] ; GFX8-NEXT: s_cselect_b64 s[16:17], s[0:1], s[24:25]
; GFX8-NEXT: s_sub_i32 s26, s22, 64 ; GFX8-NEXT: s_sub_i32 s23, s22, 64
; GFX8-NEXT: s_sub_i32 s24, 64, s22 ; GFX8-NEXT: s_sub_i32 s26, 64, s22
; GFX8-NEXT: s_cmp_lt_u32 s22, 64 ; GFX8-NEXT: s_cmp_lt_u32 s22, 64
; GFX8-NEXT: s_cselect_b32 s27, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s22, 0
; GFX8-NEXT: s_cselect_b32 s28, 1, 0 ; GFX8-NEXT: s_cselect_b32 s28, 1, 0
; GFX8-NEXT: s_lshr_b64 s[24:25], s[8:9], s22
; GFX8-NEXT: s_lshl_b64 s[26:27], s[10:11], s26
; GFX8-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[10:11], s22
; GFX8-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 ; GFX8-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
; GFX8-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[10:11], s23
; GFX8-NEXT: s_or_b64 s[22:23], s[22:23], s[24:25]
; GFX8-NEXT: s_lshr_b64 s[10:11], s[10:11], s26
; GFX8-NEXT: s_cmp_lg_u32 s27, 0
; GFX8-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11]
; GFX8-NEXT: s_cmp_lg_u32 s28, 0 ; GFX8-NEXT: s_cmp_lg_u32 s28, 0
; GFX8-NEXT: s_cselect_b64 s[10:11], s[24:25], s[10:11]
; GFX8-NEXT: s_cmp_eq_u32 s22, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
; GFX8-NEXT: s_cmp_lg_u32 s27, 0 ; GFX8-NEXT: s_cmp_lg_u32 s28, 0
; GFX8-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 ; GFX8-NEXT: s_cselect_b64 s[10:11], s[0:1], 0
; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9] ; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9]
; GFX8-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11] ; GFX8-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11]
; GFX8-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX8-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX8-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX8-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GFX8-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GFX8-NEXT: s_lshr_b32 s18, s5, 31 ; GFX8-NEXT: s_lshr_b32 s18, s5, 31
; GFX8-NEXT: s_lshl_b64 s[16:17], s[4:5], 1 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[4:5], 1
; GFX8-NEXT: s_or_b64 s[4:5], s[6:7], s[18:19] ; GFX8-NEXT: s_or_b64 s[4:5], s[6:7], s[18:19]
; GFX8-NEXT: s_sub_i32 s9, s10, 64 ; GFX8-NEXT: s_sub_i32 s9, s10, 64
; GFX8-NEXT: s_sub_i32 s11, 64, s10 ; GFX8-NEXT: s_sub_i32 s11, 64, s10
; GFX8-NEXT: s_cmp_lt_u32 s10, 64 ; GFX8-NEXT: s_cmp_lt_u32 s10, 64
; GFX8-NEXT: s_cselect_b32 s20, 1, 0 ; GFX8-NEXT: s_cselect_b32 s22, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s10, 0
; GFX8-NEXT: s_cselect_b32 s21, 1, 0
; GFX8-NEXT: s_lshl_b64 s[6:7], s[16:17], s10
; GFX8-NEXT: s_lshr_b64 s[18:19], s[16:17], s11 ; GFX8-NEXT: s_lshr_b64 s[18:19], s[16:17], s11
; GFX8-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX8-NEXT: s_lshl_b64 s[20:21], s[4:5], s10
; GFX8-NEXT: s_or_b64 s[10:11], s[18:19], s[10:11] ; GFX8-NEXT: s_lshl_b64 s[6:7], s[16:17], s10
; GFX8-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21]
; GFX8-NEXT: s_lshl_b64 s[16:17], s[16:17], s9 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[16:17], s9
; GFX8-NEXT: s_cmp_lg_u32 s20, 0 ; GFX8-NEXT: s_cmp_lg_u32 s22, 0
; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX8-NEXT: s_cselect_b64 s[10:11], s[10:11], s[16:17] ; GFX8-NEXT: s_cselect_b64 s[16:17], s[18:19], s[16:17]
; GFX8-NEXT: s_cmp_lg_u32 s21, 0 ; GFX8-NEXT: s_cmp_eq_u32 s10, 0
; GFX8-NEXT: s_cselect_b64 s[10:11], s[4:5], s[10:11] ; GFX8-NEXT: s_cselect_b64 s[10:11], s[4:5], s[16:17]
; GFX8-NEXT: s_sub_i32 s18, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, s8, 64
; GFX8-NEXT: s_sub_i32 s16, 64, s8 ; GFX8-NEXT: s_sub_i32 s18, 64, s8
; GFX8-NEXT: s_cmp_lt_u32 s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64
; GFX8-NEXT: s_cselect_b32 s19, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b32 s20, 1, 0 ; GFX8-NEXT: s_cselect_b32 s20, 1, 0
; GFX8-NEXT: s_lshr_b64 s[16:17], s[12:13], s8
; GFX8-NEXT: s_lshl_b64 s[18:19], s[14:15], s18
; GFX8-NEXT: s_lshr_b64 s[4:5], s[14:15], s8 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[14:15], s8
; GFX8-NEXT: s_lshr_b64 s[8:9], s[12:13], s8 ; GFX8-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GFX8-NEXT: s_lshl_b64 s[16:17], s[14:15], s16 ; GFX8-NEXT: s_lshr_b64 s[14:15], s[14:15], s9
; GFX8-NEXT: s_or_b64 s[8:9], s[8:9], s[16:17] ; GFX8-NEXT: s_cmp_lg_u32 s20, 0
; GFX8-NEXT: s_lshr_b64 s[14:15], s[14:15], s18 ; GFX8-NEXT: s_cselect_b64 s[14:15], s[16:17], s[14:15]
; GFX8-NEXT: s_cmp_lg_u32 s19, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[8:9], s[14:15] ; GFX8-NEXT: s_cselect_b64 s[8:9], s[12:13], s[14:15]
; GFX8-NEXT: s_cmp_lg_u32 s20, 0 ; GFX8-NEXT: s_cmp_lg_u32 s20, 0
; GFX8-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
; GFX8-NEXT: s_cmp_lg_u32 s19, 0
; GFX8-NEXT: s_cselect_b64 s[12:13], s[4:5], 0 ; GFX8-NEXT: s_cselect_b64 s[12:13], s[4:5], 0
; GFX8-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9] ; GFX8-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
; GFX8-NEXT: s_or_b64 s[6:7], s[10:11], s[12:13] ; GFX8-NEXT: s_or_b64 s[6:7], s[10:11], s[12:13]
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_fshr_v2i128: ; GFX9-LABEL: s_fshr_v2i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_movk_i32 s18, 0x7f ; GFX9-NEXT: s_movk_i32 s18, 0x7f
; GFX9-NEXT: s_mov_b32 s19, 0 ; GFX9-NEXT: s_mov_b32 s19, 0
; GFX9-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX9-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX9-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] ; GFX9-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX9-NEXT: s_lshl_b64 s[24:25], s[0:1], 1 ; GFX9-NEXT: s_lshl_b64 s[24:25], s[0:1], 1
; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX9-NEXT: s_lshr_b32 s0, s1, 31 ; GFX9-NEXT: s_lshr_b32 s0, s1, 31
; GFX9-NEXT: s_mov_b32 s1, s19 ; GFX9-NEXT: s_mov_b32 s1, s19
; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; GFX9-NEXT: s_sub_i32 s23, s16, 64 ; GFX9-NEXT: s_sub_i32 s17, s16, 64
; GFX9-NEXT: s_sub_i32 s17, 64, s16 ; GFX9-NEXT: s_sub_i32 s23, 64, s16
; GFX9-NEXT: s_cmp_lt_u32 s16, 64 ; GFX9-NEXT: s_cmp_lt_u32 s16, 64
; GFX9-NEXT: s_cselect_b32 s28, 1, 0 ; GFX9-NEXT: s_cselect_b32 s30, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s16, 0 ; GFX9-NEXT: s_lshr_b64 s[26:27], s[24:25], s23
; GFX9-NEXT: s_cselect_b32 s29, 1, 0 ; GFX9-NEXT: s_lshl_b64 s[28:29], s[0:1], s16
; GFX9-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[24:25], s16
; GFX9-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX9-NEXT: s_or_b64 s[26:27], s[26:27], s[28:29]
; GFX9-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 ; GFX9-NEXT: s_lshl_b64 s[24:25], s[24:25], s17
; GFX9-NEXT: s_or_b64 s[16:17], s[26:27], s[16:17] ; GFX9-NEXT: s_cmp_lg_u32 s30, 0
; GFX9-NEXT: s_lshl_b64 s[24:25], s[24:25], s23
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX9-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX9-NEXT: s_cselect_b64 s[16:17], s[16:17], s[24:25] ; GFX9-NEXT: s_cselect_b64 s[24:25], s[26:27], s[24:25]
; GFX9-NEXT: s_cmp_lg_u32 s29, 0 ; GFX9-NEXT: s_cmp_eq_u32 s16, 0
; GFX9-NEXT: s_cselect_b64 s[16:17], s[0:1], s[16:17] ; GFX9-NEXT: s_cselect_b64 s[16:17], s[0:1], s[24:25]
; GFX9-NEXT: s_sub_i32 s26, s22, 64 ; GFX9-NEXT: s_sub_i32 s23, s22, 64
; GFX9-NEXT: s_sub_i32 s24, 64, s22 ; GFX9-NEXT: s_sub_i32 s26, 64, s22
; GFX9-NEXT: s_cmp_lt_u32 s22, 64 ; GFX9-NEXT: s_cmp_lt_u32 s22, 64
; GFX9-NEXT: s_cselect_b32 s27, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s22, 0
; GFX9-NEXT: s_cselect_b32 s28, 1, 0 ; GFX9-NEXT: s_cselect_b32 s28, 1, 0
; GFX9-NEXT: s_lshr_b64 s[24:25], s[8:9], s22
; GFX9-NEXT: s_lshl_b64 s[26:27], s[10:11], s26
; GFX9-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[10:11], s22
; GFX9-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 ; GFX9-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
; GFX9-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s23
; GFX9-NEXT: s_or_b64 s[22:23], s[22:23], s[24:25]
; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s26
; GFX9-NEXT: s_cmp_lg_u32 s27, 0
; GFX9-NEXT: s_cselect_b64 s[10:11], s[22:23], s[10:11]
; GFX9-NEXT: s_cmp_lg_u32 s28, 0 ; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cselect_b64 s[10:11], s[24:25], s[10:11]
; GFX9-NEXT: s_cmp_eq_u32 s22, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11] ; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[10:11]
; GFX9-NEXT: s_cmp_lg_u32 s27, 0 ; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cselect_b64 s[10:11], s[0:1], 0 ; GFX9-NEXT: s_cselect_b64 s[10:11], s[0:1], 0
; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9] ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[8:9]
; GFX9-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11] ; GFX9-NEXT: s_or_b64 s[2:3], s[16:17], s[10:11]
; GFX9-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX9-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX9-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX9-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX9-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GFX9-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GFX9-NEXT: s_lshr_b32 s18, s5, 31 ; GFX9-NEXT: s_lshr_b32 s18, s5, 31
; GFX9-NEXT: s_lshl_b64 s[16:17], s[4:5], 1 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[4:5], 1
; GFX9-NEXT: s_or_b64 s[4:5], s[6:7], s[18:19] ; GFX9-NEXT: s_or_b64 s[4:5], s[6:7], s[18:19]
; GFX9-NEXT: s_sub_i32 s9, s10, 64 ; GFX9-NEXT: s_sub_i32 s9, s10, 64
; GFX9-NEXT: s_sub_i32 s11, 64, s10 ; GFX9-NEXT: s_sub_i32 s11, 64, s10
; GFX9-NEXT: s_cmp_lt_u32 s10, 64 ; GFX9-NEXT: s_cmp_lt_u32 s10, 64
; GFX9-NEXT: s_cselect_b32 s20, 1, 0 ; GFX9-NEXT: s_cselect_b32 s22, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s10, 0
; GFX9-NEXT: s_cselect_b32 s21, 1, 0
; GFX9-NEXT: s_lshl_b64 s[6:7], s[16:17], s10
; GFX9-NEXT: s_lshr_b64 s[18:19], s[16:17], s11 ; GFX9-NEXT: s_lshr_b64 s[18:19], s[16:17], s11
; GFX9-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX9-NEXT: s_lshl_b64 s[20:21], s[4:5], s10
; GFX9-NEXT: s_or_b64 s[10:11], s[18:19], s[10:11] ; GFX9-NEXT: s_lshl_b64 s[6:7], s[16:17], s10
; GFX9-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21]
; GFX9-NEXT: s_lshl_b64 s[16:17], s[16:17], s9 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[16:17], s9
; GFX9-NEXT: s_cmp_lg_u32 s20, 0 ; GFX9-NEXT: s_cmp_lg_u32 s22, 0
; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], 0 ; GFX9-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX9-NEXT: s_cselect_b64 s[10:11], s[10:11], s[16:17] ; GFX9-NEXT: s_cselect_b64 s[16:17], s[18:19], s[16:17]
; GFX9-NEXT: s_cmp_lg_u32 s21, 0 ; GFX9-NEXT: s_cmp_eq_u32 s10, 0
; GFX9-NEXT: s_cselect_b64 s[10:11], s[4:5], s[10:11] ; GFX9-NEXT: s_cselect_b64 s[10:11], s[4:5], s[16:17]
; GFX9-NEXT: s_sub_i32 s18, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, s8, 64
; GFX9-NEXT: s_sub_i32 s16, 64, s8 ; GFX9-NEXT: s_sub_i32 s18, 64, s8
; GFX9-NEXT: s_cmp_lt_u32 s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64
; GFX9-NEXT: s_cselect_b32 s19, 1, 0
; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b32 s20, 1, 0 ; GFX9-NEXT: s_cselect_b32 s20, 1, 0
; GFX9-NEXT: s_lshr_b64 s[16:17], s[12:13], s8
; GFX9-NEXT: s_lshl_b64 s[18:19], s[14:15], s18
; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], s8 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], s8
; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], s8 ; GFX9-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GFX9-NEXT: s_lshl_b64 s[16:17], s[14:15], s16 ; GFX9-NEXT: s_lshr_b64 s[14:15], s[14:15], s9
; GFX9-NEXT: s_or_b64 s[8:9], s[8:9], s[16:17] ; GFX9-NEXT: s_cmp_lg_u32 s20, 0
; GFX9-NEXT: s_lshr_b64 s[14:15], s[14:15], s18 ; GFX9-NEXT: s_cselect_b64 s[14:15], s[16:17], s[14:15]
; GFX9-NEXT: s_cmp_lg_u32 s19, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[8:9], s[14:15] ; GFX9-NEXT: s_cselect_b64 s[8:9], s[12:13], s[14:15]
; GFX9-NEXT: s_cmp_lg_u32 s20, 0 ; GFX9-NEXT: s_cmp_lg_u32 s20, 0
; GFX9-NEXT: s_cselect_b64 s[8:9], s[12:13], s[8:9]
; GFX9-NEXT: s_cmp_lg_u32 s19, 0
; GFX9-NEXT: s_cselect_b64 s[12:13], s[4:5], 0 ; GFX9-NEXT: s_cselect_b64 s[12:13], s[4:5], 0
; GFX9-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9] ; GFX9-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
; GFX9-NEXT: s_or_b64 s[6:7], s[10:11], s[12:13] ; GFX9-NEXT: s_or_b64 s[6:7], s[10:11], s[12:13]
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_fshr_v2i128: ; GFX10-LABEL: s_fshr_v2i128:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_movk_i32 s18, 0x7f ; GFX10-NEXT: s_movk_i32 s18, 0x7f
; GFX10-NEXT: s_mov_b32 s19, 0 ; GFX10-NEXT: s_mov_b32 s19, 0
; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX10-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX10-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17] ; GFX10-NEXT: s_andn2_b64 s[16:17], s[18:19], s[16:17]
; GFX10-NEXT: s_lshr_b32 s24, s1, 31 ; GFX10-NEXT: s_lshr_b32 s24, s1, 31
; GFX10-NEXT: s_mov_b32 s25, s19 ; GFX10-NEXT: s_mov_b32 s25, s19
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[24:25] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[24:25]
; GFX10-NEXT: s_sub_i32 s23, s16, 64 ; GFX10-NEXT: s_sub_i32 s17, s16, 64
; GFX10-NEXT: s_sub_i32 s17, 64, s16 ; GFX10-NEXT: s_sub_i32 s23, 64, s16
; GFX10-NEXT: s_cmp_lt_u32 s16, 64 ; GFX10-NEXT: s_cmp_lt_u32 s16, 64
; GFX10-NEXT: s_cselect_b32 s28, 1, 0 ; GFX10-NEXT: s_cselect_b32 s30, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s16, 0 ; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s23
; GFX10-NEXT: s_cselect_b32 s29, 1, 0
; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s17
; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], s16 ; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], s16
; GFX10-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 ; GFX10-NEXT: s_lshl_b64 s[28:29], s[0:1], s16
; GFX10-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27] ; GFX10-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s23 ; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], s17
; GFX10-NEXT: s_cmp_lg_u32 s28, 0 ; GFX10-NEXT: s_cmp_lg_u32 s30, 0
; GFX10-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 ; GFX10-NEXT: s_cselect_b64 s[26:27], s[28:29], 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s29, 0 ; GFX10-NEXT: s_cmp_eq_u32 s16, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX10-NEXT: s_sub_i32 s26, s22, 64 ; GFX10-NEXT: s_sub_i32 s23, s22, 64
; GFX10-NEXT: s_sub_i32 s23, 64, s22 ; GFX10-NEXT: s_sub_i32 s16, 64, s22
; GFX10-NEXT: s_cmp_lt_u32 s22, 64 ; GFX10-NEXT: s_cmp_lt_u32 s22, 64
; GFX10-NEXT: s_cselect_b32 s27, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s22, 0
; GFX10-NEXT: s_cselect_b32 s28, 1, 0 ; GFX10-NEXT: s_cselect_b32 s28, 1, 0
; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], s22 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], s22
; GFX10-NEXT: s_lshl_b64 s[24:25], s[10:11], s23 ; GFX10-NEXT: s_lshl_b64 s[16:17], s[10:11], s16
; GFX10-NEXT: s_lshr_b64 s[22:23], s[10:11], s22 ; GFX10-NEXT: s_lshr_b64 s[24:25], s[10:11], s22
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[24:25] ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[16:17]
; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], s26 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[10:11], s23
; GFX10-NEXT: s_cmp_lg_u32 s27, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11]
; GFX10-NEXT: s_cmp_lg_u32 s28, 0 ; GFX10-NEXT: s_cmp_lg_u32 s28, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11]
; GFX10-NEXT: s_cmp_eq_u32 s22, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX10-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX10-NEXT: s_cmp_lg_u32 s27, 0 ; GFX10-NEXT: s_cmp_lg_u32 s28, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[22:23], 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[24:25], 0
; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21] ; GFX10-NEXT: s_andn2_b64 s[10:11], s[18:19], s[20:21]
; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX10-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX10-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX10-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX10-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GFX10-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GFX10-NEXT: s_lshr_b32 s18, s5, 31 ; GFX10-NEXT: s_lshr_b32 s18, s5, 31
; GFX10-NEXT: s_or_b64 s[0:1], s[16:17], s[0:1] ; GFX10-NEXT: s_or_b64 s[0:1], s[26:27], s[0:1]
; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], 1 ; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], 1
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[18:19] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[18:19]
; GFX10-NEXT: s_sub_i32 s9, s10, 64 ; GFX10-NEXT: s_sub_i32 s9, s10, 64
; GFX10-NEXT: s_sub_i32 s11, 64, s10 ; GFX10-NEXT: s_sub_i32 s11, 64, s10
; GFX10-NEXT: s_cmp_lt_u32 s10, 64 ; GFX10-NEXT: s_cmp_lt_u32 s10, 64
; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_cselect_b32 s22, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s10, 0
; GFX10-NEXT: s_cselect_b32 s21, 1, 0
; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s11 ; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s11
; GFX10-NEXT: s_lshl_b64 s[18:19], s[6:7], s10 ; GFX10-NEXT: s_lshl_b64 s[18:19], s[6:7], s10
; GFX10-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX10-NEXT: s_lshl_b64 s[20:21], s[4:5], s10
; GFX10-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GFX10-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], s9 ; GFX10-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: s_cmp_lg_u32 s22, 0
; GFX10-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 ; GFX10-NEXT: s_cselect_b64 s[18:19], s[20:21], 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] ; GFX10-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5]
; GFX10-NEXT: s_cmp_lg_u32 s21, 0 ; GFX10-NEXT: s_cmp_eq_u32 s10, 0
; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] ; GFX10-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX10-NEXT: s_sub_i32 s18, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, s8, 64
; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_sub_i32 s10, 64, s8
; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64
; GFX10-NEXT: s_cselect_b32 s19, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: s_cselect_b32 s20, 1, 0 ; GFX10-NEXT: s_cselect_b32 s20, 1, 0
; GFX10-NEXT: s_lshr_b64 s[4:5], s[12:13], s8 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[12:13], s8
; GFX10-NEXT: s_lshl_b64 s[16:17], s[14:15], s9 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[14:15], s10
; GFX10-NEXT: s_lshr_b64 s[8:9], s[14:15], s8 ; GFX10-NEXT: s_lshr_b64 s[16:17], s[14:15], s8
; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[16:17] ; GFX10-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
; GFX10-NEXT: s_lshr_b64 s[14:15], s[14:15], s18 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[14:15], s9
; GFX10-NEXT: s_cmp_lg_u32 s19, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[14:15]
; GFX10-NEXT: s_cmp_lg_u32 s20, 0 ; GFX10-NEXT: s_cmp_lg_u32 s20, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
; GFX10-NEXT: s_cmp_eq_u32 s8, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[12:13], s[4:5] ; GFX10-NEXT: s_cselect_b64 s[4:5], s[12:13], s[4:5]
; GFX10-NEXT: s_cmp_lg_u32 s19, 0 ; GFX10-NEXT: s_cmp_lg_u32 s20, 0
; GFX10-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX10-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
; GFX10-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5] ; GFX10-NEXT: s_or_b64 s[4:5], s[18:19], s[4:5]
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_fshr_v2i128: ; GFX11-LABEL: s_fshr_v2i128:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_movk_i32 s18, 0x7f ; GFX11-NEXT: s_movk_i32 s18, 0x7f
; GFX11-NEXT: s_mov_b32 s19, 0 ; GFX11-NEXT: s_mov_b32 s19, 0
; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GFX11-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19] ; GFX11-NEXT: s_and_b64 s[22:23], s[16:17], s[18:19]
; GFX11-NEXT: s_and_not1_b64 s[16:17], s[18:19], s[16:17] ; GFX11-NEXT: s_and_not1_b64 s[16:17], s[18:19], s[16:17]
; GFX11-NEXT: s_lshr_b32 s24, s1, 31 ; GFX11-NEXT: s_lshr_b32 s24, s1, 31
; GFX11-NEXT: s_mov_b32 s25, s19 ; GFX11-NEXT: s_mov_b32 s25, s19
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 1
; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[24:25] ; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[24:25]
; GFX11-NEXT: s_sub_i32 s23, s16, 64 ; GFX11-NEXT: s_sub_i32 s17, s16, 64
; GFX11-NEXT: s_sub_i32 s17, 64, s16 ; GFX11-NEXT: s_sub_i32 s23, 64, s16
; GFX11-NEXT: s_cmp_lt_u32 s16, 64 ; GFX11-NEXT: s_cmp_lt_u32 s16, 64
; GFX11-NEXT: s_cselect_b32 s28, 1, 0 ; GFX11-NEXT: s_cselect_b32 s30, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s16, 0 ; GFX11-NEXT: s_lshr_b64 s[24:25], s[0:1], s23
; GFX11-NEXT: s_cselect_b32 s29, 1, 0
; GFX11-NEXT: s_lshr_b64 s[24:25], s[0:1], s17
; GFX11-NEXT: s_lshl_b64 s[26:27], s[2:3], s16 ; GFX11-NEXT: s_lshl_b64 s[26:27], s[2:3], s16
; GFX11-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 ; GFX11-NEXT: s_lshl_b64 s[28:29], s[0:1], s16
; GFX11-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27] ; GFX11-NEXT: s_or_b64 s[24:25], s[24:25], s[26:27]
; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s23 ; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], s17
; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_cmp_lg_u32 s30, 0
; GFX11-NEXT: s_cselect_b64 s[16:17], s[16:17], 0 ; GFX11-NEXT: s_cselect_b64 s[26:27], s[28:29], 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[24:25], s[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s29, 0 ; GFX11-NEXT: s_cmp_eq_u32 s16, 0
; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[2:3], s[2:3], s[0:1]
; GFX11-NEXT: s_sub_i32 s26, s22, 64 ; GFX11-NEXT: s_sub_i32 s23, s22, 64
; GFX11-NEXT: s_sub_i32 s23, 64, s22 ; GFX11-NEXT: s_sub_i32 s16, 64, s22
; GFX11-NEXT: s_cmp_lt_u32 s22, 64 ; GFX11-NEXT: s_cmp_lt_u32 s22, 64
; GFX11-NEXT: s_cselect_b32 s27, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s22, 0
; GFX11-NEXT: s_cselect_b32 s28, 1, 0 ; GFX11-NEXT: s_cselect_b32 s28, 1, 0
; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], s22 ; GFX11-NEXT: s_lshr_b64 s[0:1], s[8:9], s22
; GFX11-NEXT: s_lshl_b64 s[24:25], s[10:11], s23 ; GFX11-NEXT: s_lshl_b64 s[16:17], s[10:11], s16
; GFX11-NEXT: s_lshr_b64 s[22:23], s[10:11], s22 ; GFX11-NEXT: s_lshr_b64 s[24:25], s[10:11], s22
; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[24:25] ; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[16:17]
; GFX11-NEXT: s_lshr_b64 s[10:11], s[10:11], s26 ; GFX11-NEXT: s_lshr_b64 s[10:11], s[10:11], s23
; GFX11-NEXT: s_cmp_lg_u32 s27, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11]
; GFX11-NEXT: s_cmp_lg_u32 s28, 0 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], s[10:11]
; GFX11-NEXT: s_cmp_eq_u32 s22, 0
; GFX11-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1] ; GFX11-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX11-NEXT: s_cmp_lg_u32 s27, 0 ; GFX11-NEXT: s_cmp_lg_u32 s28, 0
; GFX11-NEXT: s_cselect_b64 s[8:9], s[22:23], 0 ; GFX11-NEXT: s_cselect_b64 s[8:9], s[24:25], 0
; GFX11-NEXT: s_and_not1_b64 s[10:11], s[18:19], s[20:21] ; GFX11-NEXT: s_and_not1_b64 s[10:11], s[18:19], s[20:21]
; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GFX11-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19] ; GFX11-NEXT: s_and_b64 s[8:9], s[20:21], s[18:19]
; GFX11-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GFX11-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GFX11-NEXT: s_lshr_b32 s18, s5, 31 ; GFX11-NEXT: s_lshr_b32 s18, s5, 31
; GFX11-NEXT: s_or_b64 s[0:1], s[16:17], s[0:1] ; GFX11-NEXT: s_or_b64 s[0:1], s[26:27], s[0:1]
; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], 1 ; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], 1
; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[18:19] ; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[18:19]
; GFX11-NEXT: s_sub_i32 s9, s10, 64 ; GFX11-NEXT: s_sub_i32 s9, s10, 64
; GFX11-NEXT: s_sub_i32 s11, 64, s10 ; GFX11-NEXT: s_sub_i32 s11, 64, s10
; GFX11-NEXT: s_cmp_lt_u32 s10, 64 ; GFX11-NEXT: s_cmp_lt_u32 s10, 64
; GFX11-NEXT: s_cselect_b32 s20, 1, 0 ; GFX11-NEXT: s_cselect_b32 s22, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s10, 0
; GFX11-NEXT: s_cselect_b32 s21, 1, 0
; GFX11-NEXT: s_lshr_b64 s[16:17], s[4:5], s11 ; GFX11-NEXT: s_lshr_b64 s[16:17], s[4:5], s11
; GFX11-NEXT: s_lshl_b64 s[18:19], s[6:7], s10 ; GFX11-NEXT: s_lshl_b64 s[18:19], s[6:7], s10
; GFX11-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX11-NEXT: s_lshl_b64 s[20:21], s[4:5], s10
; GFX11-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GFX11-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s9 ; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
; GFX11-NEXT: s_cmp_lg_u32 s20, 0 ; GFX11-NEXT: s_cmp_lg_u32 s22, 0
; GFX11-NEXT: s_cselect_b64 s[10:11], s[10:11], 0 ; GFX11-NEXT: s_cselect_b64 s[18:19], s[20:21], 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] ; GFX11-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5]
; GFX11-NEXT: s_cmp_lg_u32 s21, 0 ; GFX11-NEXT: s_cmp_eq_u32 s10, 0
; GFX11-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5] ; GFX11-NEXT: s_cselect_b64 s[6:7], s[6:7], s[4:5]
; GFX11-NEXT: s_sub_i32 s18, s8, 64 ; GFX11-NEXT: s_sub_i32 s9, s8, 64
; GFX11-NEXT: s_sub_i32 s9, 64, s8 ; GFX11-NEXT: s_sub_i32 s10, 64, s8
; GFX11-NEXT: s_cmp_lt_u32 s8, 64 ; GFX11-NEXT: s_cmp_lt_u32 s8, 64
; GFX11-NEXT: s_cselect_b32 s19, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: s_cselect_b32 s20, 1, 0 ; GFX11-NEXT: s_cselect_b32 s20, 1, 0
; GFX11-NEXT: s_lshr_b64 s[4:5], s[12:13], s8 ; GFX11-NEXT: s_lshr_b64 s[4:5], s[12:13], s8
; GFX11-NEXT: s_lshl_b64 s[16:17], s[14:15], s9 ; GFX11-NEXT: s_lshl_b64 s[10:11], s[14:15], s10
; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], s8 ; GFX11-NEXT: s_lshr_b64 s[16:17], s[14:15], s8
; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[16:17] ; GFX11-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
; GFX11-NEXT: s_lshr_b64 s[14:15], s[14:15], s18 ; GFX11-NEXT: s_lshr_b64 s[10:11], s[14:15], s9
; GFX11-NEXT: s_cmp_lg_u32 s19, 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], s[14:15]
; GFX11-NEXT: s_cmp_lg_u32 s20, 0 ; GFX11-NEXT: s_cmp_lg_u32 s20, 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[4:5], s[10:11]
; GFX11-NEXT: s_cmp_eq_u32 s8, 0
; GFX11-NEXT: s_cselect_b64 s[4:5], s[12:13], s[4:5] ; GFX11-NEXT: s_cselect_b64 s[4:5], s[12:13], s[4:5]
; GFX11-NEXT: s_cmp_lg_u32 s19, 0 ; GFX11-NEXT: s_cmp_lg_u32 s20, 0
; GFX11-NEXT: s_cselect_b64 s[8:9], s[8:9], 0 ; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], 0
; GFX11-NEXT: s_or_b64 s[4:5], s[10:11], s[4:5] ; GFX11-NEXT: s_or_b64 s[4:5], s[18:19], s[4:5]
; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX11-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) %result = call <2 x i128> @llvm.fshr.v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt)
ret <2 x i128> %result ret <2 x i128> %result
} }
define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) { define <2 x i128> @v_fshr_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %amt) {
; GFX6-LABEL: v_fshr_v2i128: ; GFX6-LABEL: v_fshr_v2i128:
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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir

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# GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1 # GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
# GCN: [[SGPR2:%[0-9]+]]:sreg_32 = COPY $sgpr2 # GCN: [[SGPR2:%[0-9]+]]:sreg_32 = COPY $sgpr2
# GCN: [[SGPR3:%[0-9]+]]:sreg_32 = COPY $sgpr3 # GCN: [[SGPR3:%[0-9]+]]:sreg_32 = COPY $sgpr3
# GCN: [[SGPR4:%[0-9]+]]:sreg_32 = COPY $sgpr4 # GCN: [[SGPR4:%[0-9]+]]:sreg_32 = COPY $sgpr4
# GCN: [[SGPR5:%[0-9]+]]:sreg_32 = COPY $sgpr5 # GCN: [[SGPR5:%[0-9]+]]:sreg_32 = COPY $sgpr5
# GCN: [[SGPR6:%[0-9]+]]:sreg_32 = COPY $sgpr6 # GCN: [[SGPR6:%[0-9]+]]:sreg_32 = COPY $sgpr6
# GCN: [[SGPR7:%[0-9]+]]:sreg_32 = COPY $sgpr7 # GCN: [[SGPR7:%[0-9]+]]:sreg_32 = COPY $sgpr7
# GCN: S_CMP_LG_U32 [[SGPR0]], [[SGPR1]], implicit-def $scc # GCN: S_CMP_LG_U32 [[SGPR0]], [[SGPR1]], implicit-def $scc
# GCN-NEXT: [[COND0:%[0-9]+]]:sreg_32 = COPY $scc
# GCN: S_CMP_LG_U32 [[SGPR4]], [[SGPR5]], implicit-def $scc
# GCN-NEXT: [[COND1:%[0-9]+]]:sreg_32 = COPY $scc
# GCN: $scc = COPY [[COND0]]
# GCN-NEXT: S_CSELECT_B32 [[SGPR6]], [[SGPR7]], implicit $scc # GCN-NEXT: S_CSELECT_B32 [[SGPR6]], [[SGPR7]], implicit $scc
# GCN: $scc = COPY [[COND1]] # GCN: S_CMP_LG_U32 [[SGPR4]], [[SGPR5]], implicit-def $scc
# GCN-NEXT: S_CSELECT_B32 [[SGPR2]], [[SGPR3]], implicit $scc # GCN-NEXT: S_CSELECT_B32 [[SGPR2]], [[SGPR3]], implicit $scc
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7
%0:vgpr(p1) = COPY $vgpr0_vgpr1 %0:vgpr(p1) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir

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; GCN-LABEL: name: select_s32_scc ; GCN-LABEL: name: select_s32_scc
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2 %2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = COPY $sgpr3 %3:sgpr(s32) = COPY $sgpr3
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
%5:sgpr(s32) = G_SELECT %4, %2, %3 %5:sgpr(s32) = G_SELECT %4, %2, %3
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; GCN-LABEL: name: select_s64_scc ; GCN-LABEL: name: select_s64_scc
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s64) = COPY $sgpr2_sgpr3 %2:sgpr(s64) = COPY $sgpr2_sgpr3
%3:sgpr(s64) = COPY $sgpr4_sgpr5 %3:sgpr(s64) = COPY $sgpr4_sgpr5
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
%5:sgpr(s64) = G_SELECT %4, %2, %3 %5:sgpr(s64) = G_SELECT %4, %2, %3
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; GCN-LABEL: name: select_p0_scc ; GCN-LABEL: name: select_p0_scc
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(p0) = COPY $sgpr2_sgpr3 %2:sgpr(p0) = COPY $sgpr2_sgpr3
%3:sgpr(p0) = COPY $sgpr4_sgpr5 %3:sgpr(p0) = COPY $sgpr4_sgpr5
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
%5:sgpr(p0) = G_SELECT %4, %2, %3 %5:sgpr(p0) = G_SELECT %4, %2, %3
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; GCN-LABEL: name: select_p1_scc ; GCN-LABEL: name: select_p1_scc
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(p1) = COPY $sgpr2_sgpr3 %2:sgpr(p1) = COPY $sgpr2_sgpr3
%3:sgpr(p1) = COPY $sgpr4_sgpr5 %3:sgpr(p1) = COPY $sgpr4_sgpr5
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
%5:sgpr(p1) = G_SELECT %4, %2, %3 %5:sgpr(p1) = G_SELECT %4, %2, %3
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; GCN-LABEL: name: select_p999_scc ; GCN-LABEL: name: select_p999_scc
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(p999) = COPY $sgpr2_sgpr3 %2:sgpr(p999) = COPY $sgpr2_sgpr3
%3:sgpr(p999) = COPY $sgpr4_sgpr5 %3:sgpr(p999) = COPY $sgpr4_sgpr5
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
%5:sgpr(p999) = G_SELECT %4, %2, %3 %5:sgpr(p999) = G_SELECT %4, %2, %3
Show All 13 Lines bb.0:
; GCN-LABEL: name: select_v4s16_scc ; GCN-LABEL: name: select_v4s16_scc
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3 %2:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
%3:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5 %3:sgpr(<4 x s16>) = COPY $sgpr4_sgpr5
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
%5:sgpr(<4 x s16>) = G_SELECT %4, %2, %3 %5:sgpr(<4 x s16>) = G_SELECT %4, %2, %3
Show All 13 Lines bb.0:
; GCN-LABEL: name: select_s16_scc ; GCN-LABEL: name: select_s16_scc
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GCN-NEXT: S_CMP_EQ_U32 [[COPY2]], [[COPY3]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY2]], [[COPY3]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY]], [[COPY1]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2 %2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = COPY $sgpr3 %3:sgpr(s32) = COPY $sgpr3
%4:sgpr(s16) = G_TRUNC %0 %4:sgpr(s16) = G_TRUNC %0
%5:sgpr(s16) = G_TRUNC %1 %5:sgpr(s16) = G_TRUNC %1
Show All 15 Lines bb.0:
; GCN-LABEL: name: select_v2s16_scc ; GCN-LABEL: name: select_v2s16_scc
; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[COPY3]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<2 x s16>) = COPY $sgpr2 %2:sgpr(<2 x s16>) = COPY $sgpr2
%3:sgpr(<2 x s16>) = COPY $sgpr3 %3:sgpr(<2 x s16>) = COPY $sgpr3
%4:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1
%5:sgpr(<2 x s16>) = G_SELECT %4, %2, %3 %5:sgpr(<2 x s16>) = G_SELECT %4, %2, %3
▲ Show 20 Lines • Show All 295 Lines • ▼ Show 20 Lines bb.0:
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_XOR_B32_]], [[COPY3]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[S_XOR_B32_]], [[COPY3]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2 %2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = COPY $sgpr3 %3:sgpr(s32) = COPY $sgpr3
%4:sgpr(s32) = G_FNEG %2 %4:sgpr(s32) = G_FNEG %2
%5:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %5:sgpr(s32) = G_ICMP intpred(eq), %0, %1
Show All 16 Lines bb.0:
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def $scc ; GCN-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def $scc
; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc ; GCN-NEXT: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc
; GCN-NEXT: $scc = COPY [[COPY4]]
; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[S_XOR_B32_]], implicit $scc ; GCN-NEXT: [[S_CSELECT_B32_:%[0-9]+]]:sreg_32 = S_CSELECT_B32 [[COPY2]], [[S_XOR_B32_]], implicit $scc
; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]] ; GCN-NEXT: S_ENDPGM 0, implicit [[S_CSELECT_B32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2 %2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = COPY $sgpr3 %3:sgpr(s32) = COPY $sgpr3
%4:sgpr(s32) = G_FNEG %3 %4:sgpr(s32) = G_FNEG %3
%5:sgpr(s32) = G_ICMP intpred(eq), %0, %1 %5:sgpr(s32) = G_ICMP intpred(eq), %0, %1
%6:sgpr(s32) = G_SELECT %5, %2, %4 %6:sgpr(s32) = G_SELECT %5, %2, %4
S_ENDPGM 0, implicit %6 S_ENDPGM 0, implicit %6
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

Show First 20 Lines • Show All 1,744 Lines • ▼ Show 20 Lines; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = lshr i65 %value, 33 %result = lshr i65 %value, 33
ret i65 %result ret i65 %result
} }
define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) { define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) {
; GCN-LABEL: s_lshr_i65: ; GCN-LABEL: s_lshr_i65:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_and_b64 s[4:5], s[2:3], 1 ; GCN-NEXT: s_and_b64 s[4:5], s[2:3], 1
; GCN-NEXT: s_sub_i32 s10, s3, 64 ; GCN-NEXT: s_sub_i32 s2, s3, 64
; GCN-NEXT: s_sub_i32 s8, 64, s3 ; GCN-NEXT: s_sub_i32 s10, 64, s3
; GCN-NEXT: s_cmp_lt_u32 s3, 64 ; GCN-NEXT: s_cmp_lt_u32 s3, 64
; GCN-NEXT: s_cselect_b32 s11, 1, 0
; GCN-NEXT: s_cmp_eq_u32 s3, 0
; GCN-NEXT: s_cselect_b32 s12, 1, 0 ; GCN-NEXT: s_cselect_b32 s12, 1, 0
; GCN-NEXT: s_lshr_b64 s[8:9], s[0:1], s3
; GCN-NEXT: s_lshl_b64 s[10:11], s[4:5], s10
; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s3 ; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s3
; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3 ; GCN-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11]
; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 ; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s2
; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9] ; GCN-NEXT: s_cmp_lg_u32 s12, 0
; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s10 ; GCN-NEXT: s_cselect_b64 s[4:5], s[8:9], s[4:5]
; GCN-NEXT: s_cmp_lg_u32 s11, 0 ; GCN-NEXT: s_cmp_eq_u32 s3, 0
; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] ; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_cmp_lg_u32 s12, 0
; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s11, 0
; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], 0 ; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], 0
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_lshr_i65: ; GFX10PLUS-LABEL: s_lshr_i65:
; GFX10PLUS: ; %bb.0: ; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_and_b64 s[4:5], s[2:3], 1 ; GFX10PLUS-NEXT: s_and_b64 s[4:5], s[2:3], 1
; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 64 ; GFX10PLUS-NEXT: s_sub_i32 s2, s3, 64
; GFX10PLUS-NEXT: s_sub_i32 s2, 64, s3 ; GFX10PLUS-NEXT: s_sub_i32 s8, 64, s3
; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64 ; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64
; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0
; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0
; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0 ; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0
; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s3 ; GFX10PLUS-NEXT: s_lshr_b64 s[6:7], s[0:1], s3
; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s2 ; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[4:5], s8
; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[4:5], s3 ; GFX10PLUS-NEXT: s_lshr_b64 s[10:11], s[4:5], s3
; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GFX10PLUS-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[4:5], s10 ; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[4:5], s2
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5] ; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], 0 ; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[10:11], 0
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10PLUS-NEXT: ; return to shader part epilog
%result = lshr i65 %value, %amount %result = lshr i65 %value, %amount
ret i65 %result ret i65 %result
} }
define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) { define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) {
; GCN-LABEL: s_lshr_i65_33: ; GCN-LABEL: s_lshr_i65_33:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
Show All 31 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

Show First 20 Lines • Show All 1,718 Lines • ▼ Show 20 Lines
define amdgpu_ps i65 @s_shl_i65(i65 inreg %value, i65 inreg %amount) { define amdgpu_ps i65 @s_shl_i65(i65 inreg %value, i65 inreg %amount) {
; GCN-LABEL: s_shl_i65: ; GCN-LABEL: s_shl_i65:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_sub_i32 s10, s3, 64 ; GCN-NEXT: s_sub_i32 s10, s3, 64
; GCN-NEXT: s_sub_i32 s6, 64, s3 ; GCN-NEXT: s_sub_i32 s6, 64, s3
; GCN-NEXT: s_cmp_lt_u32 s3, 64 ; GCN-NEXT: s_cmp_lt_u32 s3, 64
; GCN-NEXT: s_cselect_b32 s11, 1, 0 ; GCN-NEXT: s_cselect_b32 s11, 1, 0
; GCN-NEXT: s_cmp_eq_u32 s3, 0
; GCN-NEXT: s_cselect_b32 s12, 1, 0
; GCN-NEXT: s_lshr_b64 s[6:7], s[0:1], s6 ; GCN-NEXT: s_lshr_b64 s[6:7], s[0:1], s6
; GCN-NEXT: s_lshl_b64 s[8:9], s[2:3], s3 ; GCN-NEXT: s_lshl_b64 s[8:9], s[2:3], s3
; GCN-NEXT: s_lshl_b64 s[4:5], s[0:1], s3 ; GCN-NEXT: s_lshl_b64 s[4:5], s[0:1], s3
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9] ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GCN-NEXT: s_lshl_b64 s[8:9], s[0:1], s10 ; GCN-NEXT: s_lshl_b64 s[8:9], s[0:1], s10
; GCN-NEXT: s_cmp_lg_u32 s11, 0 ; GCN-NEXT: s_cmp_lg_u32 s11, 0
; GCN-NEXT: s_cselect_b64 s[0:1], s[4:5], 0 ; GCN-NEXT: s_cselect_b64 s[0:1], s[4:5], 0
; GCN-NEXT: s_cselect_b64 s[4:5], s[6:7], s[8:9] ; GCN-NEXT: s_cselect_b64 s[4:5], s[6:7], s[8:9]
; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_cmp_eq_u32 s3, 0
; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] ; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
; ;
; GFX10PLUS-LABEL: s_shl_i65: ; GFX10PLUS-LABEL: s_shl_i65:
; GFX10PLUS: ; %bb.0: ; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 64 ; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 64
; GFX10PLUS-NEXT: s_sub_i32 s4, 64, s3 ; GFX10PLUS-NEXT: s_sub_i32 s4, 64, s3
; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64 ; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 64
; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0 ; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 0
; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0
; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 0
; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[0:1], s4 ; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[0:1], s4
; GFX10PLUS-NEXT: s_lshl_b64 s[6:7], s[2:3], s3 ; GFX10PLUS-NEXT: s_lshl_b64 s[6:7], s[2:3], s3
; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[0:1], s3 ; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[0:1], s3
; GFX10PLUS-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GFX10PLUS-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GFX10PLUS-NEXT: s_lshl_b64 s[6:7], s[0:1], s10 ; GFX10PLUS-NEXT: s_lshl_b64 s[6:7], s[0:1], s10
; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[8:9], 0 ; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[8:9], 0
; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7] ; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[4:5], s[6:7]
; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 0 ; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 0
; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] ; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
; GFX10PLUS-NEXT: ; return to shader part epilog ; GFX10PLUS-NEXT: ; return to shader part epilog
%result = shl i65 %value, %amount %result = shl i65 %value, %amount
ret i65 %result ret i65 %result
} }
define amdgpu_ps i65 @s_shl_i65_33(i65 inreg %value) { define amdgpu_ps i65 @s_shl_i65_33(i65 inreg %value) {
; GCN-LABEL: s_shl_i65_33: ; GCN-LABEL: s_shl_i65_33:
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llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

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; GFX6-LABEL: s_uaddsat_i48: ; GFX6-LABEL: s_uaddsat_i48:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_add_u32 s0, s0, s2 ; GFX6-NEXT: s_add_u32 s0, s0, s2
; GFX6-NEXT: s_cselect_b32 s2, 1, 0 ; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s1, s1, 0xffff ; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
; GFX6-NEXT: s_and_b32 s3, s3, 0xffff ; GFX6-NEXT: s_and_b32 s3, s3, 0xffff
; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0
; GFX6-NEXT: s_addc_u32 s2, s1, s3 ; GFX6-NEXT: s_addc_u32 s2, s1, s3
; GFX6-NEXT: s_and_b32 s1, s2, 0xffff
; GFX6-NEXT: s_cmp_lg_u32 s2, s1
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_lshr_b32 s3, s0, 16 ; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff ; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s1, s2, 0xffff
; GFX6-NEXT: s_or_b32 s0, s0, s3 ; GFX6-NEXT: s_or_b32 s0, s0, s3
; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_cmp_lg_u32 s2, s1
; GFX6-NEXT: s_cselect_b64 s[0:1], -1, s[0:1] ; GFX6-NEXT: s_cselect_b64 s[0:1], -1, s[0:1]
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_uaddsat_i48: ; GFX8-LABEL: s_uaddsat_i48:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 16 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GFX8-NEXT: s_add_u32 s0, s0, s2 ; GFX8-NEXT: s_add_u32 s0, s0, s2
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llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

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; GFX6-LABEL: s_usubsat_i48: ; GFX6-LABEL: s_usubsat_i48:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s0, s0, s2 ; GFX6-NEXT: s_sub_u32 s0, s0, s2
; GFX6-NEXT: s_cselect_b32 s2, 1, 0 ; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s1, s1, 0xffff ; GFX6-NEXT: s_and_b32 s1, s1, 0xffff
; GFX6-NEXT: s_and_b32 s3, s3, 0xffff ; GFX6-NEXT: s_and_b32 s3, s3, 0xffff
; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0
; GFX6-NEXT: s_subb_u32 s2, s1, s3 ; GFX6-NEXT: s_subb_u32 s2, s1, s3
; GFX6-NEXT: s_and_b32 s1, s2, 0xffff
; GFX6-NEXT: s_cmp_lg_u32 s2, s1
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_lshr_b32 s3, s0, 16 ; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_and_b32 s0, s0, 0xffff ; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: s_lshl_b32 s3, s3, 16 ; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s1, s2, 0xffff
; GFX6-NEXT: s_or_b32 s0, s0, s3 ; GFX6-NEXT: s_or_b32 s0, s0, s3
; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_cmp_lg_u32 s2, s1
; GFX6-NEXT: s_cselect_b64 s[0:1], 0, s[0:1] ; GFX6-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_usubsat_i48: ; GFX8-LABEL: s_usubsat_i48:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 ; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 16
; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 16 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
; GFX8-NEXT: s_sub_u32 s0, s0, s2 ; GFX8-NEXT: s_sub_u32 s0, s0, s2
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llvm/test/CodeGen/AMDGPU/fptrunc.ll

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; VI-SAFE-GISEL-NEXT: s_lshr_b32 s5, s3, 8 ; VI-SAFE-GISEL-NEXT: s_lshr_b32 s5, s3, 8
; VI-SAFE-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff ; VI-SAFE-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff
; VI-SAFE-GISEL-NEXT: s_addk_i32 s4, 0xfc10 ; VI-SAFE-GISEL-NEXT: s_addk_i32 s4, 0xfc10
; VI-SAFE-GISEL-NEXT: s_and_b32 s5, s5, 0xffe ; VI-SAFE-GISEL-NEXT: s_and_b32 s5, s5, 0xffe
; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s6, s2 ; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s6, s2
; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0 ; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; VI-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0 ; VI-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0
; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s5, s2 ; VI-SAFE-GISEL-NEXT: s_or_b32 s2, s5, s2
; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; VI-SAFE-GISEL-NEXT: s_movk_i32 s5, 0x7e00 ; VI-SAFE-GISEL-NEXT: s_movk_i32 s5, 0x7e00
; VI-SAFE-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; VI-SAFE-GISEL-NEXT: s_cselect_b32 s5, s5, 0x7c00 ; VI-SAFE-GISEL-NEXT: s_cselect_b32 s5, s5, 0x7c00
; VI-SAFE-GISEL-NEXT: s_sub_i32 s7, 1, s4 ; VI-SAFE-GISEL-NEXT: s_sub_i32 s7, 1, s4
; VI-SAFE-GISEL-NEXT: s_lshl_b32 s6, s4, 12 ; VI-SAFE-GISEL-NEXT: s_lshl_b32 s6, s4, 12
; VI-SAFE-GISEL-NEXT: s_max_i32 s7, s7, 0 ; VI-SAFE-GISEL-NEXT: s_max_i32 s7, s7, 0
; VI-SAFE-GISEL-NEXT: s_or_b32 s6, s2, s6 ; VI-SAFE-GISEL-NEXT: s_or_b32 s6, s2, s6
; VI-SAFE-GISEL-NEXT: s_min_i32 s7, s7, 13 ; VI-SAFE-GISEL-NEXT: s_min_i32 s7, s7, 13
; VI-SAFE-GISEL-NEXT: s_bitset1_b32 s2, 12 ; VI-SAFE-GISEL-NEXT: s_bitset1_b32 s2, 12
; VI-SAFE-GISEL-NEXT: s_lshr_b32 s8, s2, s7 ; VI-SAFE-GISEL-NEXT: s_lshr_b32 s8, s2, s7
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