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Differential D155891

AMDGPU: Filter out contract flags when lowering exp
ClosedPublic

Authored by arsenm on Jul 20 2023, 2:49 PM.

Details

Reviewers
rampitec
foad
Pierre-vh
b-sumner
Group Reviewers
Restricted Project
Summary

It is unsafe to contract the fsub into the fmul. It also increases
code size by duplicating a constant.

Diff Detail

Event Timeline

arsenm created this revision.Jul 20 2023, 2:49 PM
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arsenm requested review of this revision.Jul 20 2023, 2:49 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 20 2023, 2:49 PM
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rampitec accepted this revision.Jul 20 2023, 2:52 PM
This revision is now accepted and ready to land.Jul 20 2023, 2:52 PM
arsenm closed this revision.Jul 20 2023, 3:14 PM

02955132380e5e2b6f44b1277c15178e343b63b3

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
7 lines
8 lines
test/
CodeGen/
AMDGPU/
272 lines

Diff 542687

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 2,822 Lines • ▼ Show 20 LinesSDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
// (2^(j/64)) is precomputed // (2^(j/64)) is precomputed
// //
// e^r = 1 + r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5! // e^r = 1 + r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5!
// e^r = 1 + q // e^r = 1 + q
// //
// q = r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5! // q = r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5!
// //
// e^x = (2^m) * ( (2^(j/64)) + q*(2^(j/64)) ) // e^x = (2^m) * ( (2^(j/64)) + q*(2^(j/64)) )
SDNodeFlags FlagsNoContract = Flags;
FlagsNoContract.setAllowContract(false);
SDValue PH, PL; SDValue PH, PL;
if (Subtarget->hasFastFMAF32()) { if (Subtarget->hasFastFMAF32()) {
const float c_exp = numbers::log2ef; const float c_exp = numbers::log2ef;
const float cc_exp = 0x1.4ae0bep-26f; // c+cc are 49 bits const float cc_exp = 0x1.4ae0bep-26f; // c+cc are 49 bits
const float c_exp10 = 0x1.a934f0p+1f; const float c_exp10 = 0x1.a934f0p+1f;
const float cc_exp10 = 0x1.2f346ep-24f; const float cc_exp10 = 0x1.2f346ep-24f;
Show All 23 Lines if (Subtarget->hasFastFMAF32()) {
PH = DAG.getNode(ISD::FMUL, SL, VT, XH, CH, Flags); PH = DAG.getNode(ISD::FMUL, SL, VT, XH, CH, Flags);
SDValue XLCL = DAG.getNode(ISD::FMUL, SL, VT, XL, CL, Flags); SDValue XLCL = DAG.getNode(ISD::FMUL, SL, VT, XL, CL, Flags);
SDValue Mad0 = getMad(DAG, SL, VT, XL, CH, XLCL, Flags); SDValue Mad0 = getMad(DAG, SL, VT, XL, CH, XLCL, Flags);
PL = getMad(DAG, SL, VT, XH, CL, Mad0, Flags); PL = getMad(DAG, SL, VT, XH, CL, Mad0, Flags);
} }
SDValue E = DAG.getNode(ISD::FRINT, SL, VT, PH, Flags); SDValue E = DAG.getNode(ISD::FRINT, SL, VT, PH, Flags);
SDValue PHSubE = DAG.getNode(ISD::FSUB, SL, VT, PH, E, Flags);
// It is unsafe to constract this fsub into the PH multiply.
SDValue PHSubE = DAG.getNode(ISD::FSUB, SL, VT, PH, E, FlagsNoContract);
SDValue A = DAG.getNode(ISD::FADD, SL, VT, PHSubE, PL, Flags); SDValue A = DAG.getNode(ISD::FADD, SL, VT, PHSubE, PL, Flags);
SDValue IntE = DAG.getNode(ISD::FP_TO_SINT, SL, MVT::i32, E); SDValue IntE = DAG.getNode(ISD::FP_TO_SINT, SL, MVT::i32, E);
SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, A, Flags); SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, A, Flags);
SDValue R = DAG.getNode(ISD::FLDEXP, SL, VT, Exp2, IntE, Flags); SDValue R = DAG.getNode(ISD::FLDEXP, SL, VT, Exp2, IntE, Flags);
SDValue UnderflowCheckConst = SDValue UnderflowCheckConst =
DAG.getConstantFP(IsExp10 ? -0x1.66d3e8p+5f : -0x1.9d1da0p+6f, SL, VT); DAG.getConstantFP(IsExp10 ? -0x1.66d3e8p+5f : -0x1.9d1da0p+6f, SL, VT);
▲ Show 20 Lines • Show All 2,854 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 3,306 Lines • ▼ Show 20 Linesbool AMDGPULegalizerInfo::legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst,
return true; return true;
} }
bool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI, bool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI,
MachineIRBuilder &B) const { MachineIRBuilder &B) const {
Register Dst = MI.getOperand(0).getReg(); Register Dst = MI.getOperand(0).getReg();
Register X = MI.getOperand(1).getReg(); Register X = MI.getOperand(1).getReg();
unsigned Flags = MI.getFlags(); const unsigned Flags = MI.getFlags();
MachineFunction &MF = B.getMF(); MachineFunction &MF = B.getMF();
MachineRegisterInfo &MRI = *B.getMRI(); MachineRegisterInfo &MRI = *B.getMRI();
LLT Ty = MRI.getType(Dst); LLT Ty = MRI.getType(Dst);
const LLT F16 = LLT::scalar(16); const LLT F16 = LLT::scalar(16);
const LLT F32 = LLT::scalar(32); const LLT F32 = LLT::scalar(32);
const bool IsExp10 = false; // TODO: For some reason exp10 is missing const bool IsExp10 = false; // TODO: For some reason exp10 is missing
if (Ty == F16) { if (Ty == F16) {
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesbool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI,
// (2^(j/64)) is precomputed // (2^(j/64)) is precomputed
// //
// e^r = 1 + r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5! // e^r = 1 + r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5!
// e^r = 1 + q // e^r = 1 + q
// //
// q = r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5! // q = r + (r^2)/2! + (r^3)/3! + (r^4)/4! + (r^5)/5!
// //
// e^x = (2^m) * ( (2^(j/64)) + q*(2^(j/64)) ) // e^x = (2^m) * ( (2^(j/64)) + q*(2^(j/64)) )
const unsigned FlagsNoContract = Flags & ~MachineInstr::FmContract;
Register PH, PL; Register PH, PL;
if (ST.hasFastFMAF32()) { if (ST.hasFastFMAF32()) {
const float c_exp = numbers::log2ef; const float c_exp = numbers::log2ef;
const float cc_exp = 0x1.4ae0bep-26f; // c+cc are 49 bits const float cc_exp = 0x1.4ae0bep-26f; // c+cc are 49 bits
const float c_exp10 = 0x1.a934f0p+1f; const float c_exp10 = 0x1.a934f0p+1f;
const float cc_exp10 = 0x1.2f346ep-24f; const float cc_exp10 = 0x1.2f346ep-24f;
Show All 22 Lines if (ST.hasFastFMAF32()) {
auto XLCL = B.buildFMul(Ty, XL, CL, Flags); auto XLCL = B.buildFMul(Ty, XL, CL, Flags);
Register Mad0 = Register Mad0 =
getMad(B, Ty, XL.getReg(0), CH.getReg(0), XLCL.getReg(0), Flags); getMad(B, Ty, XL.getReg(0), CH.getReg(0), XLCL.getReg(0), Flags);
PL = getMad(B, Ty, XH.getReg(0), CL.getReg(0), Mad0, Flags); PL = getMad(B, Ty, XH.getReg(0), CL.getReg(0), Mad0, Flags);
} }
auto E = B.buildFRint(Ty, PH, Flags); auto E = B.buildFRint(Ty, PH, Flags);
auto PHSubE = B.buildFSub(Ty, PH, E, Flags);
// It is unsafe to contract this fsub into the PH multiply.
auto PHSubE = B.buildFSub(Ty, PH, E, FlagsNoContract);
auto A = B.buildFAdd(Ty, PHSubE, PL, Flags); auto A = B.buildFAdd(Ty, PHSubE, PL, Flags);
auto IntE = B.buildFPTOSI(LLT::scalar(32), E); auto IntE = B.buildFPTOSI(LLT::scalar(32), E);
auto Exp2 = B.buildIntrinsic(Intrinsic::amdgcn_exp2, {Ty}, false) auto Exp2 = B.buildIntrinsic(Intrinsic::amdgcn_exp2, {Ty}, false)
.addUse(A.getReg(0)) .addUse(A.getReg(0))
.setMIFlags(Flags); .setMIFlags(Flags);
auto R = B.buildFLdexp(Ty, Exp2, IntE, Flags); auto R = B.buildFLdexp(Ty, Exp2, IntE, Flags);
▲ Show 20 Lines • Show All 3,304 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.exp.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,253 Lines • ▼ Show 20 Lines
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31] ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-SDAG-LABEL: v_exp_f32_fast: ; GFX900-SDAG-LABEL: v_exp_f32_fast:
; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v2, v1 ; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_fast: ; GFX900-GISEL-LABEL: v_exp_f32_fast:
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
; GFX900-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2 ; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v2, v1 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_fast: ; SI-SDAG-LABEL: v_exp_f32_fast:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; SI-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; SI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_fast: ; SI-GISEL-LABEL: v_exp_f32_fast:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v1
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
; SI-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1
; SI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2 ; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_exp_f32_fast: ; R600-LABEL: v_exp_f32_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
▲ Show 20 Lines • Show All 3,123 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_fast: ; SI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_fast:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f
; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v1
; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
; SI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_fast: ; SI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_fast:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
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; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 ; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31] ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-SDAG-LABEL: v_exp_f32_contract: ; GFX900-SDAG-LABEL: v_exp_f32_contract:
; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v2, v1 ; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 ; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_contract: ; GFX900-GISEL-LABEL: v_exp_f32_contract:
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
; GFX900-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2 ; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v2, v1 ; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 ; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_contract: ; SI-SDAG-LABEL: v_exp_f32_contract:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; SI-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; SI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 ; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_contract: ; SI-GISEL-LABEL: v_exp_f32_contract:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v1
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
; SI-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1
; SI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2 ; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 ; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
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; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 ; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31] ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-SDAG-LABEL: v_exp_f32_contract_daz: ; GFX900-SDAG-LABEL: v_exp_f32_contract_daz:
; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v2, v1 ; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 ; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_contract_daz: ; GFX900-GISEL-LABEL: v_exp_f32_contract_daz:
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
; GFX900-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2 ; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v2, v1 ; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 ; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_contract_daz: ; SI-SDAG-LABEL: v_exp_f32_contract_daz:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; SI-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; SI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000 ; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0 ; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_contract_daz: ; SI-GISEL-LABEL: v_exp_f32_contract_daz:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v1
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
; SI-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1
; SI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2 ; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2 ; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
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; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc ; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31] ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-SDAG-LABEL: v_exp_f32_contract_nnan_ninf: ; GFX900-SDAG-LABEL: v_exp_f32_contract_nnan_ninf:
; GFX900-SDAG: ; %bb.0: ; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v2, v1 ; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_contract_nnan_ninf: ; GFX900-GISEL-LABEL: v_exp_f32_contract_nnan_ninf:
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
; GFX900-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2 ; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v2, v1 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_contract_nnan_ninf: ; SI-SDAG-LABEL: v_exp_f32_contract_nnan_ninf:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; SI-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; SI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2 ; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0 ; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_contract_nnan_ninf: ; SI-GISEL-LABEL: v_exp_f32_contract_nnan_ninf:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f
; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v1
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2
; SI-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1
; SI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2 ; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc ; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_exp_f32_contract_nnan_ninf: ; R600-LABEL: v_exp_f32_contract_nnan_ninf:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
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