[libc] RISC-V V extension memory functions

[gchatelet]

Summary

This is just a POC, it is not tested as I don't have access to real hardware.

[gchatelet]

• Integrate vext
• Add RISCV VEXT feature detection

[gchatelet]

• Add all memfunctions for riscv with vext
• Ensure the subtraction is done with int instead of uint8

libc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake

 # ------------------------------------------------------------------------------
 # Cpu features definition and flags
 # ------------------------------------------------------------------------------
 
 # Initialize ALL_CPU_FEATURES as empty list.
 set(ALL_CPU_FEATURES "")
 
 if(${LIBC_TARGET_ARCHITECTURE_IS_X86})
   set(ALL_CPU_FEATURES SSE2 SSE4_2 AVX AVX2 AVX512F AVX512BW FMA)
   set(LIBC_COMPILE_OPTIONS_NATIVE -march=native)
+elseif(${LIBC_TARGET_ARCHITECTURE_IS_RISCV64})
+  set(ALL_CPU_FEATURES RISCV_VEXT)
+  set(LIBC_COMPILE_OPTIONS_NATIVE -mcpu=native)
 elseif(${LIBC_TARGET_ARCHITECTURE_IS_AARCH64})
   set(LIBC_COMPILE_OPTIONS_NATIVE -mcpu=native)
 endif()
 
 # Making sure ALL_CPU_FEATURES is sorted.
 list(SORT ALL_CPU_FEATURES)
 
 # Function to check whether the target CPU supports the provided set of features.
foreach(element IN LISTS list1)
     if("${list2}" MATCHES "(^|;)${element}(;|$)")
       list(APPEND tmp "${element}")
     endif()
   endforeach()
   set(${output_var} ${tmp} PARENT_SCOPE)
 endfunction()
 
 set(AVAILABLE_CPU_FEATURES "")
-if(LIBC_CROSSBUILD)
+
+if(LIBC_CROSSBUILD OR CMAKE_CROSSCOMPILING)
   # If we are doing a cross build, we will just assume that all CPU features
   # are available.
   set(AVAILABLE_CPU_FEATURES ${ALL_CPU_FEATURES})
 else()
   # Try compile a C file to check if flag is supported.
   set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
   foreach(feature IN LISTS ALL_CPU_FEATURES)
     try_compile(

libc/cmake/modules/cpu_features/check_RISCV_VEXT.cpp

+#include "src/__support/macros/properties/cpu_features.h"
+
+#ifndef LIBC_TARGET_CPU_HAS_RISCV_VEXT
+#error unsupported
+#endif

libc/src/__support/macros/properties/cpu_features.h

 #if defined(__AVX512F__)
 #define LIBC_TARGET_CPU_HAS_AVX512F
 #endif
 
 #if defined(__AVX512BW__)
 #define LIBC_TARGET_CPU_HAS_AVX512BW
 #endif
 
+#if defined(__riscv_vector)
+#define LIBC_TARGET_CPU_HAS_RISCV_VEXT
+#endif
+
 #if defined(__ARM_FEATURE_FMA) || (defined(__AVX2__) && defined(__FMA__)) ||   \
     defined(__NVPTX__) || defined(__AMDGPU__) || defined(__LIBC_RISCV_USE_FMA)
 #define LIBC_TARGET_CPU_HAS_FMA
 #endif
 
 #if defined(LIBC_TARGET_ARCH_IS_AARCH64) ||                                    \
     (defined(LIBC_TARGET_ARCH_IS_X86_64) &&                                    \
      defined(LIBC_TARGET_CPU_HAS_SSE4_2))
 #define LIBC_TARGET_CPU_HAS_NEAREST_INT
 #endif
 
 #endif // LLVM_LIBC_SRC_SUPPORT_MACROS_PROPERTIES_CPU_FEATURES_H

libc/src/string/CMakeLists.txt

 
 if(${LIBC_TARGET_ARCHITECTURE_IS_X86})
   add_bcmp(bcmp_x86_64_opt_sse2   COMPILE_OPTIONS -march=k8             REQUIRE SSE2)
   add_bcmp(bcmp_x86_64_opt_sse4   COMPILE_OPTIONS -march=nehalem        REQUIRE SSE4_2)
   add_bcmp(bcmp_x86_64_opt_avx2   COMPILE_OPTIONS -march=haswell        REQUIRE AVX2)
   add_bcmp(bcmp_x86_64_opt_avx512 COMPILE_OPTIONS -march=skylake-avx512 REQUIRE AVX512BW)
   add_bcmp(bcmp_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_bcmp(bcmp)
+elseif(LIBC_TARGET_ARCHITECTURE_IS_RISCV64)
+  add_bcmp(bcmp_riscv64_vext COMPILE_OPTIONS -march=rv64idzve32x1p0 REQUIRE RISCV_VEXT)
+  add_bcmp(bcmp)
 else()
   add_bcmp(bcmp_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_bcmp(bcmp)
 endif()
 
 # ------------------------------------------------------------------------------
 # bzero
 # ------------------------------------------------------------------------------

 
 if(${LIBC_TARGET_ARCHITECTURE_IS_X86})
   add_bzero(bzero_x86_64_opt_sse2   COMPILE_OPTIONS -march=k8             REQUIRE SSE2)
   add_bzero(bzero_x86_64_opt_sse4   COMPILE_OPTIONS -march=nehalem        REQUIRE SSE4_2)
   add_bzero(bzero_x86_64_opt_avx2   COMPILE_OPTIONS -march=haswell        REQUIRE AVX2)
   add_bzero(bzero_x86_64_opt_avx512 COMPILE_OPTIONS -march=skylake-avx512 REQUIRE AVX512F)
   add_bzero(bzero_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_bzero(bzero)
+elseif(LIBC_TARGET_ARCHITECTURE_IS_RISCV64)
+  add_bzero(bzero_riscv64_vext COMPILE_OPTIONS -march=rv64idzve32x1p0 REQUIRE RISCV_VEXT)
+  add_bzero(bzero)
 else()
   add_bzero(bzero_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_bzero(bzero)
 endif()
 
 # ------------------------------------------------------------------------------
 # memcmp
 # ------------------------------------------------------------------------------
if(${LIBC_TARGET_ARCHITECTURE_IS_X86})
   add_memcmp(memcmp_x86_64_opt_sse4   COMPILE_OPTIONS -march=nehalem        REQUIRE SSE4_2)
   add_memcmp(memcmp_x86_64_opt_avx2   COMPILE_OPTIONS -march=haswell        REQUIRE AVX2)
   add_memcmp(memcmp_x86_64_opt_avx512 COMPILE_OPTIONS -march=skylake-avx512 REQUIRE AVX512BW)
   add_memcmp(memcmp_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memcmp(memcmp)
 elseif(${LIBC_TARGET_ARCHITECTURE_IS_AARCH64})
   add_memcmp(memcmp_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memcmp(memcmp)
+elseif(LIBC_TARGET_ARCHITECTURE_IS_RISCV64)
+  add_memcmp(memcmp_riscv64_vext COMPILE_OPTIONS -march=rv64idzve32x1p0 REQUIRE RISCV_VEXT)
+  add_memcmp(memcmp)
 else()
   add_memcmp(memcmp_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memcmp(memcmp)
 endif()
 
 # ------------------------------------------------------------------------------
 # memcpy
 # ------------------------------------------------------------------------------
if(${LIBC_TARGET_ARCHITECTURE_IS_X86})
   add_memcpy(memcpy_x86_64_opt_sw_prefetch_avx    COMPILE_OPTIONS -DLIBC_COPT_MEMCPY_X86_USE_SOFTWARE_PREFETCHING -march=sandybridge    REQUIRE AVX)
   add_memcpy(memcpy_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memcpy(memcpy)
 elseif(${LIBC_TARGET_ARCHITECTURE_IS_AARCH64})
   # Disable tail merging as it leads to lower performance.
   add_memcpy(memcpy_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE}
                                       MLLVM_COMPILE_OPTIONS "-tail-merge-threshold=0")
   add_memcpy(memcpy                   MLLVM_COMPILE_OPTIONS "-tail-merge-threshold=0")
+elseif(LIBC_TARGET_ARCHITECTURE_IS_RISCV64)
+  add_memcpy(memcpy_riscv64_vext COMPILE_OPTIONS -march=rv64idzve32x1p0 REQUIRE RISCV_VEXT)
+  add_memcpy(memcpy)
 else()
   add_memcpy(memcpy_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memcpy(memcpy)
 endif()
 
 # ------------------------------------------------------------------------------
 # memmove
 # ------------------------------------------------------------------------------
if(${LIBC_TARGET_ARCHITECTURE_IS_X86})
   add_memmove(memmove_x86_64_opt_avx512 COMPILE_OPTIONS -march=skylake-avx512 REQUIRE AVX512F)
   add_memmove(memmove_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memmove(memmove)
 elseif(${LIBC_TARGET_ARCHITECTURE_IS_AARCH64})
   # Disable tail merging as it leads to lower performance.
   add_memmove(memmove_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE}
                                         MLLVM_COMPILE_OPTIONS "-tail-merge-threshold=0")
   add_memmove(memmove                   MLLVM_COMPILE_OPTIONS "-tail-merge-threshold=0")
+elseif(LIBC_TARGET_ARCHITECTURE_IS_RISCV64)
+  add_memmove(memmove_riscv64_vext COMPILE_OPTIONS -march=rv64idzve32x1p0 REQUIRE RISCV_VEXT)
+  add_memmove(memmove)
 else()
   add_memmove(memmove_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memmove(memmove)
 endif()
 
 # ------------------------------------------------------------------------------
 # memset
 # ------------------------------------------------------------------------------
if(${LIBC_TARGET_ARCHITECTURE_IS_X86})
   add_memset(memset_x86_64_opt_avx512 COMPILE_OPTIONS -march=skylake-avx512 REQUIRE AVX512F)
   add_memset(memset_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memset(memset)
 elseif(${LIBC_TARGET_ARCHITECTURE_IS_AARCH64})
   # Disable tail merging as it leads to lower performance.
   add_memset(memset_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE}
                                       MLLVM_COMPILE_OPTIONS "-tail-merge-threshold=0")
   add_memset(memset                   MLLVM_COMPILE_OPTIONS "-tail-merge-threshold=0")
+elseif(LIBC_TARGET_ARCHITECTURE_IS_RISCV64)
+  add_memset(memset_riscv64_vext COMPILE_OPTIONS -march=rv64idzve32x1p0 REQUIRE RISCV_VEXT)
+  add_memset(memset)
 else()
   add_memset(memset_opt_host          COMPILE_OPTIONS ${LIBC_COMPILE_OPTIONS_NATIVE})
   add_memset(memset)
 endif()

libc/src/string/memory_utils/riscv/inline_bcmp.h

 //===-- Bcmp implementation for riscv ---------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #ifndef LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_BCMP_H
 #define LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_BCMP_H
 
-#include "src/__support/macros/attributes.h"               // LIBC_INLINE
-#include "src/__support/macros/properties/architectures.h" // LIBC_TARGET_ARCH_IS_RISCV64
+#include "src/__support/macros/attributes.h" // LIBC_INLINE
+#include "src/__support/macros/properties/architectures.h"
+#include "src/__support/macros/properties/cpu_features.h"
 #include "src/string/memory_utils/generic/aligned_access.h"
 #include "src/string/memory_utils/utils.h" // Ptr, CPtr
 
 #include <stddef.h> // size_t
 
+#if defined(LIBC_TARGET_CPU_HAS_RISCV_VEXT)
+#include "src/string/memory_utils/riscv/inline_vext.h"
+#endif // LIBC_TARGET_CPU_HAS_RISCV_VEXT
+
 namespace __llvm_libc {
 
 [[maybe_unused]] LIBC_INLINE BcmpReturnType inline_bcmp_riscv(CPtr p1, CPtr p2,
                                                               size_t count) {
-#if defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_CPU_HAS_RISCV_VEXT)
+  return inline_bcmp_riscv_vext(reinterpret_cast<const uint8_t *>(p1),
+                                reinterpret_cast<const uint8_t *>(p2), count);
+#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
   return inline_bcmp_aligned_access_64bit(p1, p2, count);
 #elif defined(LIBC_TARGET_ARCH_IS_RISCV32)
   return inline_bcmp_aligned_access_32bit(p1, p2, count);
 #else
 #error "Unimplemented"
 #endif
 }
 
 } // namespace __llvm_libc
 
 #endif // LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_BCMP_H

libc/src/string/memory_utils/riscv/inline_memcmp.h

 //===-- Memcmp implementation for riscv -------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #ifndef LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMCMP_H
 #define LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMCMP_H
 
-#include "src/__support/macros/attributes.h"               // LIBC_INLINE
-#include "src/__support/macros/properties/architectures.h" // LIBC_TARGET_ARCH_IS_RISCV64
+#include "src/__support/macros/attributes.h" // LIBC_INLINE
+#include "src/__support/macros/properties/architectures.h"
+#include "src/__support/macros/properties/cpu_features.h"
 #include "src/string/memory_utils/generic/aligned_access.h"
 #include "src/string/memory_utils/utils.h" // Ptr, CPtr
 
 #include <stddef.h> // size_t
 
+#if defined(LIBC_TARGET_CPU_HAS_RISCV_VEXT)
+#include "src/string/memory_utils/riscv/inline_vext.h"
+#endif // LIBC_TARGET_CPU_HAS_RISCV_VEXT
+
 namespace __llvm_libc {
 
 [[maybe_unused]] LIBC_INLINE MemcmpReturnType
 inline_memcmp_riscv(CPtr p1, CPtr p2, size_t count) {
-#if defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_CPU_HAS_RISCV_VEXT)
+  return inline_memcmp_riscv_vext(reinterpret_cast<const uint8_t *>(p1),
+                                  reinterpret_cast<const uint8_t *>(p2), count);
+#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
   return inline_memcmp_aligned_access_64bit(p1, p2, count);
 #elif defined(LIBC_TARGET_ARCH_IS_RISCV32)
   return inline_memcmp_aligned_access_32bit(p1, p2, count);
 #else
 #error "Unimplemented"
 #endif
 }
 
 } // namespace __llvm_libc
 
 #endif // LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMCMP_H

libc/src/string/memory_utils/riscv/inline_memcpy.h

 //===-- Memcpy implementation for riscv -------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #ifndef LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMCPY_H
 #define LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMCPY_H
 
-#include "src/__support/macros/attributes.h"               // LIBC_INLINE
-#include "src/__support/macros/properties/architectures.h" // LIBC_TARGET_ARCH_IS_RISCV64
+#include "src/__support/macros/attributes.h" // LIBC_INLINE
+#include "src/__support/macros/properties/architectures.h"
+#include "src/__support/macros/properties/cpu_features.h"
 #include "src/string/memory_utils/generic/aligned_access.h"
 #include "src/string/memory_utils/utils.h" // Ptr, CPtr
 
 #include <stddef.h> // size_t
 
+#if defined(LIBC_TARGET_CPU_HAS_RISCV_VEXT)
+#include "src/string/memory_utils/riscv/inline_vext.h"
+#endif // LIBC_TARGET_CPU_HAS_RISCV_VEXT
+
 namespace __llvm_libc {
 
 [[maybe_unused]] LIBC_INLINE void
 inline_memcpy_riscv(Ptr __restrict dst, CPtr __restrict src, size_t count) {
-#if defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_CPU_HAS_RISCV_VEXT)
+  return inline_memcpy_riscv_vext(reinterpret_cast<uint8_t *>(dst),
+                                  reinterpret_cast<const uint8_t *>(src),
+                                  count);
+#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
   return inline_memcpy_aligned_access_64bit(dst, src, count);
 #elif defined(LIBC_TARGET_ARCH_IS_RISCV32)
   return inline_memcpy_aligned_access_32bit(dst, src, count);
 #else
 #error "Unimplemented"
 #endif
 }
 
 } // namespace __llvm_libc
 
 #endif // LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMCPY_H

libc/src/string/memory_utils/riscv/inline_memset.h

 //===-- Memset implementation for riscv -------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #ifndef LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMSET_H
 #define LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMSET_H
 
-#include "src/__support/macros/attributes.h"               // LIBC_INLINE
-#include "src/__support/macros/properties/architectures.h" // LIBC_TARGET_ARCH_IS_RISCV64
+#include "src/__support/macros/attributes.h" // LIBC_INLINE
+#include "src/__support/macros/properties/architectures.h"
+#include "src/__support/macros/properties/cpu_features.h"
 #include "src/string/memory_utils/generic/aligned_access.h"
 #include "src/string/memory_utils/utils.h" // Ptr, CPtr
 
 #include <stddef.h> // size_t
 
+#if defined(LIBC_TARGET_CPU_HAS_RISCV_VEXT)
+#include "src/string/memory_utils/riscv/inline_vext.h"
+#endif // LIBC_TARGET_CPU_HAS_RISCV_VEXT
+
 namespace __llvm_libc {
 
 LIBC_INLINE static void inline_memset_riscv(Ptr dst, uint8_t value,
                                             size_t count) {
-#if defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_CPU_HAS_RISCV_VEXT)
+  return inline_memset_riscv_vext(reinterpret_cast<uint8_t *>(p1), value,
+                                  count);
+#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
   return inline_memset_aligned_access_64bit(dst, value, count);
 #elif defined(LIBC_TARGET_ARCH_IS_RISCV32)
   return inline_memset_aligned_access_32bit(dst, value, count);
 #else
 #error "Unimplemented"
 #endif
 }
 
 } // namespace __llvm_libc
 
 #endif // LIBC_SRC_STRING_MEMORY_UTILS_RISCV_INLINE_MEMSET_H

libc/src/string/memory_utils/riscv/inline_vext.h

+//===-- Memory functions vector implementations for riscv -------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+#ifndef LIBC_SRC_STRING_MEMORY_UTILS_RISCV_VECTOR_EXTENSION_H
+#define LIBC_SRC_STRING_MEMORY_UTILS_RISCV_VECTOR_EXTENSION_H
+
+#include "src/__support/macros/properties/cpu_features.h"
+
+#ifndef LIBC_TARGET_CPU_HAS_RISCV_VEXT
+#error "Include this file only if riscv vector extension is available"
+#endif
+
+#include "src/__support/macros/attributes.h" // LIBC_INLINE
+#include "src/string/memory_utils/utils.h"   // Ptr, CPtr
+
+#include <riscv_vector.h>
+#include <stddef.h> // size_t
+
+namespace __llvm_libc {
+
+LIBC_INLINE static void
+inline_memcpy_riscv_vext(uint8_t *dst, const uint8_t *src, size_t count) {
+  while (count > 0) {
+    const size_t vl = __riscv_vsetvl_e8m8(count);
+    __riscv_vse8_v_u8m8(dst, __riscv_vle8_v_u8m8(src, vl), vl);
+    count -= vl;
+    src += vl;
+    dst += vl;
+  }
+}
+
+LIBC_INLINE static void
+inline_memset_riscv_vext(uint8_t *dst, const uint8_t value, size_t count) {
+  const vuint8m8_t splat =
+      __riscv_vmv_v_x_u8m8(value, __riscv_vsetvlmax_e8m8());
+  while (count > 0) {
+    const size_t vl = __riscv_vsetvl_e8m8(count);
+    __riscv_vse8_v_u8m8(dst, splat, vl);
+    count -= vl;
+    dst += vl;
+  }
+}
+
+LIBC_INLINE static int inline_bcmp_riscv_vext(const uint8_t *p1,
+                                              const uint8_t *p2, size_t count) {
+  while (count > 0) {
+    const size_t vl = __riscv_vsetvl_e8m8(count);
+    const vuint8m8_t a = __riscv_vle8_v_u8m8(p1, vl);
+    const vuint8m8_t b = __riscv_vle8_v_u8m8(p2, vl);
+    const vbool1_t neq_mask = __riscv_vmsne_vv_u8m8_b1(a, b, vl);
+    const long first_neq_index = __riscv_vfirst_m_b1(neq_mask, vl);
+    if (first_neq_index >= 0)
+      return 1;
+    count -= vl;
+    p1 += vl;
+    p2 += vl;
+  }
+  return 0;
+}
+
+LIBC_INLINE static int
+inline_memcmp_riscv_vext(const uint8_t *p1, const uint8_t *p2, size_t count) {
+  while (count > 0) {
+    const size_t vl = __riscv_vsetvl_e8m8(count);
+    const vuint8m8_t a = __riscv_vle8_v_u8m8(p1, vl);
+    const vuint8m8_t b = __riscv_vle8_v_u8m8(p2, vl);
+    const vbool1_t neq_mask = __riscv_vmsne_vv_u8m8_b1(a, b, vl);
+    const long first_neq_index = __riscv_vfirst_m_b1(neq_mask, vl);
+    if (first_neq_index >= 0)
+      return static_cast<int>(p1[first_neq_index]) -
+             static_cast<int>(p2[first_neq_index]);
+    count -= vl;
+    p1 += vl;
+    p2 += vl;
+  }
+  return 0;
+}
+
+} // namespace __llvm_libc
+
+#endif // LIBC_SRC_STRING_MEMORY_UTILS_RISCV_VECTOR_EXTENSION_H