[WIP][AMDGPU] Divergence-driven instruction selection for fshr

[foad]

Summary

Make divergent fshr legal since it is selected to v_alignbit, but
expand uniform fshr since there is no s_alignbit instruction.

[foad]

llvm/test/CodeGen/AMDGPU/bf16.ll

631

There are lots of minor regressions like this. I will investigate.

llvm/test/CodeGen/AMDGPU/build_vector.ll

74

This is the intended change. In general we should select SALU instructions for uniform calculations, even if it's more instructions. In this case it's a shame that the result gets copied to a VGPR anyway...

[foad]

llvm/test/CodeGen/AMDGPU/bf16.ll

631

The problem here is that really need to combine shifts and ORs into fshr post-legalization. This no longer happens automatically because we have marked fshr as Custom instead of Legal. I could do it with a target-specific OR combine, but I can't find any way to call back into helper code like MatchRotate in the generic DAGCombiner from a target-specific combine.

[arsenm]

llvm/test/CodeGen/AMDGPU/bf16.ll

631

is there just an isLegal call that needs to be isLegalOrCustom?

[foad]

llvm/test/CodeGen/AMDGPU/bf16.ll

631

is there just an isLegal call that needs to be isLegalOrCustom?

I can make that change in DAGCombiner::MatchRotate but it does not work:

--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8339,10 +8339,10 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
   // The target must have at least one rotate/funnel flavor.
   // We still try to match rotate by constant pre-legalization.
   // TODO: Support pre-legalization funnel-shift by constant.
-  bool HasROTL = hasOperation(ISD::ROTL, VT);
-  bool HasROTR = hasOperation(ISD::ROTR, VT);
-  bool HasFSHL = hasOperation(ISD::FSHL, VT);
-  bool HasFSHR = hasOperation(ISD::FSHR, VT);
+  bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
+  bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
+  bool HasFSHL = TLI.isOperationLegalOrCustom(ISD::FSHL, VT);
+  bool HasFSHR = TLI.isOperationLegalOrCustom(ISD::FSHR, VT);
 
   // If the type is going to be promoted and the target has enabled custom
   // lowering for rotate, allow matching rotate by non-constants. Only allow

The problem is that during legalization a uniform fshr will be legalized by lowering it to shifts and ORs, but this combine will immediately kick in and combine it back into a fshr. That causes an infinite loop.

Maybe the whole premise of this patch is flawed? Is it OK to say that fshr is only legal if it is divergent? Or do I have to say fshr is always legal, and then lower uniform fshr back into shift and ORs at some later stage?

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

protected:
   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
 
+  SDValue LowerFSHR(SDValue Op, SelectionDAG &DAG) const;
+
 protected:
   bool shouldCombineMemoryType(EVT VT) const;
   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 
   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

for (MVT VT : ScalarIntVTs) {
 
     setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand);
 
     // AMDGPU uses ADDC/SUBC/ADDE/SUBE
     setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal);
   }
 
   // The hardware supports 32-bit FSHR, but not FSHL.
-  setOperationAction(ISD::FSHR, MVT::i32, Legal);
+  setOperationAction(ISD::FSHR, MVT::i32, Custom);
 
   // The hardware supports 32-bit ROTR, but not ROTL.
   setOperationAction(ISD::ROTL, {MVT::i32, MVT::i64}, Expand);
   setOperationAction(ISD::ROTR, MVT::i64, Expand);
 
   setOperationAction({ISD::MULHU, ISD::MULHS}, MVT::i16, Expand);
 
   setOperationAction({ISD::MUL, ISD::MULHU, ISD::MULHS}, MVT::i64, Expand);
SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
   case ISD::FP_TO_UINT:
     return LowerFP_TO_INT(Op, DAG);
   case ISD::CTTZ:
   case ISD::CTTZ_ZERO_UNDEF:
   case ISD::CTLZ:
   case ISD::CTLZ_ZERO_UNDEF:
     return LowerCTLZ_CTTZ(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
+  case ISD::FSHR:
+    return LowerFSHR(Op, DAG);
   }
   return Op;
 }
 
 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
                                               SmallVectorImpl<SDValue> &Results,
                                               SelectionDAG &DAG) const {
   switch (N->getOpcode()) {
SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
 
   SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
   for (unsigned I = 0; I < NElts; ++I)
     Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
 
   return DAG.getBuildVector(VT, DL, Args);
 }
 
+SDValue AMDGPUTargetLowering::LowerFSHR(SDValue Op, SelectionDAG &DAG) const {
+  // There is no SALU instruction corresponding to fshr. We don't want to use
+  // the VALU instruction for a uniform operation so expand it.
+  return Op->isDivergent() ? Op : SDValue();
+}
+
 //===----------------------------------------------------------------------===//
 // Custom DAG optimizations
 //===----------------------------------------------------------------------===//
 
 static bool isU24(SDValue Op, SelectionDAG &DAG) {
   return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
 }
 

llvm/test/CodeGen/AMDGPU/bf16.ll

; GFX10-NEXT:    s_setpc_b64 s[30:31]
   store bfloat %in, ptr addrspace(1) %out
   ret void
 }
 
 define void @test_arg_store_v2bf16(<2 x bfloat> %in, ptr addrspace(1) %out) {
 ; GCN-LABEL: test_arg_store_v2bf16:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GCN-NEXT:    s_mov_b32 s6, 0
-; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s4, s6
 ; GCN-NEXT:    s_mov_b32 s5, s6
 ; GCN-NEXT:    buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7-LABEL: test_arg_store_v2bf16:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX7-NEXT:    s_mov_b32 s6, 0
-; GFX7-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX7-NEXT:    s_mov_b32 s4, s6
 ; GFX7-NEXT:    s_mov_b32 s5, s6
 ; GFX7-NEXT:    buffer_store_dword v0, v[2:3], s[4:7], 0 addr64
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: test_arg_store_v2bf16:
; GFX10-NEXT:    s_setpc_b64 s[30:31]
   store <2 x bfloat> %in, ptr addrspace(1) %out
   ret void
 }
 
 define void @test_arg_store_v3bf16(<3 x bfloat> %in, <3 x bfloat> addrspace(1)* %out) {
 ; GCN-LABEL: test_arg_store_v3bf16:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GCN-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s6, 0
-; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GCN-NEXT:    s_mov_b32 s4, s6
 ; GCN-NEXT:    s_mov_b32 s5, s6
 ; GCN-NEXT:    buffer_store_short v2, v[3:4], s[4:7], 0 addr64 offset:4
 ; GCN-NEXT:    buffer_store_dword v0, v[3:4], s[4:7], 0 addr64
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7-LABEL: test_arg_store_v3bf16:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX7-NEXT:    s_mov_b32 s6, 0
-; GFX7-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
 ; GFX7-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX7-NEXT:    s_mov_b32 s4, s6
 ; GFX7-NEXT:    s_mov_b32 s5, s6
 ; GFX7-NEXT:    buffer_store_short v1, v[3:4], s[4:7], 0 addr64 offset:4
 ; GFX7-NEXT:    buffer_store_dword v0, v[3:4], s[4:7], 0 addr64
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]
   store <3 x bfloat> %in, <3 x bfloat> addrspace(1) * %out
   ret void
 }
 
 define void @test_arg_store_v4bf16(<4 x bfloat> %in, ptr addrspace(1) %out) {
 ; GCN-LABEL: test_arg_store_v4bf16:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GCN-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GCN-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GCN-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GCN-NEXT:    s_mov_b32 s6, 0
-; GCN-NEXT:    v_alignbit_b32 v1, v3, v2, 16
-; GCN-NEXT:    v_alignbit_b32 v0, v6, v0, 16
+; GCN-NEXT:    v_or_b32_e32 v1, v2, v3
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v6
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s4, s6
 ; GCN-NEXT:    s_mov_b32 s5, s6
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], v[4:5], s[4:7], 0 addr64
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7-LABEL: test_arg_store_v4bf16:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX7-NEXT:    s_mov_b32 s6, 0
-; GFX7-NEXT:    v_alignbit_b32 v2, v3, v2, 16
-; GFX7-NEXT:    v_alignbit_b32 v1, v1, v0, 16
+; GFX7-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT:    v_or_b32_e32 v1, v0, v1
 ; GFX7-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX7-NEXT:    s_mov_b32 s4, s6
 ; GFX7-NEXT:    s_mov_b32 s5, s6
 ; GFX7-NEXT:    buffer_store_dwordx2 v[1:2], v[4:5], s[4:7], 0 addr64
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: test_arg_store_v4bf16:
; GFX10-NEXT:    s_setpc_b64 s[30:31]
   store <4 x bfloat> %in, ptr addrspace(1)  %out
   ret void
 }
 
 define void @test_arg_store_v8bf16(<8 x bfloat> %in, ptr addrspace(1) %out) {
 ; GCN-LABEL: test_arg_store_v8bf16:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GCN-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GCN-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GCN-NEXT:    v_and_b32_e32 v10, 0xffff0000, v3
+; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v2
+; GCN-NEXT:    v_and_b32_e32 v12, 0xffff0000, v1
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GCN-NEXT:    s_mov_b32 s6, 0
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GCN-NEXT:    v_lshrrev_b32_e32 v10, 16, v5
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT:    v_or_b32_e32 v3, v6, v7
+; GCN-NEXT:    v_or_b32_e32 v2, v4, v5
+; GCN-NEXT:    v_or_b32_e32 v1, v11, v10
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v12
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s4, s6
 ; GCN-NEXT:    s_mov_b32 s5, s6
-; GCN-NEXT:    v_alignbit_b32 v5, v7, v6, 16
-; GCN-NEXT:    v_alignbit_b32 v4, v10, v4, 16
-; GCN-NEXT:    v_alignbit_b32 v3, v3, v2, 16
-; GCN-NEXT:    v_alignbit_b32 v2, v1, v0, 16
-; GCN-NEXT:    buffer_store_dwordx4 v[2:5], v[8:9], s[4:7], 0 addr64
+; GCN-NEXT:    buffer_store_dwordx4 v[0:3], v[8:9], s[4:7], 0 addr64
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7-LABEL: test_arg_store_v8bf16:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX7-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX7-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GFX7-NEXT:    s_mov_b32 s6, 0
-; GFX7-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
-; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX7-NEXT:    v_or_b32_e32 v5, v4, v5
+; GFX7-NEXT:    v_or_b32_e32 v4, v2, v3
+; GFX7-NEXT:    v_or_b32_e32 v3, v0, v1
 ; GFX7-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX7-NEXT:    s_mov_b32 s4, s6
 ; GFX7-NEXT:    s_mov_b32 s5, s6
-; GFX7-NEXT:    v_alignbit_b32 v6, v7, v6, 16
-; GFX7-NEXT:    v_alignbit_b32 v5, v5, v4, 16
-; GFX7-NEXT:    v_alignbit_b32 v4, v3, v2, 16
-; GFX7-NEXT:    v_alignbit_b32 v3, v1, v0, 16
 ; GFX7-NEXT:    buffer_store_dwordx4 v[3:6], v[8:9], s[4:7], 0 addr64
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: test_arg_store_v8bf16:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
; GFX10-NEXT:    s_setpc_b64 s[30:31]
   store <8 x bfloat> %in, ptr addrspace(1) %out
   ret void
 }
 
 define void @test_arg_store_v16bf16(<16 x bfloat> %in, ptr addrspace(1) %out) {
 ; GCN-LABEL: test_arg_store_v16bf16:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GCN-NEXT:    v_lshrrev_b32_e32 v18, 16, v5
-; GCN-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GCN-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GCN-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GCN-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GCN-NEXT:    v_and_b32_e32 v18, 0xffff0000, v3
+; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v2
+; GCN-NEXT:    v_and_b32_e32 v20, 0xffff0000, v1
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GCN-NEXT:    v_and_b32_e32 v15, 0xffff0000, v15
+; GCN-NEXT:    v_lshrrev_b32_e32 v14, 16, v14
+; GCN-NEXT:    v_and_b32_e32 v13, 0xffff0000, v13
+; GCN-NEXT:    v_lshrrev_b32_e32 v12, 16, v12
+; GCN-NEXT:    v_and_b32_e32 v11, 0xffff0000, v11
+; GCN-NEXT:    v_lshrrev_b32_e32 v10, 16, v10
+; GCN-NEXT:    v_and_b32_e32 v9, 0xffff0000, v9
+; GCN-NEXT:    v_lshrrev_b32_e32 v8, 16, v8
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s6, 0
-; GCN-NEXT:    v_lshrrev_b32_e32 v15, 16, v15
-; GCN-NEXT:    v_lshrrev_b32_e32 v19, 16, v13
-; GCN-NEXT:    v_lshrrev_b32_e32 v11, 16, v11
-; GCN-NEXT:    v_lshrrev_b32_e32 v9, 16, v9
-; GCN-NEXT:    v_alignbit_b32 v5, v7, v6, 16
-; GCN-NEXT:    v_alignbit_b32 v4, v18, v4, 16
-; GCN-NEXT:    v_alignbit_b32 v3, v3, v2, 16
-; GCN-NEXT:    v_alignbit_b32 v2, v1, v0, 16
+; GCN-NEXT:    v_or_b32_e32 v3, v6, v7
+; GCN-NEXT:    v_or_b32_e32 v2, v4, v5
+; GCN-NEXT:    v_or_b32_e32 v1, v19, v18
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v20
+; GCN-NEXT:    v_or_b32_e32 v7, v14, v15
+; GCN-NEXT:    v_or_b32_e32 v6, v12, v13
+; GCN-NEXT:    v_or_b32_e32 v5, v10, v11
+; GCN-NEXT:    v_or_b32_e32 v4, v8, v9
 ; GCN-NEXT:    s_mov_b32 s4, s6
 ; GCN-NEXT:    s_mov_b32 s5, s6
-; GCN-NEXT:    v_alignbit_b32 v13, v15, v14, 16
-; GCN-NEXT:    v_alignbit_b32 v12, v19, v12, 16
-; GCN-NEXT:    v_alignbit_b32 v11, v11, v10, 16
-; GCN-NEXT:    v_alignbit_b32 v10, v9, v8, 16
-; GCN-NEXT:    buffer_store_dwordx4 v[10:13], v[16:17], s[4:7], 0 addr64 offset:16
-; GCN-NEXT:    buffer_store_dwordx4 v[2:5], v[16:17], s[4:7], 0 addr64
+; GCN-NEXT:    buffer_store_dwordx4 v[4:7], v[16:17], s[4:7], 0 addr64 offset:16
+; GCN-NEXT:    buffer_store_dwordx4 v[0:3], v[16:17], s[4:7], 0 addr64
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7-LABEL: test_arg_store_v16bf16:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
-; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX7-NEXT:    v_alignbit_b32 v5, v5, v4, 16
-; GFX7-NEXT:    v_alignbit_b32 v4, v3, v2, 16
-; GFX7-NEXT:    v_alignbit_b32 v3, v1, v0, 16
-; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v15
-; GFX7-NEXT:    v_alignbit_b32 v14, v0, v14, 16
-; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v13
-; GFX7-NEXT:    v_alignbit_b32 v13, v0, v12, 16
-; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v11
+; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v5
+; GFX7-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
+; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT:    v_or_b32_e32 v5, v4, v5
+; GFX7-NEXT:    v_or_b32_e32 v4, v2, v3
+; GFX7-NEXT:    v_or_b32_e32 v3, v0, v1
+; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v15
+; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v14
+; GFX7-NEXT:    v_or_b32_e32 v14, v1, v0
+; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v13
+; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v12
+; GFX7-NEXT:    v_or_b32_e32 v13, v1, v0
+; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v11
+; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v10
+; GFX7-NEXT:    v_or_b32_e32 v12, v1, v0
+; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v9
+; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
 ; GFX7-NEXT:    s_mov_b32 s6, 0
-; GFX7-NEXT:    v_alignbit_b32 v12, v0, v10, 16
-; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v9
-; GFX7-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
+; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v7
+; GFX7-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
+; GFX7-NEXT:    v_or_b32_e32 v11, v1, v0
 ; GFX7-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX7-NEXT:    s_mov_b32 s4, s6
 ; GFX7-NEXT:    s_mov_b32 s5, s6
-; GFX7-NEXT:    v_alignbit_b32 v11, v0, v8, 16
-; GFX7-NEXT:    v_alignbit_b32 v6, v7, v6, 16
+; GFX7-NEXT:    v_or_b32_e32 v6, v6, v7
 ; GFX7-NEXT:    buffer_store_dwordx4 v[11:14], v[16:17], s[4:7], 0 addr64 offset:16
 ; GFX7-NEXT:    buffer_store_dwordx4 v[3:6], v[16:17], s[4:7], 0 addr64
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: test_arg_store_v16bf16:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GCN-NEXT:    v_writelane_b32 v4, s30, 0
 ; GCN-NEXT:    v_writelane_b32 v4, s31, 1
 ; GCN-NEXT:    s_getpc_b64 s[4:5]
 ; GCN-NEXT:    s_add_u32 s4, s4, test_arg_store_v2bf16@gotpcrel32@lo+4
 ; GCN-NEXT:    s_addc_u32 s5, s5, test_arg_store_v2bf16@gotpcrel32@hi+12
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GCN-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
 ; GCN-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, 4, v3
-; GCN-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GCN-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GCN-NEXT:    buffer_store_short v2, v5, s[0:3], 0 offen
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v0, v3, s[0:3], 0 offen
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    v_readlane_b32 s31, v4, 1
 ; GCN-NEXT:    v_readlane_b32 s30, v4, 0
 ; GCN-NEXT:    s_xor_saveexec_b64 s[4:5], -1
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 ; 4-byte Folded Reload

 ; GFX7-NEXT:    s_getpc_b64 s[4:5]
 ; GFX7-NEXT:    s_add_u32 s4, s4, test_arg_store_v2bf16@gotpcrel32@lo+4
 ; GFX7-NEXT:    s_addc_u32 s5, s5, test_arg_store_v2bf16@gotpcrel32@hi+12
 ; GFX7-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x0
 ; GFX7-NEXT:    v_writelane_b32 v4, s30, 0
 ; GFX7-NEXT:    v_writelane_b32 v4, s31, 1
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7-NEXT:    s_swappc_b64 s[30:31], s[4:5]
-; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX7-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
 ; GFX7-NEXT:    v_add_i32_e32 v2, vcc, 4, v3
 ; GFX7-NEXT:    buffer_store_short v1, v2, s[0:3], 0 offen
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    buffer_store_dword v0, v3, s[0:3], 0 offen
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    v_readlane_b32 s31, v4, 1
 ; GFX7-NEXT:    v_readlane_b32 s30, v4, 0

llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll

 ; GFX9-NEXT:    ;;#ASMSTART
 ; GFX9-NEXT:    ; use v[0:1]
 ; GFX9-NEXT:    ;;#ASMEND
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: undef_lo2_v4i16:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX8-NEXT:    v_and_b32_e32 v1, 0xffff0000, v0
+; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX8-NEXT:    ;;#ASMSTART
 ; GFX8-NEXT:    ; use v[0:1]
 ; GFX8-NEXT:    ;;#ASMEND
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
   %undef.lo = shufflevector <2 x i16> %arg0, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 3>
   call void asm sideeffect "; use $0", "v"(<4 x i16> %undef.lo);
   ret void
 }
 
 define void @undef_lo2_v4f16(<2 x half> %arg0) {
 ; GFX9-LABEL: undef_lo2_v4f16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_mov_b32 s4, 0x7060302
 ; GFX9-NEXT:    v_perm_b32 v0, v0, v0, s4
 ; GFX9-NEXT:    ;;#ASMSTART
 ; GFX9-NEXT:    ; use v[0:1]
 ; GFX9-NEXT:    ;;#ASMEND
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: undef_lo2_v4f16:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX8-NEXT:    v_and_b32_e32 v1, 0xffff0000, v0
+; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX8-NEXT:    ;;#ASMSTART
 ; GFX8-NEXT:    ; use v[0:1]
 ; GFX8-NEXT:    ;;#ASMEND
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
   %undef.lo = shufflevector <2 x half> %arg0, <2 x half> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 3>
   call void asm sideeffect "; use $0", "v"(<4 x half> %undef.lo);
   ret void
 }

llvm/test/CodeGen/AMDGPU/build_vector.ll

 
 ; ALL-LABEL: {{^}}build_vector_v2i16_trunc:
 ; R600: LSHR
 ; R600: OR_INT
 ; R600: LSHR
 ; R600-NOT: MOV
 ; GFX6: s_mov_b32 s3, 0xf000
 ; GFX6: s_waitcnt lgkmcnt(0)
-; GFX6: v_alignbit_b32 v0, 5, s4, 16
+; GFX6: s_lshr_b32 s2, s2, 16
+; GFX6: s_or_b32 s4, s2, 0x50000
+; GFX6: s_mov_b32 s2, -1
+; GFX6: v_mov_b32_e32 v0, s4
 ; GFX6: buffer_store_dword v0, off, s[0:3], 0
 ; GFX8: s_mov_b32 s3, 0xf000
 ; GFX8: s_mov_b32 s2, -1
 ; GFX8: s_waitcnt lgkmcnt(0)
 ; GFX8: s_lshr_b32 s4, s4, 16
 ; GFX8: s_or_b32 s4, s4, 0x50000
 ; GFX8: v_mov_b32_e32 v0, s4
 ; GFX8: buffer_store_dword v0, off, s[0:3], 0

llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll

; GFX11-NEXT:    s_setpc_b64 s[30:31]
   ret i32 %val
 }
 
 define amdgpu_kernel void @uniform_vec_i16_HH(ptr addrspace(1) %out, i32 %a, i32 %b) {
 ; GCN-LABEL: uniform_vec_i16_HH:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_lshr_b32 s2, s2, 16
+; GCN-NEXT:    s_and_b32 s3, s3, 0xffff0000
+; GCN-NEXT:    s_or_b32 s2, s3, s2
+; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_mov_b32 s4, s0
 ; GCN-NEXT:    s_mov_b32 s5, s1
-; GCN-NEXT:    s_lshr_b32 s0, s3, 16
 ; GCN-NEXT:    v_mov_b32_e32 v0, s2
-; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 16
 ; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: uniform_vec_i16_HH:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)

llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll

; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %fneg = fneg double %bitcast
   ret double %fneg
 }
 
 define double @fneg_f64_bitcast_build_vector_v4bf16_to_f64(bfloat %elt0, bfloat %elt1, bfloat %elt2, bfloat %elt3) {
 ; GFX7-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX7-NEXT:    v_alignbit_b32 v2, v3, v2, 16
-; GFX7-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; GFX7-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX7-NEXT:    v_xor_b32_e32 v1, 0x80000000, v2
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: fneg_f64_bitcast_build_vector_v4bf16_to_f64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_mov_b32 s4, 0x3020706
 ; GFX9-NEXT:    v_perm_b32 v2, v2, v3, s4

llvm/test/CodeGen/AMDGPU/fp_to_sint.ll

 ; VI-NEXT:    v_xor_b32_e32 v1, v1, v3
 ; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v3
 ; VI-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: fp_to_sint_i64:
 ; EG:       ; %bb.0: ; %entry
-; EG-NEXT:    ALU 40, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 42, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
 ; EG-NEXT:     MOV * T0.W, literal.x,
 ; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; EG-NEXT:     BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,
-; EG-NEXT:     AND_INT * T1.W, KC0[2].Z, literal.y,
-; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
-; EG-NEXT:     OR_INT T1.W, PS, literal.x,
-; EG-NEXT:     ADD_INT * T2.W, PV.W, literal.y,
-; EG-NEXT:    8388608(1.175494e-38), -150(nan)
+; EG-NEXT:     BFE_UINT * T0.W, KC0[2].Z, literal.x, PV.W,
+; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT:     ADD_INT T1.W, PV.W, literal.x,
+; EG-NEXT:     AND_INT * T2.W, KC0[2].Z, literal.y,
+; EG-NEXT:    -150(nan), 8388607(1.175494e-38)
+; EG-NEXT:     OR_INT T0.Z, PS, literal.x,
+; EG-NEXT:     NOT_INT T2.W, PV.W,
+; EG-NEXT:     SUB_INT * T3.W, literal.y, T0.W,
+; EG-NEXT:    8388608(1.175494e-38), 150(2.101948e-43)
 ; EG-NEXT:     ADD_INT T0.X, T0.W, literal.x,
-; EG-NEXT:     SUB_INT T0.Y, literal.y, T0.W,
-; EG-NEXT:     AND_INT T0.Z, PS, literal.z,
-; EG-NEXT:     NOT_INT T0.W, PS,
-; EG-NEXT:     LSHR * T3.W, PV.W, 1,
-; EG-NEXT:    -127(nan), 150(2.101948e-43)
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T1.Y, T1.W, PV.Z,
-; EG-NEXT:     AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
-; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
-; EG-NEXT:     AND_INT * T1.W, PV.Y, literal.x,
+; EG-NEXT:     AND_INT T0.Y, T1.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
+; EG-NEXT:     AND_INT T0.W, PV.W, literal.y,
+; EG-NEXT:     LSHR * T2.W, PV.Z, 1,
+; EG-NEXT:    -127(nan), 31(4.344025e-44)
+; EG-NEXT:     LSHR T1.X, PS, PV.W,
+; EG-NEXT:     LSHR T1.Y, T0.Z, PV.Z,
+; EG-NEXT:     AND_INT T1.Z, T3.W, literal.x,
+; EG-NEXT:     LSHL T0.W, T0.Z, PV.Y,
+; EG-NEXT:     AND_INT * T1.W, T1.W, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
 ; EG-NEXT:     CNDE_INT T0.Y, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
-; EG-NEXT:     CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
+; EG-NEXT:     CNDE_INT T0.Z, PV.Z, PV.Y, 0.0,
+; EG-NEXT:     CNDE_INT T0.W, PS, PV.X, PV.W,
 ; EG-NEXT:     SETGT_INT * T1.W, T0.X, literal.x,
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T0.Z, PS, 0.0, PV.W,
-; EG-NEXT:     CNDE_INT T0.W, PS, PV.Y, PV.Z,
+; EG-NEXT:     CNDE_INT T1.Z, PS, 0.0, PV.W,
+; EG-NEXT:     CNDE_INT T0.W, PS, PV.Z, PV.Y,
 ; EG-NEXT:     ASHR * T1.W, KC0[2].Z, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     XOR_INT T0.W, PV.W, PS,
 ; EG-NEXT:     XOR_INT * T2.W, PV.Z, PS,
 ; EG-NEXT:     SUB_INT T2.W, PS, T1.W,
 ; EG-NEXT:     SUBB_UINT * T3.W, PV.W, T1.W,
 ; EG-NEXT:     SUB_INT T2.W, PV.W, PS,
 ; EG-NEXT:     SETGT_INT * T3.W, 0.0, T0.X,

 ; VI-NEXT:    v_sub_u32_e32 v0, vcc, v0, v1
 ; VI-NEXT:    s_mov_b32 s5, s1
 ; VI-NEXT:    v_subb_u32_e32 v1, vcc, v4, v1, vcc
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: fp_to_sint_v2i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 75, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 80, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
 ; EG-NEXT:     MOV * T0.W, literal.x,
 ; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
 ; EG-NEXT:     BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
 ; EG-NEXT:     AND_INT T0.Z, KC0[2].W, literal.x,
-; EG-NEXT:     BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
-; EG-NEXT:     ADD_INT * T2.W, PV.W, literal.z,
-; EG-NEXT:    8388607(1.175494e-38), 23(3.222986e-44)
+; EG-NEXT:     SUB_INT T2.W, literal.y, PV.W,
+; EG-NEXT:     ADD_INT * T3.W, PV.W, literal.z,
+; EG-NEXT:    8388607(1.175494e-38), 150(2.101948e-43)
 ; EG-NEXT:    -150(nan), 0(0.000000e+00)
-; EG-NEXT:     SUB_INT T0.X, literal.x, PV.W,
-; EG-NEXT:     SUB_INT T0.Y, literal.x, T1.W,
-; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
-; EG-NEXT:     OR_INT T3.W, PV.Z, literal.z,
-; EG-NEXT:     AND_INT * T4.W, KC0[3].X, literal.w,
-; EG-NEXT:    150(2.101948e-43), 31(4.344025e-44)
-; EG-NEXT:    8388608(1.175494e-38), 8388607(1.175494e-38)
-; EG-NEXT:     OR_INT T1.X, PS, literal.x,
-; EG-NEXT:     LSHL T1.Y, PV.W, PV.Z,
+; EG-NEXT:     AND_INT T0.X, KC0[3].X, literal.x,
+; EG-NEXT:     AND_INT T0.Y, PS, literal.y,
+; EG-NEXT:     AND_INT T1.Z, PV.W, literal.y,
+; EG-NEXT:     BFE_UINT T0.W, KC0[3].X, literal.z, T0.W,
+; EG-NEXT:     OR_INT * T4.W, PV.Z, literal.w,
+; EG-NEXT:    8388607(1.175494e-38), 31(4.344025e-44)
+; EG-NEXT:    23(3.222986e-44), 8388608(1.175494e-38)
+; EG-NEXT:     ADD_INT T1.X, PV.W, literal.x,
+; EG-NEXT:     LSHR T1.Y, PS, PV.Z,
 ; EG-NEXT:     AND_INT T0.Z, T2.W, literal.y,
-; EG-NEXT:     BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
-; EG-NEXT:     AND_INT * T5.W, PV.Y, literal.y,
-; EG-NEXT:    8388608(1.175494e-38), 32(4.484155e-44)
-; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
-; EG-NEXT:     ADD_INT T1.Z, T0.W, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
-; EG-NEXT:     AND_INT * T5.W, T0.X, literal.y,
+; EG-NEXT:     LSHL T2.W, PS, PV.Y,
+; EG-NEXT:     AND_INT * T5.W, T3.W, literal.y,
 ; EG-NEXT:    -150(nan), 32(4.484155e-44)
-; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, 0.0,
-; EG-NEXT:     NOT_INT T2.Y, T2.W,
-; EG-NEXT:     AND_INT T2.Z, PV.Z, literal.x,
-; EG-NEXT:     NOT_INT T2.W, PV.Z,
-; EG-NEXT:     LSHR * T4.W, T1.X, 1,
+; EG-NEXT:     CNDE_INT T0.Y, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T0.Z, PV.Z, PV.Y, 0.0,
+; EG-NEXT:     AND_INT T6.W, PV.X, literal.x,
+; EG-NEXT:     OR_INT * T7.W, T0.X, literal.y,
+; EG-NEXT:    31(4.344025e-44), 8388608(1.175494e-38)
+; EG-NEXT:     NOT_INT T0.X, T1.X,
+; EG-NEXT:     SUB_INT T1.Y, literal.x, T0.W,
+; EG-NEXT:     NOT_INT T1.Z, T3.W,
+; EG-NEXT:     LSHL T3.W, PS, PV.W,
+; EG-NEXT:     AND_INT * T6.W, T1.X, literal.y,
+; EG-NEXT:    150(2.101948e-43), 32(4.484155e-44)
+; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
+; EG-NEXT:     AND_INT T2.Y, PV.Z, literal.x,
+; EG-NEXT:     AND_INT T1.Z, PV.Y, literal.x,
+; EG-NEXT:     AND_INT T8.W, PV.X, literal.x,
+; EG-NEXT:     LSHR * T9.W, T7.W, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     LSHR T3.X, T3.W, 1,
+; EG-NEXT:     LSHR T0.X, T4.W, 1,
 ; EG-NEXT:     ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
-; EG-NEXT:     BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T0.W, T1.X, PV.Z,
-; EG-NEXT:     AND_INT * T2.W, T1.Z, literal.y,
+; EG-NEXT:     LSHR T2.Z, PS, PV.W,
+; EG-NEXT:     LSHR T0.W, T7.W, PV.Z, BS:VEC_201
+; EG-NEXT:     AND_INT * T4.W, T1.Y, literal.y,
 ; EG-NEXT:    -127(nan), 32(4.484155e-44)
-; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT T4.Y, PS, PV.Z, PV.W,
+; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T1.Y, T6.W, PV.Z, T3.W,
 ; EG-NEXT:     SETGT_INT T1.Z, PV.Y, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
-; EG-NEXT:     ADD_INT * T1.W, T1.W, literal.y,
+; EG-NEXT:     ADD_INT T0.W, T1.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     LSHR * T1.W, PV.X, T2.Y,
 ; EG-NEXT:    23(3.222986e-44), -127(nan)
-; EG-NEXT:     CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
-; EG-NEXT:     SETGT_INT T1.Y, PS, literal.x,
-; EG-NEXT:     CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
-; EG-NEXT:     CNDE_INT T0.W, PV.Z, T0.X, PV.X,
+; EG-NEXT:     CNDE_INT T0.X, T5.W, PS, T2.W,
+; EG-NEXT:     SETGT_INT T2.Y, PV.W, literal.x,
+; EG-NEXT:     CNDE_INT T2.Z, PV.Z, 0.0, PV.Y,
+; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.X, T1.X,
 ; EG-NEXT:     ASHR * T2.W, KC0[3].X, literal.y,
 ; EG-NEXT:    23(3.222986e-44), 31(4.344025e-44)
-; EG-NEXT:     XOR_INT T0.X, PV.W, PS,
-; EG-NEXT:     XOR_INT T2.Y, PV.Z, PS,
-; EG-NEXT:     CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
-; EG-NEXT:     CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
+; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
+; EG-NEXT:     XOR_INT T1.Y, PV.Z, PS,
+; EG-NEXT:     CNDE_INT T1.Z, PV.Y, 0.0, PV.X,
+; EG-NEXT:     CNDE_INT T1.W, PV.Y, T0.Z, T0.Y,
 ; EG-NEXT:     ASHR * T3.W, KC0[2].W, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     XOR_INT T0.Y, PV.W, PS,
 ; EG-NEXT:     XOR_INT T0.Z, PV.Z, PS,
-; EG-NEXT:     SUB_INT T0.W, PV.Y, T2.W,
+; EG-NEXT:     SUB_INT T1.W, PV.Y, T2.W,
 ; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T2.W,
 ; EG-NEXT:     SUB_INT T1.Y, PV.W, PS,
 ; EG-NEXT:     SETGT_INT T1.Z, 0.0, T3.Y,
-; EG-NEXT:     SUB_INT T0.W, PV.Z, T3.W,
+; EG-NEXT:     SUB_INT T1.W, PV.Z, T3.W,
 ; EG-NEXT:     SUBB_UINT * T4.W, PV.Y, T3.W,
 ; EG-NEXT:     SUB_INT T0.Z, PV.W, PS,
-; EG-NEXT:     SETGT_INT T0.W, 0.0, T1.W,
+; EG-NEXT:     SETGT_INT T0.W, 0.0, T0.W,
 ; EG-NEXT:     CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
 ; EG-NEXT:     CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
-; EG-NEXT:     SUB_INT * T2.W, T0.X, T2.W,
+; EG-NEXT:     SUB_INT * T2.W, T1.X, T2.W,
 ; EG-NEXT:     CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
 ; EG-NEXT:     SUB_INT * T2.W, T0.Y, T3.W,
 ; EG-NEXT:     CNDE_INT T1.X, T0.W, PV.W, 0.0,
 ; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %conv = fptosi <2 x float> %x to <2 x i64>
   store <2 x i64> %conv, ptr addrspace(1) %out
   ret void

 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    v_subb_u32_e32 v5, vcc, v8, v5, vcc
 ; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: fp_to_sint_v4i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 101, @6, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    ALU 54, @108, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
+; EG-NEXT:    ALU 100, @6, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 66, @107, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T1.X, 0
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T0.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 6:
 ; EG-NEXT:     MOV * T0.W, literal.x,
 ; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; EG-NEXT:     BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
-; EG-NEXT:     AND_INT * T2.W, KC0[4].X, literal.y,
-; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
-; EG-NEXT:     OR_INT T0.Z, PS, literal.x,
-; EG-NEXT:     BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
-; EG-NEXT:     ADD_INT * T3.W, PV.W, literal.z,
-; EG-NEXT:    8388608(1.175494e-38), 23(3.222986e-44)
-; EG-NEXT:    -150(nan), 0(0.000000e+00)
-; EG-NEXT:     ADD_INT T0.Y, PV.W, literal.x,
-; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
-; EG-NEXT:     NOT_INT T4.W, PS,
-; EG-NEXT:     LSHR * T5.W, PV.Z, 1,
-; EG-NEXT:    -127(nan), 31(4.344025e-44)
+; EG-NEXT:     BFE_UINT * T1.W, KC0[3].Z, literal.x, PV.W,
+; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT:     ADD_INT T2.W, PV.W, literal.x,
+; EG-NEXT:     AND_INT * T3.W, KC0[3].Z, literal.y,
+; EG-NEXT:    -150(nan), 8388607(1.175494e-38)
+; EG-NEXT:     OR_INT T3.W, PS, literal.x,
+; EG-NEXT:     NOT_INT * T4.W, PV.W,
+; EG-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T0.Z, T2.W, literal.x,
+; EG-NEXT:     AND_INT T4.W, PS, literal.x,
+; EG-NEXT:     LSHR * T5.W, PV.W, 1,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     ADD_INT T0.X, T1.W, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
-; EG-NEXT:     AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
-; EG-NEXT:     LSHL T3.W, T0.Z, PV.Z,
-; EG-NEXT:     SUB_INT * T1.W, literal.z, T1.W,
+; EG-NEXT:     LSHR T0.Y, PS, PV.W,
+; EG-NEXT:     AND_INT T1.Z, T2.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     BFE_UINT * T2.W, KC0[4].X, literal.z, T0.W,
 ; EG-NEXT:    -127(nan), 32(4.484155e-44)
-; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T1.X, PS, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
-; EG-NEXT:     AND_INT T0.Z, KC0[3].Z, literal.y,
-; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
-; EG-NEXT:     SETGT_INT * T4.W, PV.X, literal.z,
-; EG-NEXT:    32(4.484155e-44), 8388607(1.175494e-38)
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T2.X, PS, 0.0, PV.W,
-; EG-NEXT:     OR_INT T1.Y, PV.Z, literal.x,
+; EG-NEXT:     LSHL * T4.W, T3.W, T0.Z,
+; EG-NEXT:     AND_INT T1.Y, KC0[4].X, literal.x,
 ; EG-NEXT:     ADD_INT T0.Z, T2.W, literal.y,
-; EG-NEXT:     CNDE_INT T1.W, PV.X, PV.Y, 0.0,
-; EG-NEXT:     CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
-; EG-NEXT:    8388608(1.175494e-38), -150(nan)
-; EG-NEXT:     CNDE_INT T1.X, T4.W, PV.W, PS,
-; EG-NEXT:     ASHR T2.Y, KC0[4].X, literal.x,
-; EG-NEXT:     AND_INT T1.Z, PV.Z, literal.x,
-; EG-NEXT:     NOT_INT T1.W, PV.Z,
-; EG-NEXT:     LSHR * T3.W, PV.Y, 1,
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T3.Y, T1.Y, PV.Z,
-; EG-NEXT:     XOR_INT T1.Z, PV.X, PV.Y,
-; EG-NEXT:     XOR_INT T1.W, T2.X, PV.Y,
-; EG-NEXT:     SUB_INT * T2.W, literal.x, T2.W,
-; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T1.X, T0.Z, literal.x,
-; EG-NEXT:     AND_INT T4.Y, PS, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
-; EG-NEXT:     SUB_INT T1.W, PV.W, T2.Y,
-; EG-NEXT:     SUBB_UINT * T2.W, PV.Z, T2.Y,
+; EG-NEXT:     CNDE_INT T5.W, T1.Z, T0.Y, PV.W,
+; EG-NEXT:     SETGT_INT * T6.W, T0.X, literal.z,
+; EG-NEXT:    8388607(1.175494e-38), -150(nan)
+; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T1.X, KC0[3].W, literal.x,
+; EG-NEXT:     CNDE_INT T0.Y, PS, 0.0, PV.W,
+; EG-NEXT:     AND_INT T2.Z, PV.Z, literal.y,
+; EG-NEXT:     OR_INT T5.W, PV.Y, literal.z,
+; EG-NEXT:     SUB_INT * T1.W, literal.w, T1.W,
+; EG-NEXT:    8388607(1.175494e-38), 31(4.344025e-44)
+; EG-NEXT:    8388608(1.175494e-38), 150(2.101948e-43)
+; EG-NEXT:     NOT_INT T2.X, T0.Z,
+; EG-NEXT:     SUB_INT T1.Y, literal.x, T2.W,
+; EG-NEXT:     AND_INT T3.Z, PS, literal.y,
+; EG-NEXT:     LSHL T7.W, PV.W, PV.Z,
+; EG-NEXT:     AND_INT * T8.W, T0.Z, literal.z,
+; EG-NEXT:    150(2.101948e-43), 31(4.344025e-44)
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     SUB_INT T2.X, PV.W, PS,
-; EG-NEXT:     CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
-; EG-NEXT:     CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
-; EG-NEXT:     CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
-; EG-NEXT:     SETGT_INT * T2.W, T0.Y, literal.x,
+; EG-NEXT:     CNDE_INT T3.X, PS, PV.W, 0.0,
+; EG-NEXT:     LSHR T2.Y, T3.W, PV.Z,
+; EG-NEXT:     AND_INT T0.Z, PV.Y, literal.x,
+; EG-NEXT:     AND_INT T3.W, PV.X, literal.x,
+; EG-NEXT:     LSHR * T9.W, T5.W, 1,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T2.X, T1.W, literal.x,
+; EG-NEXT:     ADD_INT T3.Y, T2.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     LSHR T2.Z, PS, PV.W,
+; EG-NEXT:     LSHR T1.W, T5.W, PV.Z, BS:VEC_201
+; EG-NEXT:     AND_INT * T2.W, T1.Y, literal.x,
+; EG-NEXT:    32(4.484155e-44), -127(nan)
+; EG-NEXT:     CNDE_INT T4.X, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T1.Y, T8.W, PV.Z, T7.W,
+; EG-NEXT:     SETGT_INT T0.Z, PV.Y, literal.x,
+; EG-NEXT:     CNDE_INT T1.W, T1.Z, T4.W, 0.0,
+; EG-NEXT:     CNDE_INT * T2.W, PV.X, T2.Y, 0.0,
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
-; EG-NEXT:     AND_INT T3.Y, KC0[3].W, literal.y,
-; EG-NEXT:     CNDE_INT T2.Z, PS, 0.0, PV.W,
-; EG-NEXT:     CNDE_INT T1.W, PS, PV.Y, PV.Z,
-; EG-NEXT:     ASHR * T2.W, KC0[3].Z, literal.z,
-; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
+; EG-NEXT:     CNDE_INT T2.X, T6.W, PS, PV.W,
+; EG-NEXT:     ASHR T2.Y, KC0[3].Z, literal.x,
+; EG-NEXT:     CNDE_INT T1.Z, PV.Z, 0.0, PV.Y,
+; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.X, T3.X,
+; EG-NEXT:     ASHR * T2.W, KC0[4].X, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
-; EG-NEXT:     XOR_INT T1.Y, PV.W, PS,
-; EG-NEXT:     XOR_INT T0.Z, PV.Z, PS,
-; EG-NEXT:     OR_INT T0.W, PV.Y, literal.y,
-; EG-NEXT:     SUB_INT * T1.W, literal.z, PV.X,
-; EG-NEXT:    23(3.222986e-44), 8388608(1.175494e-38)
-; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T4.X, KC0[3].Y, literal.x,
-; EG-NEXT:     AND_INT T3.Y, PS, literal.y,
-; EG-NEXT:     BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
-; EG-NEXT:     SUB_INT T1.W, PV.Z, T2.W,
-; EG-NEXT:     SUBB_UINT * T3.W, PV.Y, T2.W,
-; EG-NEXT:    8388607(1.175494e-38), 32(4.484155e-44)
-; EG-NEXT:     SUB_INT T5.X, PV.W, PS,
-; EG-NEXT:     SETGT_INT T0.Y, 0.0, T0.Y,
-; EG-NEXT:     CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
-; EG-NEXT:     OR_INT T1.W, PV.X, literal.x,
-; EG-NEXT:     ADD_INT * T3.W, T3.X, literal.y,
-; EG-NEXT:    8388608(1.175494e-38), -150(nan)
-; EG-NEXT:     ADD_INT T4.X, T3.X, literal.x,
-; EG-NEXT:     SUB_INT T3.Y, literal.y, T3.X,
-; EG-NEXT:     AND_INT T2.Z, PS, literal.z,
-; EG-NEXT:     NOT_INT T4.W, PS,
-; EG-NEXT:     LSHR * T5.W, PV.W, 1,
-; EG-NEXT:    -127(nan), 150(2.101948e-43)
+; EG-NEXT:     XOR_INT T3.X, PV.W, PS,
+; EG-NEXT:     XOR_INT T1.Y, PV.Z, PS,
+; EG-NEXT:     XOR_INT T0.Z, PV.X, PV.Y,
+; EG-NEXT:     BFE_UINT T1.W, KC0[3].W, literal.x, T0.W,
+; EG-NEXT:     XOR_INT * T3.W, T0.Y, PV.Y,
+; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT:     ADD_INT T2.X, PV.W, literal.x,
+; EG-NEXT:     SUB_INT T0.Y, PS, T2.Y,
+; EG-NEXT:     SUBB_UINT T1.Z, PV.Z, T2.Y,
+; EG-NEXT:     SUB_INT T3.W, PV.Y, T2.W,
+; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T2.W,
+; EG-NEXT:    -150(nan), 0(0.000000e+00)
+; EG-NEXT:     SUB_INT T4.X, PV.W, PS,
+; EG-NEXT:     SUB_INT T0.Y, PV.Y, PV.Z,
+; EG-NEXT:     AND_INT T1.Z, PV.X, literal.x,
+; EG-NEXT:     BFE_UINT T0.W, KC0[3].Y, literal.y, T0.W,
+; EG-NEXT:     OR_INT * T3.W, T1.X, literal.z,
+; EG-NEXT:    31(4.344025e-44), 23(3.222986e-44)
+; EG-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; EG-NEXT:     SETGT_INT T0.X, 0.0, T0.X,
+; EG-NEXT:     ADD_INT T1.Y, PV.W, literal.x,
+; EG-NEXT:     AND_INT T2.Z, KC0[3].Y, literal.y,
+; EG-NEXT:     LSHL T4.W, PS, PV.Z,
+; EG-NEXT:     AND_INT * T5.W, T2.X, literal.z,
+; EG-NEXT:    -150(nan), 8388607(1.175494e-38)
+; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
+; EG-NEXT:     NOT_INT T4.Y, T2.X,
+; EG-NEXT:     OR_INT T1.Z, PV.Z, literal.x,
+; EG-NEXT:     NOT_INT T6.W, PV.Y,
+; EG-NEXT:     SUB_INT * T7.W, literal.y, T0.W,
+; EG-NEXT:    8388608(1.175494e-38), 150(2.101948e-43)
+; EG-NEXT:     ADD_INT T2.X, T0.W, literal.x,
+; EG-NEXT:     AND_INT T5.Y, T1.Y, literal.y,
+; EG-NEXT:     AND_INT * T2.Z, PS, literal.y,
+; EG-NEXT:    -127(nan), 31(4.344025e-44)
+; EG-NEXT:    ALU clause starting at 107:
+; EG-NEXT:     AND_INT T0.W, T6.W, literal.x,
+; EG-NEXT:     LSHR * T6.W, T1.Z, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T4.Y, T1.W, PV.Z,
-; EG-NEXT:     AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
-; EG-NEXT:     BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
-; EG-NEXT:     AND_INT * T3.W, PV.Y, literal.x,
+; EG-NEXT:     LSHR T5.X, PS, PV.W,
+; EG-NEXT:     LSHR T6.Y, T1.Z, T2.Z,
+; EG-NEXT:     AND_INT T2.Z, T7.W, literal.x,
+; EG-NEXT:     LSHL T0.W, T1.Z, T5.Y,
+; EG-NEXT:     AND_INT * T6.W, T1.Y, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     ADD_INT T6.X, T1.X, literal.x,
-; EG-NEXT:     CNDE_INT T3.Y, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
-; EG-NEXT:    -150(nan), 0(0.000000e+00)
-; EG-NEXT:    ALU clause starting at 108:
-; EG-NEXT:     CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
-; EG-NEXT:     SETGT_INT * T3.W, T4.X, literal.x,
-; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T3.X, PS, 0.0, PV.W,
-; EG-NEXT:     CNDE_INT T3.Y, PS, T3.Y, T3.Z,
-; EG-NEXT:     AND_INT T2.Z, T6.X, literal.x,
-; EG-NEXT:     NOT_INT T1.W, T6.X,
-; EG-NEXT:     LSHR * T3.W, T0.W, 1,
+; EG-NEXT:     SUB_INT T6.X, literal.x, T1.W,
+; EG-NEXT:     CNDE_INT T1.Y, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
+; EG-NEXT:     CNDE_INT T0.W, PS, PV.X, PV.W,
+; EG-NEXT:     SETGT_INT * T6.W, T2.X, literal.y,
+; EG-NEXT:    150(2.101948e-43), 23(3.222986e-44)
+; EG-NEXT:     CNDE_INT T5.X, PS, 0.0, PV.W,
+; EG-NEXT:     CNDE_INT T1.Y, PS, PV.Z, PV.Y,
+; EG-NEXT:     AND_INT T1.Z, PV.X, literal.x,
+; EG-NEXT:     AND_INT T0.W, T4.Y, literal.x,
+; EG-NEXT:     LSHR * T6.W, T3.W, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     ASHR T7.X, KC0[3].Y, literal.x,
-; EG-NEXT:     ADD_INT T4.Y, T1.X, literal.y,
-; EG-NEXT:     BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T0.W, T0.W, PV.Z,
+; EG-NEXT:     ADD_INT T4.Y, T1.W, literal.y,
+; EG-NEXT:     LSHR T2.Z, PS, PV.W,
+; EG-NEXT:     LSHR T0.W, T3.W, PV.Z, BS:VEC_120/SCL_212
 ; EG-NEXT:     AND_INT * T1.W, T6.X, literal.z,
 ; EG-NEXT:    31(4.344025e-44), -127(nan)
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT T5.Y, PS, PV.Z, PV.W,
-; EG-NEXT:     SETGT_INT T2.Z, PV.Y, literal.x,
-; EG-NEXT:     XOR_INT T0.W, T3.Y, PV.X,
-; EG-NEXT:     XOR_INT * T1.W, T3.X, PV.X,
+; EG-NEXT:     CNDE_INT T6.X, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T5.Y, T5.W, PV.Z, T4.W,
+; EG-NEXT:     SETGT_INT T1.Z, PV.Y, literal.x,
+; EG-NEXT:     XOR_INT T0.W, T1.Y, PV.X,
+; EG-NEXT:     XOR_INT * T1.W, T5.X, PV.X,
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     SUB_INT T3.X, PS, T7.X,
-; EG-NEXT:     SUBB_UINT T3.Y, PV.W, T7.X,
-; EG-NEXT:     CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
-; EG-NEXT:     CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
+; EG-NEXT:     SUB_INT T5.X, PS, T7.X,
+; EG-NEXT:     SUBB_UINT T1.Y, PV.W, T7.X,
+; EG-NEXT:     CNDE_INT T2.Z, PV.Z, 0.0, PV.Y,
+; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.X, T1.X,
 ; EG-NEXT:     ASHR * T3.W, KC0[3].W, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
 ; EG-NEXT:     XOR_INT T5.Y, PV.Z, PS,
-; EG-NEXT:     SUB_INT T0.Z, PV.X, PV.Y,
-; EG-NEXT:     SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
-; EG-NEXT:     CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
-; EG-NEXT:     SETGT_INT T0.X, 0.0, T0.X,
+; EG-NEXT:     SUB_INT T1.Z, PV.X, PV.Y,
+; EG-NEXT:     SETGT_INT T1.W, 0.0, T2.X,
+; EG-NEXT:     CNDE_INT * T6.W, T0.X, T0.Y, 0.0,
+; EG-NEXT:     SETGT_INT T2.X, 0.0, T3.Y,
 ; EG-NEXT:     CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
-; EG-NEXT:     SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
-; EG-NEXT:     SUB_INT T2.W, PV.Y, T3.W,
-; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T3.W,
-; EG-NEXT:     SUB_INT T3.X, PV.W, PS,
-; EG-NEXT:     SETGT_INT T1.Y, 0.0, T4.Y,
-; EG-NEXT:     CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
+; EG-NEXT:     SUB_INT T0.Z, T0.Z, T2.Y, BS:VEC_021/SCL_122
+; EG-NEXT:     SUB_INT T4.W, PV.Y, T3.W,
+; EG-NEXT:     SUBB_UINT * T5.W, PV.X, T3.W,
+; EG-NEXT:     SUB_INT T5.X, PV.W, PS,
+; EG-NEXT:     SETGT_INT T0.Y, 0.0, T4.Y,
+; EG-NEXT:     CNDE_INT T6.Z, T0.X, PV.Z, 0.0,
 ; EG-NEXT:     SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
-; EG-NEXT:     CNDE_INT * T4.W, PV.X, T2.X, 0.0,
+; EG-NEXT:     CNDE_INT * T4.W, PV.X, T4.X, 0.0,
 ; EG-NEXT:     CNDE_INT T6.X, T1.W, PV.W, 0.0,
 ; EG-NEXT:     CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
-; EG-NEXT:     SUB_INT T0.W, T1.Z, T2.Y,
-; EG-NEXT:     LSHR * T2.X, KC0[2].Y, literal.x,
+; EG-NEXT:     SUB_INT T0.W, T3.X, T2.W,
+; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T4.Z, T0.X, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T4.Z, T2.X, PV.W, 0.0,
 ; EG-NEXT:     SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
-; EG-NEXT:     CNDE_INT T4.X, T1.Y, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T4.X, T0.Y, PV.W, 0.0,
 ; EG-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
 ; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT:     LSHR * T0.X, PV.W, literal.x,
+; EG-NEXT:     LSHR * T1.X, PV.W, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %conv = fptosi <4 x float> %x to <4 x i64>
   store <4 x i64> %conv, ptr addrspace(1) %out
   ret void
 }
 
 define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {
 ; SI-LABEL: fp_to_uint_f32_to_i1:

llvm/test/CodeGen/AMDGPU/fp_to_uint.ll

 ; VI-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; VI-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: fp_to_uint_f32_to_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 40, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 42, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
 ; EG-NEXT:     MOV * T0.W, literal.x,
 ; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; EG-NEXT:     BFE_UINT T0.W, KC0[2].Z, literal.x, PV.W,
-; EG-NEXT:     AND_INT * T1.W, KC0[2].Z, literal.y,
-; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
-; EG-NEXT:     OR_INT T1.W, PS, literal.x,
-; EG-NEXT:     ADD_INT * T2.W, PV.W, literal.y,
-; EG-NEXT:    8388608(1.175494e-38), -150(nan)
+; EG-NEXT:     BFE_UINT * T0.W, KC0[2].Z, literal.x, PV.W,
+; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT:     ADD_INT T1.W, PV.W, literal.x,
+; EG-NEXT:     AND_INT * T2.W, KC0[2].Z, literal.y,
+; EG-NEXT:    -150(nan), 8388607(1.175494e-38)
+; EG-NEXT:     OR_INT T0.Z, PS, literal.x,
+; EG-NEXT:     NOT_INT T2.W, PV.W,
+; EG-NEXT:     SUB_INT * T3.W, literal.y, T0.W,
+; EG-NEXT:    8388608(1.175494e-38), 150(2.101948e-43)
 ; EG-NEXT:     ADD_INT T0.X, T0.W, literal.x,
-; EG-NEXT:     SUB_INT T0.Y, literal.y, T0.W,
-; EG-NEXT:     AND_INT T0.Z, PS, literal.z,
-; EG-NEXT:     NOT_INT T0.W, PS,
-; EG-NEXT:     LSHR * T3.W, PV.W, 1,
-; EG-NEXT:    -127(nan), 150(2.101948e-43)
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T1.Y, T1.W, PV.Z,
-; EG-NEXT:     AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
-; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
-; EG-NEXT:     AND_INT * T1.W, PV.Y, literal.x,
+; EG-NEXT:     AND_INT T0.Y, T1.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
+; EG-NEXT:     AND_INT T0.W, PV.W, literal.y,
+; EG-NEXT:     LSHR * T2.W, PV.Z, 1,
+; EG-NEXT:    -127(nan), 31(4.344025e-44)
+; EG-NEXT:     LSHR T1.X, PS, PV.W,
+; EG-NEXT:     LSHR T1.Y, T0.Z, PV.Z,
+; EG-NEXT:     AND_INT T1.Z, T3.W, literal.x,
+; EG-NEXT:     LSHL T0.W, T0.Z, PV.Y,
+; EG-NEXT:     AND_INT * T1.W, T1.W, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
 ; EG-NEXT:     CNDE_INT T0.Y, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
-; EG-NEXT:     CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
+; EG-NEXT:     CNDE_INT T0.Z, PV.Z, PV.Y, 0.0,
+; EG-NEXT:     CNDE_INT T0.W, PS, PV.X, PV.W,
 ; EG-NEXT:     SETGT_INT * T1.W, T0.X, literal.x,
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T0.Z, PS, 0.0, PV.W,
-; EG-NEXT:     CNDE_INT T0.W, PS, PV.Y, PV.Z,
+; EG-NEXT:     CNDE_INT T1.Z, PS, 0.0, PV.W,
+; EG-NEXT:     CNDE_INT T0.W, PS, PV.Z, PV.Y,
 ; EG-NEXT:     ASHR * T1.W, KC0[2].Z, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     XOR_INT T0.W, PV.W, PS,
 ; EG-NEXT:     XOR_INT * T2.W, PV.Z, PS,
 ; EG-NEXT:     SUB_INT T2.W, PS, T1.W,
 ; EG-NEXT:     SUBB_UINT * T3.W, PV.W, T1.W,
 ; EG-NEXT:     SUB_INT T2.W, PV.W, PS,
 ; EG-NEXT:     SETGT_INT * T3.W, 0.0, T0.X,

 ; VI-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; VI-NEXT:    s_mov_b32 s4, s0
 ; VI-NEXT:    s_mov_b32 s5, s1
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: fp_to_uint_v2f32_to_v2i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 75, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 80, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
 ; EG-NEXT:     MOV * T0.W, literal.x,
 ; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
 ; EG-NEXT:     BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
 ; EG-NEXT:     AND_INT T0.Z, KC0[2].W, literal.x,
-; EG-NEXT:     BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
-; EG-NEXT:     ADD_INT * T2.W, PV.W, literal.z,
-; EG-NEXT:    8388607(1.175494e-38), 23(3.222986e-44)
+; EG-NEXT:     SUB_INT T2.W, literal.y, PV.W,
+; EG-NEXT:     ADD_INT * T3.W, PV.W, literal.z,
+; EG-NEXT:    8388607(1.175494e-38), 150(2.101948e-43)
 ; EG-NEXT:    -150(nan), 0(0.000000e+00)
-; EG-NEXT:     SUB_INT T0.X, literal.x, PV.W,
-; EG-NEXT:     SUB_INT T0.Y, literal.x, T1.W,
-; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
-; EG-NEXT:     OR_INT T3.W, PV.Z, literal.z,
-; EG-NEXT:     AND_INT * T4.W, KC0[3].X, literal.w,
-; EG-NEXT:    150(2.101948e-43), 31(4.344025e-44)
-; EG-NEXT:    8388608(1.175494e-38), 8388607(1.175494e-38)
-; EG-NEXT:     OR_INT T1.X, PS, literal.x,
-; EG-NEXT:     LSHL T1.Y, PV.W, PV.Z,
+; EG-NEXT:     AND_INT T0.X, KC0[3].X, literal.x,
+; EG-NEXT:     AND_INT T0.Y, PS, literal.y,
+; EG-NEXT:     AND_INT T1.Z, PV.W, literal.y,
+; EG-NEXT:     BFE_UINT T0.W, KC0[3].X, literal.z, T0.W,
+; EG-NEXT:     OR_INT * T4.W, PV.Z, literal.w,
+; EG-NEXT:    8388607(1.175494e-38), 31(4.344025e-44)
+; EG-NEXT:    23(3.222986e-44), 8388608(1.175494e-38)
+; EG-NEXT:     ADD_INT T1.X, PV.W, literal.x,
+; EG-NEXT:     LSHR T1.Y, PS, PV.Z,
 ; EG-NEXT:     AND_INT T0.Z, T2.W, literal.y,
-; EG-NEXT:     BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
-; EG-NEXT:     AND_INT * T5.W, PV.Y, literal.y,
-; EG-NEXT:    8388608(1.175494e-38), 32(4.484155e-44)
-; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
-; EG-NEXT:     ADD_INT T1.Z, T0.W, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
-; EG-NEXT:     AND_INT * T5.W, T0.X, literal.y,
+; EG-NEXT:     LSHL T2.W, PS, PV.Y,
+; EG-NEXT:     AND_INT * T5.W, T3.W, literal.y,
 ; EG-NEXT:    -150(nan), 32(4.484155e-44)
-; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, 0.0,
-; EG-NEXT:     NOT_INT T2.Y, T2.W,
-; EG-NEXT:     AND_INT T2.Z, PV.Z, literal.x,
-; EG-NEXT:     NOT_INT T2.W, PV.Z,
-; EG-NEXT:     LSHR * T4.W, T1.X, 1,
+; EG-NEXT:     CNDE_INT T0.Y, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T0.Z, PV.Z, PV.Y, 0.0,
+; EG-NEXT:     AND_INT T6.W, PV.X, literal.x,
+; EG-NEXT:     OR_INT * T7.W, T0.X, literal.y,
+; EG-NEXT:    31(4.344025e-44), 8388608(1.175494e-38)
+; EG-NEXT:     NOT_INT T0.X, T1.X,
+; EG-NEXT:     SUB_INT T1.Y, literal.x, T0.W,
+; EG-NEXT:     NOT_INT T1.Z, T3.W,
+; EG-NEXT:     LSHL T3.W, PS, PV.W,
+; EG-NEXT:     AND_INT * T6.W, T1.X, literal.y,
+; EG-NEXT:    150(2.101948e-43), 32(4.484155e-44)
+; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
+; EG-NEXT:     AND_INT T2.Y, PV.Z, literal.x,
+; EG-NEXT:     AND_INT T1.Z, PV.Y, literal.x,
+; EG-NEXT:     AND_INT T8.W, PV.X, literal.x,
+; EG-NEXT:     LSHR * T9.W, T7.W, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     LSHR T3.X, T3.W, 1,
+; EG-NEXT:     LSHR T0.X, T4.W, 1,
 ; EG-NEXT:     ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
-; EG-NEXT:     BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T0.W, T1.X, PV.Z,
-; EG-NEXT:     AND_INT * T2.W, T1.Z, literal.y,
+; EG-NEXT:     LSHR T2.Z, PS, PV.W,
+; EG-NEXT:     LSHR T0.W, T7.W, PV.Z, BS:VEC_201
+; EG-NEXT:     AND_INT * T4.W, T1.Y, literal.y,
 ; EG-NEXT:    -127(nan), 32(4.484155e-44)
-; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT T4.Y, PS, PV.Z, PV.W,
+; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T1.Y, T6.W, PV.Z, T3.W,
 ; EG-NEXT:     SETGT_INT T1.Z, PV.Y, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
-; EG-NEXT:     ADD_INT * T1.W, T1.W, literal.y,
+; EG-NEXT:     ADD_INT T0.W, T1.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     LSHR * T1.W, PV.X, T2.Y,
 ; EG-NEXT:    23(3.222986e-44), -127(nan)
-; EG-NEXT:     CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
-; EG-NEXT:     SETGT_INT T1.Y, PS, literal.x,
-; EG-NEXT:     CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
-; EG-NEXT:     CNDE_INT T0.W, PV.Z, T0.X, PV.X,
+; EG-NEXT:     CNDE_INT T0.X, T5.W, PS, T2.W,
+; EG-NEXT:     SETGT_INT T2.Y, PV.W, literal.x,
+; EG-NEXT:     CNDE_INT T2.Z, PV.Z, 0.0, PV.Y,
+; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.X, T1.X,
 ; EG-NEXT:     ASHR * T2.W, KC0[3].X, literal.y,
 ; EG-NEXT:    23(3.222986e-44), 31(4.344025e-44)
-; EG-NEXT:     XOR_INT T0.X, PV.W, PS,
-; EG-NEXT:     XOR_INT T2.Y, PV.Z, PS,
-; EG-NEXT:     CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
-; EG-NEXT:     CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
+; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
+; EG-NEXT:     XOR_INT T1.Y, PV.Z, PS,
+; EG-NEXT:     CNDE_INT T1.Z, PV.Y, 0.0, PV.X,
+; EG-NEXT:     CNDE_INT T1.W, PV.Y, T0.Z, T0.Y,
 ; EG-NEXT:     ASHR * T3.W, KC0[2].W, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     XOR_INT T0.Y, PV.W, PS,
 ; EG-NEXT:     XOR_INT T0.Z, PV.Z, PS,
-; EG-NEXT:     SUB_INT T0.W, PV.Y, T2.W,
+; EG-NEXT:     SUB_INT T1.W, PV.Y, T2.W,
 ; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T2.W,
 ; EG-NEXT:     SUB_INT T1.Y, PV.W, PS,
 ; EG-NEXT:     SETGT_INT T1.Z, 0.0, T3.Y,
-; EG-NEXT:     SUB_INT T0.W, PV.Z, T3.W,
+; EG-NEXT:     SUB_INT T1.W, PV.Z, T3.W,
 ; EG-NEXT:     SUBB_UINT * T4.W, PV.Y, T3.W,
 ; EG-NEXT:     SUB_INT T0.Z, PV.W, PS,
-; EG-NEXT:     SETGT_INT T0.W, 0.0, T1.W,
+; EG-NEXT:     SETGT_INT T0.W, 0.0, T0.W,
 ; EG-NEXT:     CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
 ; EG-NEXT:     CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
-; EG-NEXT:     SUB_INT * T2.W, T0.X, T2.W,
+; EG-NEXT:     SUB_INT * T2.W, T1.X, T2.W,
 ; EG-NEXT:     CNDE_INT T1.Z, T1.Z, PV.W, 0.0,
 ; EG-NEXT:     SUB_INT * T2.W, T0.Y, T3.W,
 ; EG-NEXT:     CNDE_INT T1.X, T0.W, PV.W, 0.0,
 ; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %conv = fptoui <2 x float> %x to <2 x i64>
   store <2 x i64> %conv, ptr addrspace(1) %out
   ret void

 ; VI-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; VI-NEXT:    s_mov_b32 s2, -1
 ; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: fp_to_uint_v4f32_to_v4i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 101, @6, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    ALU 54, @108, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
+; EG-NEXT:    ALU 100, @6, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 66, @107, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T1.X, 0
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T0.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 6:
 ; EG-NEXT:     MOV * T0.W, literal.x,
 ; EG-NEXT:    8(1.121039e-44), 0(0.000000e+00)
-; EG-NEXT:     BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
-; EG-NEXT:     AND_INT * T2.W, KC0[4].X, literal.y,
-; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
-; EG-NEXT:     OR_INT T0.Z, PS, literal.x,
-; EG-NEXT:     BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
-; EG-NEXT:     ADD_INT * T3.W, PV.W, literal.z,
-; EG-NEXT:    8388608(1.175494e-38), 23(3.222986e-44)
-; EG-NEXT:    -150(nan), 0(0.000000e+00)
-; EG-NEXT:     ADD_INT T0.Y, PV.W, literal.x,
-; EG-NEXT:     AND_INT T1.Z, PS, literal.y,
-; EG-NEXT:     NOT_INT T4.W, PS,
-; EG-NEXT:     LSHR * T5.W, PV.Z, 1,
-; EG-NEXT:    -127(nan), 31(4.344025e-44)
+; EG-NEXT:     BFE_UINT * T1.W, KC0[3].Z, literal.x, PV.W,
+; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT:     ADD_INT T2.W, PV.W, literal.x,
+; EG-NEXT:     AND_INT * T3.W, KC0[3].Z, literal.y,
+; EG-NEXT:    -150(nan), 8388607(1.175494e-38)
+; EG-NEXT:     OR_INT T3.W, PS, literal.x,
+; EG-NEXT:     NOT_INT * T4.W, PV.W,
+; EG-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T0.Z, T2.W, literal.x,
+; EG-NEXT:     AND_INT T4.W, PS, literal.x,
+; EG-NEXT:     LSHR * T5.W, PV.W, 1,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     ADD_INT T0.X, T1.W, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
-; EG-NEXT:     AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
-; EG-NEXT:     LSHL T3.W, T0.Z, PV.Z,
-; EG-NEXT:     SUB_INT * T1.W, literal.z, T1.W,
+; EG-NEXT:     LSHR T0.Y, PS, PV.W,
+; EG-NEXT:     AND_INT T1.Z, T2.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     BFE_UINT * T2.W, KC0[4].X, literal.z, T0.W,
 ; EG-NEXT:    -127(nan), 32(4.484155e-44)
-; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T1.X, PS, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
-; EG-NEXT:     AND_INT T0.Z, KC0[3].Z, literal.y,
-; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
-; EG-NEXT:     SETGT_INT * T4.W, PV.X, literal.z,
-; EG-NEXT:    32(4.484155e-44), 8388607(1.175494e-38)
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T2.X, PS, 0.0, PV.W,
-; EG-NEXT:     OR_INT T1.Y, PV.Z, literal.x,
+; EG-NEXT:     LSHL * T4.W, T3.W, T0.Z,
+; EG-NEXT:     AND_INT T1.Y, KC0[4].X, literal.x,
 ; EG-NEXT:     ADD_INT T0.Z, T2.W, literal.y,
-; EG-NEXT:     CNDE_INT T1.W, PV.X, PV.Y, 0.0,
-; EG-NEXT:     CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
-; EG-NEXT:    8388608(1.175494e-38), -150(nan)
-; EG-NEXT:     CNDE_INT T1.X, T4.W, PV.W, PS,
-; EG-NEXT:     ASHR T2.Y, KC0[4].X, literal.x,
-; EG-NEXT:     AND_INT T1.Z, PV.Z, literal.x,
-; EG-NEXT:     NOT_INT T1.W, PV.Z,
-; EG-NEXT:     LSHR * T3.W, PV.Y, 1,
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T3.Y, T1.Y, PV.Z,
-; EG-NEXT:     XOR_INT T1.Z, PV.X, PV.Y,
-; EG-NEXT:     XOR_INT T1.W, T2.X, PV.Y,
-; EG-NEXT:     SUB_INT * T2.W, literal.x, T2.W,
-; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T1.X, T0.Z, literal.x,
-; EG-NEXT:     AND_INT T4.Y, PS, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
-; EG-NEXT:     SUB_INT T1.W, PV.W, T2.Y,
-; EG-NEXT:     SUBB_UINT * T2.W, PV.Z, T2.Y,
+; EG-NEXT:     CNDE_INT T5.W, T1.Z, T0.Y, PV.W,
+; EG-NEXT:     SETGT_INT * T6.W, T0.X, literal.z,
+; EG-NEXT:    8388607(1.175494e-38), -150(nan)
+; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T1.X, KC0[3].W, literal.x,
+; EG-NEXT:     CNDE_INT T0.Y, PS, 0.0, PV.W,
+; EG-NEXT:     AND_INT T2.Z, PV.Z, literal.y,
+; EG-NEXT:     OR_INT T5.W, PV.Y, literal.z,
+; EG-NEXT:     SUB_INT * T1.W, literal.w, T1.W,
+; EG-NEXT:    8388607(1.175494e-38), 31(4.344025e-44)
+; EG-NEXT:    8388608(1.175494e-38), 150(2.101948e-43)
+; EG-NEXT:     NOT_INT T2.X, T0.Z,
+; EG-NEXT:     SUB_INT T1.Y, literal.x, T2.W,
+; EG-NEXT:     AND_INT T3.Z, PS, literal.y,
+; EG-NEXT:     LSHL T7.W, PV.W, PV.Z,
+; EG-NEXT:     AND_INT * T8.W, T0.Z, literal.z,
+; EG-NEXT:    150(2.101948e-43), 31(4.344025e-44)
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     SUB_INT T2.X, PV.W, PS,
-; EG-NEXT:     CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
-; EG-NEXT:     CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
-; EG-NEXT:     CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
-; EG-NEXT:     SETGT_INT * T2.W, T0.Y, literal.x,
+; EG-NEXT:     CNDE_INT T3.X, PS, PV.W, 0.0,
+; EG-NEXT:     LSHR T2.Y, T3.W, PV.Z,
+; EG-NEXT:     AND_INT T0.Z, PV.Y, literal.x,
+; EG-NEXT:     AND_INT T3.W, PV.X, literal.x,
+; EG-NEXT:     LSHR * T9.W, T5.W, 1,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T2.X, T1.W, literal.x,
+; EG-NEXT:     ADD_INT T3.Y, T2.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     LSHR T2.Z, PS, PV.W,
+; EG-NEXT:     LSHR T1.W, T5.W, PV.Z, BS:VEC_201
+; EG-NEXT:     AND_INT * T2.W, T1.Y, literal.x,
+; EG-NEXT:    32(4.484155e-44), -127(nan)
+; EG-NEXT:     CNDE_INT T4.X, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T1.Y, T8.W, PV.Z, T7.W,
+; EG-NEXT:     SETGT_INT T0.Z, PV.Y, literal.x,
+; EG-NEXT:     CNDE_INT T1.W, T1.Z, T4.W, 0.0,
+; EG-NEXT:     CNDE_INT * T2.W, PV.X, T2.Y, 0.0,
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
-; EG-NEXT:     AND_INT T3.Y, KC0[3].W, literal.y,
-; EG-NEXT:     CNDE_INT T2.Z, PS, 0.0, PV.W,
-; EG-NEXT:     CNDE_INT T1.W, PS, PV.Y, PV.Z,
-; EG-NEXT:     ASHR * T2.W, KC0[3].Z, literal.z,
-; EG-NEXT:    23(3.222986e-44), 8388607(1.175494e-38)
+; EG-NEXT:     CNDE_INT T2.X, T6.W, PS, PV.W,
+; EG-NEXT:     ASHR T2.Y, KC0[3].Z, literal.x,
+; EG-NEXT:     CNDE_INT T1.Z, PV.Z, 0.0, PV.Y,
+; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.X, T3.X,
+; EG-NEXT:     ASHR * T2.W, KC0[4].X, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
-; EG-NEXT:     XOR_INT T1.Y, PV.W, PS,
-; EG-NEXT:     XOR_INT T0.Z, PV.Z, PS,
-; EG-NEXT:     OR_INT T0.W, PV.Y, literal.y,
-; EG-NEXT:     SUB_INT * T1.W, literal.z, PV.X,
-; EG-NEXT:    23(3.222986e-44), 8388608(1.175494e-38)
-; EG-NEXT:    150(2.101948e-43), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T4.X, KC0[3].Y, literal.x,
-; EG-NEXT:     AND_INT T3.Y, PS, literal.y,
-; EG-NEXT:     BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
-; EG-NEXT:     SUB_INT T1.W, PV.Z, T2.W,
-; EG-NEXT:     SUBB_UINT * T3.W, PV.Y, T2.W,
-; EG-NEXT:    8388607(1.175494e-38), 32(4.484155e-44)
-; EG-NEXT:     SUB_INT T5.X, PV.W, PS,
-; EG-NEXT:     SETGT_INT T0.Y, 0.0, T0.Y,
-; EG-NEXT:     CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
-; EG-NEXT:     OR_INT T1.W, PV.X, literal.x,
-; EG-NEXT:     ADD_INT * T3.W, T3.X, literal.y,
-; EG-NEXT:    8388608(1.175494e-38), -150(nan)
-; EG-NEXT:     ADD_INT T4.X, T3.X, literal.x,
-; EG-NEXT:     SUB_INT T3.Y, literal.y, T3.X,
-; EG-NEXT:     AND_INT T2.Z, PS, literal.z,
-; EG-NEXT:     NOT_INT T4.W, PS,
-; EG-NEXT:     LSHR * T5.W, PV.W, 1,
-; EG-NEXT:    -127(nan), 150(2.101948e-43)
+; EG-NEXT:     XOR_INT T3.X, PV.W, PS,
+; EG-NEXT:     XOR_INT T1.Y, PV.Z, PS,
+; EG-NEXT:     XOR_INT T0.Z, PV.X, PV.Y,
+; EG-NEXT:     BFE_UINT T1.W, KC0[3].W, literal.x, T0.W,
+; EG-NEXT:     XOR_INT * T3.W, T0.Y, PV.Y,
+; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT:     ADD_INT T2.X, PV.W, literal.x,
+; EG-NEXT:     SUB_INT T0.Y, PS, T2.Y,
+; EG-NEXT:     SUBB_UINT T1.Z, PV.Z, T2.Y,
+; EG-NEXT:     SUB_INT T3.W, PV.Y, T2.W,
+; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T2.W,
+; EG-NEXT:    -150(nan), 0(0.000000e+00)
+; EG-NEXT:     SUB_INT T4.X, PV.W, PS,
+; EG-NEXT:     SUB_INT T0.Y, PV.Y, PV.Z,
+; EG-NEXT:     AND_INT T1.Z, PV.X, literal.x,
+; EG-NEXT:     BFE_UINT T0.W, KC0[3].Y, literal.y, T0.W,
+; EG-NEXT:     OR_INT * T3.W, T1.X, literal.z,
+; EG-NEXT:    31(4.344025e-44), 23(3.222986e-44)
+; EG-NEXT:    8388608(1.175494e-38), 0(0.000000e+00)
+; EG-NEXT:     SETGT_INT T0.X, 0.0, T0.X,
+; EG-NEXT:     ADD_INT T1.Y, PV.W, literal.x,
+; EG-NEXT:     AND_INT T2.Z, KC0[3].Y, literal.y,
+; EG-NEXT:     LSHL T4.W, PS, PV.Z,
+; EG-NEXT:     AND_INT * T5.W, T2.X, literal.z,
+; EG-NEXT:    -150(nan), 8388607(1.175494e-38)
+; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
+; EG-NEXT:     NOT_INT T4.Y, T2.X,
+; EG-NEXT:     OR_INT T1.Z, PV.Z, literal.x,
+; EG-NEXT:     NOT_INT T6.W, PV.Y,
+; EG-NEXT:     SUB_INT * T7.W, literal.y, T0.W,
+; EG-NEXT:    8388608(1.175494e-38), 150(2.101948e-43)
+; EG-NEXT:     ADD_INT T2.X, T0.W, literal.x,
+; EG-NEXT:     AND_INT T5.Y, T1.Y, literal.y,
+; EG-NEXT:     AND_INT * T2.Z, PS, literal.y,
+; EG-NEXT:    -127(nan), 31(4.344025e-44)
+; EG-NEXT:    ALU clause starting at 107:
+; EG-NEXT:     AND_INT T0.W, T6.W, literal.x,
+; EG-NEXT:     LSHR * T6.W, T1.Z, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T4.Y, T1.W, PV.Z,
-; EG-NEXT:     AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
-; EG-NEXT:     BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
-; EG-NEXT:     AND_INT * T3.W, PV.Y, literal.x,
+; EG-NEXT:     LSHR T5.X, PS, PV.W,
+; EG-NEXT:     LSHR T6.Y, T1.Z, T2.Z,
+; EG-NEXT:     AND_INT T2.Z, T7.W, literal.x,
+; EG-NEXT:     LSHL T0.W, T1.Z, T5.Y,
+; EG-NEXT:     AND_INT * T6.W, T1.Y, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     ADD_INT T6.X, T1.X, literal.x,
-; EG-NEXT:     CNDE_INT T3.Y, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
-; EG-NEXT:    -150(nan), 0(0.000000e+00)
-; EG-NEXT:    ALU clause starting at 108:
-; EG-NEXT:     CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
-; EG-NEXT:     SETGT_INT * T3.W, T4.X, literal.x,
-; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T3.X, PS, 0.0, PV.W,
-; EG-NEXT:     CNDE_INT T3.Y, PS, T3.Y, T3.Z,
-; EG-NEXT:     AND_INT T2.Z, T6.X, literal.x,
-; EG-NEXT:     NOT_INT T1.W, T6.X,
-; EG-NEXT:     LSHR * T3.W, T0.W, 1,
+; EG-NEXT:     SUB_INT T6.X, literal.x, T1.W,
+; EG-NEXT:     CNDE_INT T1.Y, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
+; EG-NEXT:     CNDE_INT T0.W, PS, PV.X, PV.W,
+; EG-NEXT:     SETGT_INT * T6.W, T2.X, literal.y,
+; EG-NEXT:    150(2.101948e-43), 23(3.222986e-44)
+; EG-NEXT:     CNDE_INT T5.X, PS, 0.0, PV.W,
+; EG-NEXT:     CNDE_INT T1.Y, PS, PV.Z, PV.Y,
+; EG-NEXT:     AND_INT T1.Z, PV.X, literal.x,
+; EG-NEXT:     AND_INT T0.W, T4.Y, literal.x,
+; EG-NEXT:     LSHR * T6.W, T3.W, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     ASHR T7.X, KC0[3].Y, literal.x,
-; EG-NEXT:     ADD_INT T4.Y, T1.X, literal.y,
-; EG-NEXT:     BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
-; EG-NEXT:     LSHL T0.W, T0.W, PV.Z,
+; EG-NEXT:     ADD_INT T4.Y, T1.W, literal.y,
+; EG-NEXT:     LSHR T2.Z, PS, PV.W,
+; EG-NEXT:     LSHR T0.W, T3.W, PV.Z, BS:VEC_120/SCL_212
 ; EG-NEXT:     AND_INT * T1.W, T6.X, literal.z,
 ; EG-NEXT:    31(4.344025e-44), -127(nan)
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, 0.0,
-; EG-NEXT:     CNDE_INT T5.Y, PS, PV.Z, PV.W,
-; EG-NEXT:     SETGT_INT T2.Z, PV.Y, literal.x,
-; EG-NEXT:     XOR_INT T0.W, T3.Y, PV.X,
-; EG-NEXT:     XOR_INT * T1.W, T3.X, PV.X,
+; EG-NEXT:     CNDE_INT T6.X, PS, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T5.Y, T5.W, PV.Z, T4.W,
+; EG-NEXT:     SETGT_INT T1.Z, PV.Y, literal.x,
+; EG-NEXT:     XOR_INT T0.W, T1.Y, PV.X,
+; EG-NEXT:     XOR_INT * T1.W, T5.X, PV.X,
 ; EG-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; EG-NEXT:     SUB_INT T3.X, PS, T7.X,
-; EG-NEXT:     SUBB_UINT T3.Y, PV.W, T7.X,
-; EG-NEXT:     CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
-; EG-NEXT:     CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
+; EG-NEXT:     SUB_INT T5.X, PS, T7.X,
+; EG-NEXT:     SUBB_UINT T1.Y, PV.W, T7.X,
+; EG-NEXT:     CNDE_INT T2.Z, PV.Z, 0.0, PV.Y,
+; EG-NEXT:     CNDE_INT T1.W, PV.Z, PV.X, T1.X,
 ; EG-NEXT:     ASHR * T3.W, KC0[3].W, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     XOR_INT T1.X, PV.W, PS,
 ; EG-NEXT:     XOR_INT T5.Y, PV.Z, PS,
-; EG-NEXT:     SUB_INT T0.Z, PV.X, PV.Y,
-; EG-NEXT:     SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
-; EG-NEXT:     CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
-; EG-NEXT:     SETGT_INT T0.X, 0.0, T0.X,
+; EG-NEXT:     SUB_INT T1.Z, PV.X, PV.Y,
+; EG-NEXT:     SETGT_INT T1.W, 0.0, T2.X,
+; EG-NEXT:     CNDE_INT * T6.W, T0.X, T0.Y, 0.0,
+; EG-NEXT:     SETGT_INT T2.X, 0.0, T3.Y,
 ; EG-NEXT:     CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
-; EG-NEXT:     SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
-; EG-NEXT:     SUB_INT T2.W, PV.Y, T3.W,
-; EG-NEXT:     SUBB_UINT * T4.W, PV.X, T3.W,
-; EG-NEXT:     SUB_INT T3.X, PV.W, PS,
-; EG-NEXT:     SETGT_INT T1.Y, 0.0, T4.Y,
-; EG-NEXT:     CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
+; EG-NEXT:     SUB_INT T0.Z, T0.Z, T2.Y, BS:VEC_021/SCL_122
+; EG-NEXT:     SUB_INT T4.W, PV.Y, T3.W,
+; EG-NEXT:     SUBB_UINT * T5.W, PV.X, T3.W,
+; EG-NEXT:     SUB_INT T5.X, PV.W, PS,
+; EG-NEXT:     SETGT_INT T0.Y, 0.0, T4.Y,
+; EG-NEXT:     CNDE_INT T6.Z, T0.X, PV.Z, 0.0,
 ; EG-NEXT:     SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
-; EG-NEXT:     CNDE_INT * T4.W, PV.X, T2.X, 0.0,
+; EG-NEXT:     CNDE_INT * T4.W, PV.X, T4.X, 0.0,
 ; EG-NEXT:     CNDE_INT T6.X, T1.W, PV.W, 0.0,
 ; EG-NEXT:     CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
-; EG-NEXT:     SUB_INT T0.W, T1.Z, T2.Y,
-; EG-NEXT:     LSHR * T2.X, KC0[2].Y, literal.x,
+; EG-NEXT:     SUB_INT T0.W, T3.X, T2.W,
+; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T4.Z, T0.X, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T4.Z, T2.X, PV.W, 0.0,
 ; EG-NEXT:     SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
-; EG-NEXT:     CNDE_INT T4.X, T1.Y, PV.W, 0.0,
+; EG-NEXT:     CNDE_INT T4.X, T0.Y, PV.W, 0.0,
 ; EG-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
 ; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT:     LSHR * T0.X, PV.W, literal.x,
+; EG-NEXT:     LSHR * T1.X, PV.W, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %conv = fptoui <4 x float> %x to <4 x i64>
   store <4 x i64> %conv, ptr addrspace(1) %out
   ret void
 }
 
 define amdgpu_kernel void @fp_to_uint_f32_to_i1(ptr addrspace(1) %out, float %in) #0 {
 ; SI-LABEL: fp_to_uint_f32_to_i1:

llvm/test/CodeGen/AMDGPU/fshl.ll

 define amdgpu_kernel void @fshl_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z) {
 ; SI-LABEL: fshl_i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; SI-NEXT:    s_load_dword s8, s[0:1], 0xd
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-NEXT:    s_mov_b32 s0, s4
 ; SI-NEXT:    s_mov_b32 s1, s5
-; SI-NEXT:    v_mov_b32_e32 v0, s7
+; SI-NEXT:    s_lshr_b32 s4, s7, 1
+; SI-NEXT:    s_lshl_b32 s5, s6, 31
+; SI-NEXT:    s_or_b32 s4, s5, s4
 ; SI-NEXT:    s_not_b32 s5, s8
-; SI-NEXT:    s_mov_b32 s0, s4
-; SI-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; SI-NEXT:    s_lshr_b32 s4, s6, 1
-; SI-NEXT:    v_mov_b32_e32 v1, s5
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, v1
+; SI-NEXT:    s_lshr_b32 s4, s4, s5
+; SI-NEXT:    s_and_b32 s5, s6, -2
+; SI-NEXT:    s_lshl_b32 s5, s5, s8
+; SI-NEXT:    s_or_b32 s4, s5, s4
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; VI-NEXT:    s_load_dword s0, s[0:1], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    s_not_b32 s0, s0
-; VI-NEXT:    s_lshr_b32 s1, s6, 1
-; VI-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s0
-; VI-NEXT:    v_alignbit_b32 v2, s1, v0, v1
+; VI-NEXT:    s_lshr_b32 s1, s7, 1
+; VI-NEXT:    s_lshl_b32 s2, s6, 31
+; VI-NEXT:    s_not_b32 s3, s0
+; VI-NEXT:    s_and_b32 s6, s6, -2
+; VI-NEXT:    s_or_b32 s1, s2, s1
+; VI-NEXT:    s_lshr_b32 s1, s1, s3
+; VI-NEXT:    s_lshl_b32 s0, s6, s0
+; VI-NEXT:    s_or_b32 s0, s0, s1
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s7
-; GFX9-NEXT:    s_not_b32 s1, s2
-; GFX9-NEXT:    s_lshr_b32 s0, s6, 1
-; GFX9-NEXT:    v_alignbit_b32 v1, s6, v1, 1
-; GFX9-NEXT:    v_mov_b32_e32 v2, s1
-; GFX9-NEXT:    v_alignbit_b32 v1, s0, v1, v2
+; GFX9-NEXT:    s_lshr_b32 s0, s7, 1
+; GFX9-NEXT:    s_lshl_b32 s1, s6, 31
+; GFX9-NEXT:    s_not_b32 s3, s2
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    s_and_b32 s1, s6, -2
+; GFX9-NEXT:    s_lshr_b32 s0, s0, s3
+; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 13, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LSHR T0.Z, KC0[2].Z, 1,
-; R600-NEXT:     BIT_ALIGN_INT T0.W, KC0[2].Z, KC0[2].W, 1,
+; R600-NEXT:     LSHL T0.Z, KC0[2].Z, literal.x,
+; R600-NEXT:     LSHR T0.W, KC0[2].W, 1,
 ; R600-NEXT:     NOT_INT * T1.W, KC0[3].X,
-; R600-NEXT:     BIT_ALIGN_INT T0.X, PV.Z, PV.W, PS,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     AND_INT T0.Y, KC0[2].Z, literal.x,
+; R600-NEXT:     AND_INT T1.Z, KC0[3].X, literal.y,
+; R600-NEXT:     AND_INT T1.W, PS, literal.y,
+; R600-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
+; R600-NEXT:    -2(nan), 31(4.344025e-44)
+; R600-NEXT:     LSHR T0.W, PS, PV.W,
+; R600-NEXT:     LSHL * T1.W, PV.Y, PV.Z,
+; R600-NEXT:     OR_INT T0.X, PS, PV.W,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX10-NEXT:    s_load_dword s2, s[0:1], 0x34
-; GFX10-NEXT:    v_mov_b32_e32 v1, 0
+; GFX10-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v0, s6, s7, 1
-; GFX10-NEXT:    s_lshr_b32 s0, s6, 1
-; GFX10-NEXT:    s_not_b32 s1, s2
-; GFX10-NEXT:    v_alignbit_b32 v0, s0, v0, s1
-; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]
+; GFX10-NEXT:    s_lshr_b32 s0, s7, 1
+; GFX10-NEXT:    s_lshl_b32 s1, s6, 31
+; GFX10-NEXT:    s_not_b32 s3, s2
+; GFX10-NEXT:    s_or_b32 s0, s1, s0
+; GFX10-NEXT:    s_and_b32 s1, s6, -2
+; GFX10-NEXT:    s_lshr_b32 s0, s0, s3
+; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX10-NEXT:    s_or_b32 s0, s1, s0
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
+; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
 ; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, s6, s7, 1
-; GFX11-NEXT:    s_lshr_b32 s1, s6, 1
-; GFX11-NEXT:    s_not_b32 s0, s0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s1, v0, s0
-; GFX11-NEXT:    global_store_b32 v1, v0, s[4:5]
+; GFX11-NEXT:    s_lshr_b32 s1, s7, 1
+; GFX11-NEXT:    s_lshl_b32 s2, s6, 31
+; GFX11-NEXT:    s_not_b32 s3, s0
+; GFX11-NEXT:    s_or_b32 s1, s2, s1
+; GFX11-NEXT:    s_and_b32 s2, s6, -2
+; GFX11-NEXT:    s_lshr_b32 s1, s1, s3
+; GFX11-NEXT:    s_lshl_b32 s0, s2, s0
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_or_b32 s0, s0, s1
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT:    global_store_b32 v0, v1, s[4:5]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
   store i32 %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
 ; SI-LABEL: fshl_i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s3
 ; SI-NEXT:    s_mov_b32 s4, s0
 ; SI-NEXT:    s_mov_b32 s5, s1
-; SI-NEXT:    v_alignbit_b32 v0, s2, v0, 25
+; SI-NEXT:    s_lshr_b32 s0, s3, 25
+; SI-NEXT:    s_lshl_b32 s1, s2, 7
+; SI-NEXT:    s_or_b32 s0, s1, s0
+; SI-NEXT:    v_mov_b32_e32 v0, s0
 ; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    v_alignbit_b32 v2, s2, v0, 25
+; VI-NEXT:    s_lshr_b32 s3, s3, 25
+; VI-NEXT:    s_lshl_b32 s2, s2, 7
+; VI-NEXT:    s_or_b32 s2, s2, s3
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    v_mov_b32_e32 v2, s2
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_alignbit_b32 v1, s2, v1, 25
+; GFX9-NEXT:    s_lshr_b32 s3, s3, 25
+; GFX9-NEXT:    s_lshl_b32 s2, s2, 7
+; GFX9-NEXT:    s_or_b32 s2, s2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_i32_imm:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
+; R600-NEXT:     LSHL T0.W, KC0[2].Z, literal.x,
+; R600-NEXT:     LSHR * T1.W, KC0[2].W, literal.y,
+; R600-NEXT:    7(9.809089e-45), 25(3.503246e-44)
+; R600-NEXT:     OR_INT T0.X, PV.W, PS,
+; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,
-; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v1, s2, s3, 25
+; GFX10-NEXT:    s_lshr_b32 s3, s3, 25
+; GFX10-NEXT:    s_lshl_b32 s2, s2, 7
+; GFX10-NEXT:    s_or_b32 s2, s2, s3
+; GFX10-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, s2, s3, 25
+; GFX11-NEXT:    s_lshr_b32 s3, s3, 25
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 7
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_or_b32 s2, s2, s3
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
 ; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 7)
   store i32 %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
 ; SI-LABEL: fshl_v2i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xf
 ; SI-NEXT:    s_mov_b32 s11, 0xf000
 ; SI-NEXT:    s_mov_b32 s10, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; SI-NEXT:    s_not_b32 s1, s1
-; SI-NEXT:    s_lshr_b32 s2, s5, 1
+; SI-NEXT:    s_lshr_b32 s2, s7, 1
+; SI-NEXT:    s_lshl_b32 s3, s5, 31
+; SI-NEXT:    s_or_b32 s2, s3, s2
+; SI-NEXT:    s_not_b32 s3, s1
+; SI-NEXT:    s_lshr_b32 s2, s2, s3
+; SI-NEXT:    s_and_b32 s3, s5, -2
+; SI-NEXT:    s_lshl_b32 s1, s3, s1
+; SI-NEXT:    s_or_b32 s1, s1, s2
+; SI-NEXT:    s_lshr_b32 s2, s6, 1
+; SI-NEXT:    s_lshl_b32 s3, s4, 31
+; SI-NEXT:    s_or_b32 s2, s3, s2
+; SI-NEXT:    s_not_b32 s3, s0
+; SI-NEXT:    s_lshr_b32 s2, s2, s3
+; SI-NEXT:    s_and_b32 s3, s4, -2
+; SI-NEXT:    s_lshl_b32 s0, s3, s0
+; SI-NEXT:    s_or_b32 s0, s0, s2
+; SI-NEXT:    v_mov_b32_e32 v0, s0
 ; SI-NEXT:    v_mov_b32_e32 v1, s1
-; SI-NEXT:    v_alignbit_b32 v1, s2, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s6
-; SI-NEXT:    s_not_b32 s0, s0
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; SI-NEXT:    s_lshr_b32 s1, s4, 1
-; SI-NEXT:    v_mov_b32_e32 v2, s0
-; SI-NEXT:    v_alignbit_b32 v0, s1, v0, v2
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_v2i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    s_not_b32 s3, s3
-; VI-NEXT:    s_lshr_b32 s7, s5, 1
-; VI-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_alignbit_b32 v1, s7, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s6
-; VI-NEXT:    s_not_b32 s2, s2
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; VI-NEXT:    s_lshr_b32 s3, s4, 1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_alignbit_b32 v0, s3, v0, v2
+; VI-NEXT:    s_lshl_b32 s8, s5, 31
+; VI-NEXT:    s_and_b32 s5, s5, -2
+; VI-NEXT:    s_lshr_b32 s7, s7, 1
+; VI-NEXT:    s_not_b32 s9, s3
+; VI-NEXT:    s_lshl_b32 s3, s5, s3
+; VI-NEXT:    s_lshr_b32 s5, s6, 1
+; VI-NEXT:    s_lshl_b32 s6, s4, 31
+; VI-NEXT:    s_or_b32 s7, s8, s7
+; VI-NEXT:    s_or_b32 s5, s6, s5
+; VI-NEXT:    s_not_b32 s6, s2
+; VI-NEXT:    s_and_b32 s4, s4, -2
+; VI-NEXT:    s_lshr_b32 s7, s7, s9
+; VI-NEXT:    s_lshr_b32 s5, s5, s6
+; VI-NEXT:    s_lshl_b32 s2, s4, s2
+; VI-NEXT:    s_or_b32 s3, s3, s7
+; VI-NEXT:    s_or_b32 s2, s2, s5
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_v2i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x3c
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    s_lshr_b32 s0, s5, 1
+; GFX9-NEXT:    s_lshr_b32 s0, s7, 1
+; GFX9-NEXT:    s_lshl_b32 s1, s5, 31
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
 ; GFX9-NEXT:    s_not_b32 s1, s9
-; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_alignbit_b32 v1, s0, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s6
-; GFX9-NEXT:    s_not_b32 s1, s8
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; GFX9-NEXT:    s_lshr_b32 s0, s4, 1
-; GFX9-NEXT:    v_mov_b32_e32 v3, s1
-; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v3
+; GFX9-NEXT:    s_lshr_b32 s0, s0, s1
+; GFX9-NEXT:    s_and_b32 s1, s5, -2
+; GFX9-NEXT:    s_lshl_b32 s1, s1, s9
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    s_lshr_b32 s1, s6, 1
+; GFX9-NEXT:    s_lshl_b32 s5, s4, 31
+; GFX9-NEXT:    s_or_b32 s1, s5, s1
+; GFX9-NEXT:    s_not_b32 s5, s8
+; GFX9-NEXT:    s_and_b32 s4, s4, -2
+; GFX9-NEXT:    s_lshr_b32 s1, s1, s5
+; GFX9-NEXT:    s_lshl_b32 s4, s4, s8
+; GFX9-NEXT:    s_or_b32 s1, s4, s1
+; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_v2i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 25, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LSHR T0.Z, KC0[3].X, 1,
-; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[3].X, KC0[3].Z, 1,
-; R600-NEXT:     NOT_INT * T1.W, KC0[4].X,
-; R600-NEXT:     BIT_ALIGN_INT T0.Y, T0.Z, T0.W, PV.W,
-; R600-NEXT:     LSHR T0.Z, KC0[2].W, 1,
-; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[2].W, KC0[3].Y, 1,
-; R600-NEXT:     NOT_INT * T1.W, KC0[3].W,
-; R600-NEXT:     BIT_ALIGN_INT T0.X, T0.Z, T0.W, PV.W,
+; R600-NEXT:     AND_INT T0.W, KC0[2].W, literal.x,
+; R600-NEXT:     AND_INT * T1.W, KC0[4].X, literal.y,
+; R600-NEXT:    -2(nan), 31(4.344025e-44)
+; R600-NEXT:     AND_INT T0.Y, KC0[3].X, literal.x,
+; R600-NEXT:     LSHL T0.Z, KC0[3].X, literal.y,
+; R600-NEXT:     LSHR * T2.W, KC0[3].Z, 1,
+; R600-NEXT:    -2(nan), 31(4.344025e-44)
+; R600-NEXT:     NOT_INT * T3.W, KC0[4].X,
+; R600-NEXT:     AND_INT T0.X, PV.W, literal.x,
+; R600-NEXT:     OR_INT T1.Y, T0.Z, T2.W,
+; R600-NEXT:     LSHL T0.Z, KC0[2].W, literal.x,
+; R600-NEXT:     LSHR * T2.W, KC0[3].Y, 1,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     NOT_INT * T3.W, KC0[3].W,
+; R600-NEXT:     AND_INT T1.X, KC0[3].W, literal.x,
+; R600-NEXT:     AND_INT T2.Y, PV.W, literal.x,
+; R600-NEXT:     OR_INT T0.Z, T0.Z, T2.W, BS:VEC_021/SCL_122
+; R600-NEXT:     LSHR T2.W, T1.Y, T0.X,
+; R600-NEXT:     LSHL * T1.W, T0.Y, T1.W,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     OR_INT T0.Y, PS, PV.W,
+; R600-NEXT:     LSHR T1.W, PV.Z, PV.Y,
+; R600-NEXT:     LSHL * T0.W, T0.W, PV.X,
+; R600-NEXT:     OR_INT T0.X, PS, PV.W,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_v2i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x2
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; GFX10-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v0, s5, s7, 1
-; GFX10-NEXT:    v_alignbit_b32 v3, s4, s6, 1
-; GFX10-NEXT:    s_lshr_b32 s0, s5, 1
-; GFX10-NEXT:    s_not_b32 s1, s3
-; GFX10-NEXT:    s_lshr_b32 s3, s4, 1
-; GFX10-NEXT:    s_not_b32 s2, s2
-; GFX10-NEXT:    v_alignbit_b32 v1, s0, v0, s1
-; GFX10-NEXT:    v_alignbit_b32 v0, s3, v3, s2
+; GFX10-NEXT:    s_lshr_b32 s0, s7, 1
+; GFX10-NEXT:    s_lshl_b32 s1, s5, 31
+; GFX10-NEXT:    s_and_b32 s5, s5, -2
+; GFX10-NEXT:    s_lshr_b32 s6, s6, 1
+; GFX10-NEXT:    s_lshl_b32 s10, s4, 31
+; GFX10-NEXT:    s_not_b32 s7, s3
+; GFX10-NEXT:    s_not_b32 s11, s2
+; GFX10-NEXT:    s_and_b32 s4, s4, -2
+; GFX10-NEXT:    s_or_b32 s0, s1, s0
+; GFX10-NEXT:    s_lshl_b32 s1, s5, s3
+; GFX10-NEXT:    s_or_b32 s3, s10, s6
+; GFX10-NEXT:    s_lshl_b32 s2, s4, s2
+; GFX10-NEXT:    s_lshr_b32 s3, s3, s11
+; GFX10-NEXT:    s_lshr_b32 s0, s0, s7
+; GFX10-NEXT:    s_or_b32 s2, s2, s3
+; GFX10-NEXT:    s_or_b32 s0, s1, s0
+; GFX10-NEXT:    v_mov_b32_e32 v0, s2
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_v2i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
 ; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x3c
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, s5, s7, 1
-; GFX11-NEXT:    v_alignbit_b32 v3, s4, s6, 1
-; GFX11-NEXT:    s_lshr_b32 s5, s5, 1
-; GFX11-NEXT:    s_not_b32 s3, s3
-; GFX11-NEXT:    s_lshr_b32 s4, s4, 1
-; GFX11-NEXT:    s_not_b32 s2, s2
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, v0, s3
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, v3, s2
+; GFX11-NEXT:    s_lshr_b32 s7, s7, 1
+; GFX11-NEXT:    s_lshl_b32 s8, s5, 31
+; GFX11-NEXT:    s_and_b32 s5, s5, -2
+; GFX11-NEXT:    s_lshr_b32 s6, s6, 1
+; GFX11-NEXT:    s_lshl_b32 s10, s4, 31
+; GFX11-NEXT:    s_not_b32 s9, s3
+; GFX11-NEXT:    s_not_b32 s11, s2
+; GFX11-NEXT:    s_and_b32 s4, s4, -2
+; GFX11-NEXT:    s_or_b32 s7, s8, s7
+; GFX11-NEXT:    s_lshl_b32 s3, s5, s3
+; GFX11-NEXT:    s_or_b32 s5, s10, s6
+; GFX11-NEXT:    s_lshl_b32 s2, s4, s2
+; GFX11-NEXT:    s_lshr_b32 s4, s5, s11
+; GFX11-NEXT:    s_lshr_b32 s5, s7, s9
+; GFX11-NEXT:    s_or_b32 s2, s2, s4
+; GFX11-NEXT:    s_or_b32 s3, s3, s5
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
   store <2 x i32> %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
 ; SI-LABEL: fshl_v2i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_mov_b32_e32 v2, s6
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 23
-; SI-NEXT:    v_alignbit_b32 v0, s4, v2, 25
+; SI-NEXT:    s_lshr_b32 s7, s7, 23
+; SI-NEXT:    s_lshl_b32 s5, s5, 9
+; SI-NEXT:    s_lshr_b32 s6, s6, 25
+; SI-NEXT:    s_lshl_b32 s4, s4, 7
+; SI-NEXT:    s_or_b32 s5, s5, s7
+; SI-NEXT:    s_or_b32 s4, s4, s6
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s5
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_v2i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    v_mov_b32_e32 v2, s6
-; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 23
-; VI-NEXT:    v_alignbit_b32 v0, s4, v2, 25
+; VI-NEXT:    s_lshr_b32 s2, s7, 23
+; VI-NEXT:    s_lshl_b32 s3, s5, 9
+; VI-NEXT:    s_lshr_b32 s5, s6, 25
+; VI-NEXT:    s_lshl_b32 s4, s4, 7
+; VI-NEXT:    s_or_b32 s2, s3, s2
+; VI-NEXT:    s_or_b32 s3, s4, s5
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s3
+; VI-NEXT:    v_mov_b32_e32 v1, s2
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_v2i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    v_mov_b32_e32 v3, s6
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 23
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v3, 25
+; GFX9-NEXT:    s_lshr_b32 s0, s7, 23
+; GFX9-NEXT:    s_lshl_b32 s1, s5, 9
+; GFX9-NEXT:    s_lshr_b32 s5, s6, 25
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    s_lshl_b32 s1, s4, 7
+; GFX9-NEXT:    s_or_b32 s1, s1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_v2i32_imm:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
-; R600-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
-; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
+; R600-NEXT:     LSHL T0.W, KC0[3].X, literal.x,
+; R600-NEXT:     LSHR * T1.W, KC0[3].Z, literal.y,
+; R600-NEXT:    9(1.261169e-44), 23(3.222986e-44)
+; R600-NEXT:     OR_INT T0.Y, PV.W, PS,
+; R600-NEXT:     LSHL T0.W, KC0[2].W, literal.x,
+; R600-NEXT:     LSHR * T1.W, KC0[3].Y, literal.y,
+; R600-NEXT:    7(9.809089e-45), 25(3.503246e-44)
+; R600-NEXT:     OR_INT T0.X, PV.W, PS,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_v2i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s7, 23
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s6, 25
+; GFX10-NEXT:    s_lshr_b32 s0, s7, 23
+; GFX10-NEXT:    s_lshr_b32 s1, s6, 25
+; GFX10-NEXT:    s_lshl_b32 s4, s4, 7
+; GFX10-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX10-NEXT:    s_or_b32 s1, s4, s1
+; GFX10-NEXT:    s_or_b32 s0, s5, s0
+; GFX10-NEXT:    v_mov_b32_e32 v0, s1
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_v2i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s7, 23
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s6, 25
+; GFX11-NEXT:    s_lshr_b32 s2, s7, 23
+; GFX11-NEXT:    s_lshr_b32 s3, s6, 25
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 7
+; GFX11-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX11-NEXT:    s_or_b32 s3, s4, s3
+; GFX11-NEXT:    s_or_b32 s2, s5, s2
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT:    v_mov_b32_e32 v0, s3
 ; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
   store <2 x i32> %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
 ; SI-LABEL: fshl_v4i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
 ; SI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x15
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    s_not_b32 s11, s15
-; SI-NEXT:    v_alignbit_b32 v0, s7, v0, 1
-; SI-NEXT:    s_lshr_b32 s7, s7, 1
-; SI-NEXT:    v_mov_b32_e32 v1, s11
-; SI-NEXT:    v_alignbit_b32 v3, s7, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s10
-; SI-NEXT:    s_not_b32 s7, s14
-; SI-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; SI-NEXT:    s_lshr_b32 s6, s6, 1
-; SI-NEXT:    v_mov_b32_e32 v1, s7
-; SI-NEXT:    v_alignbit_b32 v2, s6, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    s_not_b32 s6, s13
-; SI-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; SI-NEXT:    s_lshr_b32 s5, s5, 1
-; SI-NEXT:    v_mov_b32_e32 v1, s6
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s8
-; SI-NEXT:    s_not_b32 s5, s12
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; SI-NEXT:    s_lshr_b32 s4, s4, 1
-; SI-NEXT:    v_mov_b32_e32 v4, s5
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
+; SI-NEXT:    s_lshr_b32 s11, s11, 1
+; SI-NEXT:    s_lshl_b32 s16, s7, 31
+; SI-NEXT:    s_or_b32 s11, s16, s11
+; SI-NEXT:    s_not_b32 s16, s15
+; SI-NEXT:    s_and_b32 s7, s7, -2
+; SI-NEXT:    s_lshr_b32 s11, s11, s16
+; SI-NEXT:    s_lshl_b32 s7, s7, s15
+; SI-NEXT:    s_or_b32 s7, s7, s11
+; SI-NEXT:    s_lshr_b32 s10, s10, 1
+; SI-NEXT:    s_lshl_b32 s11, s6, 31
+; SI-NEXT:    s_or_b32 s10, s11, s10
+; SI-NEXT:    s_not_b32 s11, s14
+; SI-NEXT:    s_and_b32 s6, s6, -2
+; SI-NEXT:    s_lshr_b32 s10, s10, s11
+; SI-NEXT:    s_lshl_b32 s6, s6, s14
+; SI-NEXT:    s_or_b32 s6, s6, s10
+; SI-NEXT:    s_lshr_b32 s9, s9, 1
+; SI-NEXT:    s_lshl_b32 s10, s5, 31
+; SI-NEXT:    s_or_b32 s9, s10, s9
+; SI-NEXT:    s_not_b32 s10, s13
+; SI-NEXT:    s_and_b32 s5, s5, -2
+; SI-NEXT:    s_lshr_b32 s9, s9, s10
+; SI-NEXT:    s_lshl_b32 s5, s5, s13
+; SI-NEXT:    s_or_b32 s5, s5, s9
+; SI-NEXT:    s_lshr_b32 s8, s8, 1
+; SI-NEXT:    s_lshl_b32 s9, s4, 31
+; SI-NEXT:    s_or_b32 s8, s9, s8
+; SI-NEXT:    s_not_b32 s9, s12
+; SI-NEXT:    s_and_b32 s4, s4, -2
+; SI-NEXT:    s_lshr_b32 s8, s8, s9
+; SI-NEXT:    s_lshl_b32 s4, s4, s12
+; SI-NEXT:    s_or_b32 s4, s4, s8
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s5
+; SI-NEXT:    v_mov_b32_e32 v2, s6
+; SI-NEXT:    v_mov_b32_e32 v3, s7
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_v4i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    s_not_b32 s3, s15
-; VI-NEXT:    s_lshr_b32 s2, s7, 1
-; VI-NEXT:    v_alignbit_b32 v0, s7, v0, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_alignbit_b32 v3, s2, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s10
-; VI-NEXT:    s_not_b32 s3, s14
-; VI-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; VI-NEXT:    s_lshr_b32 s2, s6, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_alignbit_b32 v2, s2, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s9
-; VI-NEXT:    s_not_b32 s3, s13
-; VI-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; VI-NEXT:    s_lshr_b32 s2, s5, 1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_alignbit_b32 v1, s2, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s8
-; VI-NEXT:    s_not_b32 s3, s12
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; VI-NEXT:    s_lshr_b32 s2, s4, 1
-; VI-NEXT:    v_mov_b32_e32 v4, s3
-; VI-NEXT:    v_alignbit_b32 v0, s2, v0, v4
+; VI-NEXT:    s_lshr_b32 s2, s11, 1
+; VI-NEXT:    s_lshl_b32 s3, s7, 31
+; VI-NEXT:    s_not_b32 s11, s15
+; VI-NEXT:    s_or_b32 s2, s3, s2
+; VI-NEXT:    s_and_b32 s3, s7, -2
+; VI-NEXT:    s_lshr_b32 s2, s2, s11
+; VI-NEXT:    s_lshl_b32 s3, s3, s15
+; VI-NEXT:    s_or_b32 s2, s3, s2
+; VI-NEXT:    s_lshr_b32 s3, s10, 1
+; VI-NEXT:    s_lshl_b32 s7, s6, 31
+; VI-NEXT:    s_or_b32 s3, s7, s3
+; VI-NEXT:    s_not_b32 s7, s14
+; VI-NEXT:    s_and_b32 s6, s6, -2
+; VI-NEXT:    s_lshr_b32 s3, s3, s7
+; VI-NEXT:    s_lshl_b32 s6, s6, s14
+; VI-NEXT:    s_or_b32 s3, s6, s3
+; VI-NEXT:    s_lshr_b32 s6, s9, 1
+; VI-NEXT:    s_lshl_b32 s7, s5, 31
+; VI-NEXT:    s_or_b32 s6, s7, s6
+; VI-NEXT:    s_not_b32 s7, s13
+; VI-NEXT:    s_and_b32 s5, s5, -2
+; VI-NEXT:    s_lshr_b32 s6, s6, s7
+; VI-NEXT:    s_lshl_b32 s5, s5, s13
+; VI-NEXT:    s_or_b32 s5, s5, s6
+; VI-NEXT:    s_lshr_b32 s6, s8, 1
+; VI-NEXT:    s_lshl_b32 s7, s4, 31
+; VI-NEXT:    s_or_b32 s6, s7, s6
+; VI-NEXT:    s_not_b32 s7, s12
+; VI-NEXT:    s_and_b32 s4, s4, -2
+; VI-NEXT:    s_lshr_b32 s6, s6, s7
+; VI-NEXT:    s_lshl_b32 s4, s4, s12
+; VI-NEXT:    s_or_b32 s4, s4, s6
 ; VI-NEXT:    v_mov_b32_e32 v5, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    v_mov_b32_e32 v2, s3
+; VI-NEXT:    v_mov_b32_e32 v3, s2
 ; VI-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_v4i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX9-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_lshr_b32 s0, s11, 1
+; GFX9-NEXT:    s_lshl_b32 s1, s7, 31
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
 ; GFX9-NEXT:    s_not_b32 s1, s15
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
-; GFX9-NEXT:    s_lshr_b32 s0, s7, 1
-; GFX9-NEXT:    v_alignbit_b32 v0, s7, v0, 1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_alignbit_b32 v3, s0, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s10
-; GFX9-NEXT:    s_not_b32 s1, s14
-; GFX9-NEXT:    v_alignbit_b32 v0, s6, v0, 1
-; GFX9-NEXT:    s_lshr_b32 s0, s6, 1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_alignbit_b32 v2, s0, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s9
-; GFX9-NEXT:    s_not_b32 s1, s13
-; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 1
-; GFX9-NEXT:    s_lshr_b32 s0, s5, 1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_alignbit_b32 v1, s0, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s8
-; GFX9-NEXT:    s_not_b32 s1, s12
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 1
-; GFX9-NEXT:    s_lshr_b32 s0, s4, 1
-; GFX9-NEXT:    v_mov_b32_e32 v5, s1
-; GFX9-NEXT:    v_alignbit_b32 v0, s0, v0, v5
+; GFX9-NEXT:    s_lshr_b32 s0, s0, s1
+; GFX9-NEXT:    s_and_b32 s1, s7, -2
+; GFX9-NEXT:    s_lshl_b32 s1, s1, s15
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    s_lshr_b32 s1, s10, 1
+; GFX9-NEXT:    s_lshl_b32 s7, s6, 31
+; GFX9-NEXT:    s_or_b32 s1, s7, s1
+; GFX9-NEXT:    s_not_b32 s7, s14
+; GFX9-NEXT:    s_and_b32 s6, s6, -2
+; GFX9-NEXT:    s_lshr_b32 s1, s1, s7
+; GFX9-NEXT:    s_lshl_b32 s6, s6, s14
+; GFX9-NEXT:    s_or_b32 s1, s6, s1
+; GFX9-NEXT:    s_lshr_b32 s6, s9, 1
+; GFX9-NEXT:    s_lshl_b32 s7, s5, 31
+; GFX9-NEXT:    s_or_b32 s6, s7, s6
+; GFX9-NEXT:    s_not_b32 s7, s13
+; GFX9-NEXT:    s_and_b32 s5, s5, -2
+; GFX9-NEXT:    s_lshr_b32 s6, s6, s7
+; GFX9-NEXT:    s_lshl_b32 s5, s5, s13
+; GFX9-NEXT:    s_or_b32 s5, s5, s6
+; GFX9-NEXT:    s_lshr_b32 s6, s8, 1
+; GFX9-NEXT:    s_lshl_b32 s7, s4, 31
+; GFX9-NEXT:    s_or_b32 s6, s7, s6
+; GFX9-NEXT:    s_not_b32 s7, s12
+; GFX9-NEXT:    s_and_b32 s4, s4, -2
+; GFX9-NEXT:    s_lshr_b32 s6, s6, s7
+; GFX9-NEXT:    s_lshl_b32 s4, s4, s12
+; GFX9-NEXT:    s_or_b32 s4, s4, s6
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v2, s1
+; GFX9-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_v4i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 17, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; R600-NEXT:    ALU 49, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LSHR T0.Z, KC0[4].X, 1,
-; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1,
-; R600-NEXT:     NOT_INT * T1.W, KC0[6].X,
-; R600-NEXT:     LSHR T0.Y, KC0[3].W, 1,
-; R600-NEXT:     BIT_ALIGN_INT T1.Z, KC0[3].W, KC0[4].W, 1,
-; R600-NEXT:     BIT_ALIGN_INT * T0.W, T0.Z, T0.W, PV.W,
-; R600-NEXT:     NOT_INT * T1.W, KC0[5].W,
-; R600-NEXT:     LSHR T1.Y, KC0[3].Z, 1,
-; R600-NEXT:     BIT_ALIGN_INT T0.Z, T0.Y, T1.Z, PV.W,
-; R600-NEXT:     BIT_ALIGN_INT * T1.W, KC0[3].Z, KC0[4].Z, 1,
+; R600-NEXT:     AND_INT * T0.W, KC0[5].Z, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     AND_INT T0.X, KC0[3].Y, literal.x,
+; R600-NEXT:     AND_INT T0.Y, KC0[3].Z, literal.x,
+; R600-NEXT:     LSHL T0.Z, KC0[3].Y, literal.y,
+; R600-NEXT:     LSHL * T1.W, KC0[3].W, literal.y,
+; R600-NEXT:    -2(nan), 31(4.344025e-44)
 ; R600-NEXT:     NOT_INT * T2.W, KC0[5].Z,
-; R600-NEXT:     BIT_ALIGN_INT T0.Y, T1.Y, T1.W, PV.W,
-; R600-NEXT:     LSHR T1.Z, KC0[3].Y, 1,
-; R600-NEXT:     BIT_ALIGN_INT * T1.W, KC0[3].Y, KC0[4].Y, 1,
-; R600-NEXT:     NOT_INT * T2.W, KC0[5].Y,
-; R600-NEXT:     BIT_ALIGN_INT T0.X, T1.Z, T1.W, PV.W,
-; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT:     AND_INT T1.X, KC0[5].Y, literal.x,
+; R600-NEXT:     AND_INT T1.Y, PV.W, literal.x,
+; R600-NEXT:     LSHL T1.Z, KC0[4].X, literal.x,
+; R600-NEXT:     LSHR * T2.W, KC0[5].X, 1,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     NOT_INT * T3.W, KC0[6].X,
+; R600-NEXT:     LSHR T2.X, KC0[4].W, 1,
+; R600-NEXT:     AND_INT T2.Y, PV.W, literal.x,
+; R600-NEXT:     OR_INT T1.Z, T1.Z, T2.W,
+; R600-NEXT:     LSHL T2.W, KC0[3].Z, literal.x,
+; R600-NEXT:     LSHR * T3.W, KC0[4].Z, 1,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     OR_INT T3.X, PV.W, PS,
+; R600-NEXT:     LSHR T2.Y, PV.Z, PV.Y,
+; R600-NEXT:     NOT_INT T1.Z, KC0[5].W,
+; R600-NEXT:     AND_INT * T2.W, KC0[4].X, literal.x,
+; R600-NEXT:    -2(nan), 0(0.000000e+00)
+; R600-NEXT:     AND_INT * T3.W, KC0[6].X, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     LSHL T4.X, T2.W, PV.W,
+; R600-NEXT:     AND_INT T3.Y, KC0[3].W, literal.x,
+; R600-NEXT:     AND_INT T2.Z, KC0[5].W, literal.y,
+; R600-NEXT:     AND_INT T2.W, T1.Z, literal.y,
+; R600-NEXT:     OR_INT * T1.W, T1.W, T2.X,
+; R600-NEXT:    -2(nan), 31(4.344025e-44)
+; R600-NEXT:     LSHR T2.X, PS, PV.W,
+; R600-NEXT:     LSHL T3.Y, PV.Y, PV.Z,
+; R600-NEXT:     LSHR T1.Z, KC0[4].Y, 1,
+; R600-NEXT:     NOT_INT T1.W, KC0[5].Y,
+; R600-NEXT:     OR_INT * T2.W, PV.X, T2.Y,
+; R600-NEXT:     AND_INT T4.X, PV.W, literal.x,
+; R600-NEXT:     OR_INT T4.Y, T0.Z, PV.Z,
+; R600-NEXT:     OR_INT T2.Z, PV.Y, PV.X,
+; R600-NEXT:     LSHR T1.W, T3.X, T1.Y,
+; R600-NEXT:     LSHL * T0.W, T0.Y, T0.W,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     OR_INT T2.Y, PS, PV.W,
+; R600-NEXT:     LSHR T0.W, PV.Y, PV.X,
+; R600-NEXT:     LSHL * T1.W, T0.X, T1.X,
+; R600-NEXT:     OR_INT T2.X, PS, PV.W,
+; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_v4i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX10-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v0, s7, s11, 1
-; GFX10-NEXT:    v_alignbit_b32 v1, s6, s10, 1
-; GFX10-NEXT:    v_alignbit_b32 v5, s5, s9, 1
-; GFX10-NEXT:    v_alignbit_b32 v6, s4, s8, 1
-; GFX10-NEXT:    s_lshr_b32 s2, s7, 1
-; GFX10-NEXT:    s_not_b32 s3, s15
-; GFX10-NEXT:    s_lshr_b32 s6, s6, 1
-; GFX10-NEXT:    s_not_b32 s7, s14
-; GFX10-NEXT:    s_lshr_b32 s5, s5, 1
-; GFX10-NEXT:    s_not_b32 s9, s13
-; GFX10-NEXT:    s_lshr_b32 s4, s4, 1
-; GFX10-NEXT:    s_not_b32 s8, s12
-; GFX10-NEXT:    v_alignbit_b32 v3, s2, v0, s3
-; GFX10-NEXT:    v_alignbit_b32 v2, s6, v1, s7
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, v5, s9
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, v6, s8
+; GFX10-NEXT:    s_lshr_b32 s2, s11, 1
+; GFX10-NEXT:    s_lshl_b32 s3, s7, 31
+; GFX10-NEXT:    s_and_b32 s7, s7, -2
+; GFX10-NEXT:    s_lshr_b32 s10, s10, 1
+; GFX10-NEXT:    s_lshl_b32 s16, s6, 31
+; GFX10-NEXT:    s_not_b32 s11, s15
+; GFX10-NEXT:    s_not_b32 s17, s14
+; GFX10-NEXT:    s_and_b32 s6, s6, -2
+; GFX10-NEXT:    s_or_b32 s2, s3, s2
+; GFX10-NEXT:    s_lshl_b32 s3, s7, s15
+; GFX10-NEXT:    s_or_b32 s7, s16, s10
+; GFX10-NEXT:    s_lshr_b32 s9, s9, 1
+; GFX10-NEXT:    s_lshl_b32 s18, s5, 31
+; GFX10-NEXT:    s_lshr_b32 s8, s8, 1
+; GFX10-NEXT:    s_lshl_b32 s20, s4, 31
+; GFX10-NEXT:    s_lshl_b32 s6, s6, s14
+; GFX10-NEXT:    s_lshr_b32 s2, s2, s11
+; GFX10-NEXT:    s_lshr_b32 s7, s7, s17
+; GFX10-NEXT:    s_not_b32 s19, s13
+; GFX10-NEXT:    s_and_b32 s5, s5, -2
+; GFX10-NEXT:    s_or_b32 s9, s18, s9
+; GFX10-NEXT:    s_or_b32 s2, s3, s2
+; GFX10-NEXT:    s_or_b32 s3, s6, s7
+; GFX10-NEXT:    s_or_b32 s6, s20, s8
+; GFX10-NEXT:    s_not_b32 s7, s12
+; GFX10-NEXT:    s_and_b32 s4, s4, -2
+; GFX10-NEXT:    s_lshr_b32 s9, s9, s19
+; GFX10-NEXT:    s_lshr_b32 s6, s6, s7
+; GFX10-NEXT:    s_lshl_b32 s4, s4, s12
+; GFX10-NEXT:    s_lshl_b32 s5, s5, s13
+; GFX10-NEXT:    s_or_b32 s4, s4, s6
+; GFX10-NEXT:    s_or_b32 s5, s5, s9
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v1, s5
+; GFX10-NEXT:    v_mov_b32_e32 v2, s3
+; GFX10-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_v4i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
 ; GFX11-NEXT:    s_load_b256 s[4:11], s[0:1], 0x34
 ; GFX11-NEXT:    s_load_b128 s[12:15], s[0:1], 0x54
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v0, s7, s11, 1
-; GFX11-NEXT:    v_alignbit_b32 v1, s6, s10, 1
-; GFX11-NEXT:    v_alignbit_b32 v5, s5, s9, 1
-; GFX11-NEXT:    v_alignbit_b32 v6, s4, s8, 1
-; GFX11-NEXT:    s_lshr_b32 s2, s7, 1
-; GFX11-NEXT:    s_not_b32 s3, s15
-; GFX11-NEXT:    s_lshr_b32 s6, s6, 1
-; GFX11-NEXT:    s_not_b32 s7, s14
-; GFX11-NEXT:    s_lshr_b32 s5, s5, 1
-; GFX11-NEXT:    s_not_b32 s9, s13
-; GFX11-NEXT:    s_lshr_b32 s4, s4, 1
-; GFX11-NEXT:    s_not_b32 s8, s12
-; GFX11-NEXT:    v_alignbit_b32 v3, s2, v0, s3
-; GFX11-NEXT:    v_alignbit_b32 v2, s6, v1, s7
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, v5, s9
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, v6, s8
+; GFX11-NEXT:    s_lshr_b32 s2, s11, 1
+; GFX11-NEXT:    s_lshl_b32 s3, s7, 31
+; GFX11-NEXT:    s_and_b32 s7, s7, -2
+; GFX11-NEXT:    s_lshr_b32 s10, s10, 1
+; GFX11-NEXT:    s_lshl_b32 s16, s6, 31
+; GFX11-NEXT:    s_not_b32 s11, s15
+; GFX11-NEXT:    s_not_b32 s17, s14
+; GFX11-NEXT:    s_and_b32 s6, s6, -2
+; GFX11-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-NEXT:    s_lshl_b32 s3, s7, s15
+; GFX11-NEXT:    s_or_b32 s7, s16, s10
+; GFX11-NEXT:    s_lshr_b32 s9, s9, 1
+; GFX11-NEXT:    s_lshl_b32 s18, s5, 31
+; GFX11-NEXT:    s_lshr_b32 s8, s8, 1
+; GFX11-NEXT:    s_lshl_b32 s20, s4, 31
+; GFX11-NEXT:    s_lshl_b32 s6, s6, s14
+; GFX11-NEXT:    s_lshr_b32 s2, s2, s11
+; GFX11-NEXT:    s_lshr_b32 s7, s7, s17
+; GFX11-NEXT:    s_not_b32 s19, s13
+; GFX11-NEXT:    s_and_b32 s5, s5, -2
+; GFX11-NEXT:    s_or_b32 s9, s18, s9
+; GFX11-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-NEXT:    s_or_b32 s3, s6, s7
+; GFX11-NEXT:    s_or_b32 s6, s20, s8
+; GFX11-NEXT:    s_not_b32 s7, s12
+; GFX11-NEXT:    s_and_b32 s4, s4, -2
+; GFX11-NEXT:    s_lshr_b32 s9, s9, s19
+; GFX11-NEXT:    s_lshr_b32 s6, s6, s7
+; GFX11-NEXT:    s_lshl_b32 s4, s4, s12
+; GFX11-NEXT:    s_lshl_b32 s5, s5, s13
+; GFX11-NEXT:    s_or_b32 s4, s4, s6
+; GFX11-NEXT:    s_or_b32 s5, s5, s9
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
+; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT:    v_mov_b32_e32 v2, s3
 ; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
   store <4 x i32> %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
 ; SI-LABEL: fshl_v4i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_alignbit_b32 v3, s7, v0, 31
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    v_alignbit_b32 v2, s6, v1, 23
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 25
-; SI-NEXT:    v_mov_b32_e32 v0, s8
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, 31
+; SI-NEXT:    s_lshr_b32 s11, s11, 31
+; SI-NEXT:    s_lshl_b32 s7, s7, 1
+; SI-NEXT:    s_lshr_b32 s10, s10, 23
+; SI-NEXT:    s_lshl_b32 s6, s6, 9
+; SI-NEXT:    s_lshr_b32 s9, s9, 25
+; SI-NEXT:    s_lshl_b32 s5, s5, 7
+; SI-NEXT:    s_lshr_b32 s8, s8, 31
+; SI-NEXT:    s_lshl_b32 s4, s4, 1
+; SI-NEXT:    s_or_b32 s7, s7, s11
+; SI-NEXT:    s_or_b32 s6, s6, s10
+; SI-NEXT:    s_or_b32 s5, s5, s9
+; SI-NEXT:    s_or_b32 s4, s4, s8
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s5
+; SI-NEXT:    v_mov_b32_e32 v2, s6
+; SI-NEXT:    v_mov_b32_e32 v3, s7
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshl_v4i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    v_mov_b32_e32 v1, s10
-; VI-NEXT:    v_mov_b32_e32 v4, s9
-; VI-NEXT:    v_alignbit_b32 v3, s7, v0, 31
-; VI-NEXT:    v_alignbit_b32 v2, s6, v1, 23
-; VI-NEXT:    v_alignbit_b32 v1, s5, v4, 25
-; VI-NEXT:    v_mov_b32_e32 v0, s8
+; VI-NEXT:    s_lshr_b32 s2, s11, 31
+; VI-NEXT:    s_lshl_b32 s3, s7, 1
+; VI-NEXT:    s_lshr_b32 s7, s10, 23
+; VI-NEXT:    s_lshl_b32 s6, s6, 9
+; VI-NEXT:    s_or_b32 s2, s3, s2
+; VI-NEXT:    s_or_b32 s3, s6, s7
+; VI-NEXT:    s_lshr_b32 s6, s9, 25
+; VI-NEXT:    s_lshl_b32 s5, s5, 7
+; VI-NEXT:    s_or_b32 s5, s5, s6
+; VI-NEXT:    s_lshr_b32 s6, s8, 31
+; VI-NEXT:    s_lshl_b32 s4, s4, 1
+; VI-NEXT:    s_or_b32 s4, s4, s6
 ; VI-NEXT:    v_mov_b32_e32 v5, s1
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 31
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    v_mov_b32_e32 v2, s3
+; VI-NEXT:    v_mov_b32_e32 v3, s2
 ; VI-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshl_v4i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
-; GFX9-NEXT:    v_mov_b32_e32 v1, s10
-; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, 31
-; GFX9-NEXT:    v_mov_b32_e32 v0, s9
-; GFX9-NEXT:    v_alignbit_b32 v2, s6, v1, 23
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 25
-; GFX9-NEXT:    v_mov_b32_e32 v0, s8
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 31
+; GFX9-NEXT:    s_lshr_b32 s2, s11, 31
+; GFX9-NEXT:    s_lshl_b32 s3, s7, 1
+; GFX9-NEXT:    s_or_b32 s2, s3, s2
+; GFX9-NEXT:    s_lshl_b32 s3, s6, 9
+; GFX9-NEXT:    s_lshr_b32 s6, s9, 25
+; GFX9-NEXT:    s_lshl_b32 s5, s5, 7
+; GFX9-NEXT:    s_lshr_b32 s7, s10, 23
+; GFX9-NEXT:    s_or_b32 s5, s5, s6
+; GFX9-NEXT:    s_lshr_b32 s6, s8, 31
+; GFX9-NEXT:    s_lshl_b32 s4, s4, 1
+; GFX9-NEXT:    s_or_b32 s3, s3, s7
+; GFX9-NEXT:    s_or_b32 s4, s4, s6
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshl_v4i32_imm:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 17, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, literal.x,
+; R600-NEXT:     LSHL T0.W, KC0[4].X, 1,
+; R600-NEXT:     LSHR * T1.W, KC0[5].X, literal.x,
 ; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,
-; R600-NEXT:    23(3.222986e-44), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,
-; R600-NEXT:    25(3.503246e-44), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, literal.x,
+; R600-NEXT:     LSHL T0.Z, KC0[3].W, literal.x,
+; R600-NEXT:     LSHR T2.W, KC0[4].W, literal.y,
+; R600-NEXT:     OR_INT * T0.W, PV.W, PS,
+; R600-NEXT:    9(1.261169e-44), 23(3.222986e-44)
+; R600-NEXT:     OR_INT T0.Z, PV.Z, PV.W,
+; R600-NEXT:     LSHL T1.W, KC0[3].Z, literal.x,
+; R600-NEXT:     LSHR * T2.W, KC0[4].Z, literal.y,
+; R600-NEXT:    7(9.809089e-45), 25(3.503246e-44)
+; R600-NEXT:     OR_INT T0.Y, PV.W, PS,
+; R600-NEXT:     LSHL T1.W, KC0[3].Y, 1,
+; R600-NEXT:     LSHR * T2.W, KC0[4].Y, literal.x,
 ; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     OR_INT T0.X, PV.W, PS,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshl_v4i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v3, s7, s11, 31
-; GFX10-NEXT:    v_alignbit_b32 v2, s6, s10, 23
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s9, 25
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s8, 31
-; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX10-NEXT:    s_lshr_b32 s2, s11, 31
+; GFX10-NEXT:    s_lshl_b32 s3, s7, 1
+; GFX10-NEXT:    s_lshr_b32 s7, s10, 23
+; GFX10-NEXT:    s_lshl_b32 s6, s6, 9
+; GFX10-NEXT:    s_lshr_b32 s9, s9, 25
+; GFX10-NEXT:    s_lshl_b32 s5, s5, 7
+; GFX10-NEXT:    s_lshr_b32 s8, s8, 31
+; GFX10-NEXT:    s_lshl_b32 s4, s4, 1
+; GFX10-NEXT:    s_or_b32 s2, s3, s2
+; GFX10-NEXT:    s_or_b32 s3, s6, s7
+; GFX10-NEXT:    s_or_b32 s4, s4, s8
+; GFX10-NEXT:    s_or_b32 s5, s5, s9
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v1, s5
+; GFX10-NEXT:    v_mov_b32_e32 v2, s3
+; GFX10-NEXT:    v_mov_b32_e32 v3, s2
+; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshl_v4i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b256 s[4:11], s[0:1], 0x34
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v3, s7, s11, 31
-; GFX11-NEXT:    v_alignbit_b32 v2, s6, s10, 23
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s9, 25
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s8, 31
+; GFX11-NEXT:    s_lshr_b32 s2, s11, 31
+; GFX11-NEXT:    s_lshl_b32 s3, s7, 1
+; GFX11-NEXT:    s_lshr_b32 s7, s10, 23
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 9
+; GFX11-NEXT:    s_lshr_b32 s9, s9, 25
+; GFX11-NEXT:    s_lshl_b32 s5, s5, 7
+; GFX11-NEXT:    s_lshr_b32 s8, s8, 31
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 1
+; GFX11-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-NEXT:    s_or_b32 s3, s6, s7
+; GFX11-NEXT:    s_or_b32 s4, s4, s8
+; GFX11-NEXT:    s_or_b32 s5, s5, s9
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
+; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT:    v_mov_b32_e32 v2, s3
 ; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
   store <4 x i32> %0, ptr addrspace(1) %in
   ret void
 }

llvm/test/CodeGen/AMDGPU/fshr.ll

 define amdgpu_kernel void @fshr_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z) {
 ; SI-LABEL: fshr_i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; SI-NEXT:    s_load_dword s8, s[0:1], 0xd
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_mov_b32_e32 v1, s8
-; SI-NEXT:    s_mov_b32 s0, s4
 ; SI-NEXT:    s_mov_b32 s1, s5
-; SI-NEXT:    v_alignbit_b32 v0, s6, v0, v1
+; SI-NEXT:    s_lshl_b32 s5, s6, 1
+; SI-NEXT:    s_not_b32 s6, s8
+; SI-NEXT:    s_mov_b32 s0, s4
+; SI-NEXT:    s_lshr_b32 s4, s7, s8
+; SI-NEXT:    s_lshl_b32 s5, s5, s6
+; SI-NEXT:    s_or_b32 s4, s5, s4
+; SI-NEXT:    v_mov_b32_e32 v0, s4
 ; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; VI-NEXT:    s_load_dword s0, s[0:1], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    v_mov_b32_e32 v1, s0
-; VI-NEXT:    v_alignbit_b32 v2, s6, v0, v1
+; VI-NEXT:    s_lshl_b32 s2, s6, 1
+; VI-NEXT:    s_lshr_b32 s1, s7, s0
+; VI-NEXT:    s_not_b32 s0, s0
+; VI-NEXT:    s_lshl_b32 s0, s2, s0
+; VI-NEXT:    s_or_b32 s0, s0, s1
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s7
-; GFX9-NEXT:    v_mov_b32_e32 v2, s2
-; GFX9-NEXT:    v_alignbit_b32 v1, s6, v1, v2
+; GFX9-NEXT:    s_lshl_b32 s1, s6, 1
+; GFX9-NEXT:    s_lshr_b32 s0, s7, s2
+; GFX9-NEXT:    s_not_b32 s2, s2
+; GFX9-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 2, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
+; R600-NEXT:     NOT_INT * T0.W, KC0[3].X,
+; R600-NEXT:     AND_INT T0.Z, KC0[3].X, literal.x,
+; R600-NEXT:     AND_INT T0.W, PV.W, literal.x,
+; R600-NEXT:     LSHL * T1.W, KC0[2].Z, 1,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     LSHL T0.W, PS, PV.W,
+; R600-NEXT:     LSHR * T1.W, KC0[2].W, PV.Z,
+; R600-NEXT:     OR_INT T0.X, PV.W, PS,
+; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X,
 ;
 ; GFX10-LABEL: fshr_i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX10-NEXT:    v_mov_b32_e32 v1, 0
+; GFX10-NEXT:    s_load_dword s2, s[0:1], 0x34
+; GFX10-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, s2
-; GFX10-NEXT:    v_alignbit_b32 v0, s6, s7, v0
-; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]
+; GFX10-NEXT:    s_lshl_b32 s0, s6, 1
+; GFX10-NEXT:    s_not_b32 s1, s2
+; GFX10-NEXT:    s_lshr_b32 s2, s7, s2
+; GFX10-NEXT:    s_lshl_b32 s0, s0, s1
+; GFX10-NEXT:    s_or_b32 s0, s0, s2
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
+; GFX10-NEXT:    global_store_dword v0, v1, s[4:5]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b32 s4, s[0:1], 0x34
-; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x24
+; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x34
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT:    v_alignbit_b32 v0, s2, s3, v0
-; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT:    s_lshl_b32 s1, s6, 1
+; GFX11-NEXT:    s_not_b32 s2, s0
+; GFX11-NEXT:    s_lshr_b32 s0, s7, s0
+; GFX11-NEXT:    s_lshl_b32 s1, s1, s2
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_or_b32 s0, s1, s0
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT:    global_store_b32 v0, v1, s[4:5]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
   store i32 %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
 ; SI-LABEL: fshr_i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s3
 ; SI-NEXT:    s_mov_b32 s4, s0
 ; SI-NEXT:    s_mov_b32 s5, s1
-; SI-NEXT:    v_alignbit_b32 v0, s2, v0, 7
+; SI-NEXT:    s_lshr_b32 s0, s3, 7
+; SI-NEXT:    s_lshl_b32 s1, s2, 25
+; SI-NEXT:    s_or_b32 s0, s1, s0
+; SI-NEXT:    v_mov_b32_e32 v0, s0
 ; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    v_alignbit_b32 v2, s2, v0, 7
+; VI-NEXT:    s_lshr_b32 s3, s3, 7
+; VI-NEXT:    s_lshl_b32 s2, s2, 25
+; VI-NEXT:    s_or_b32 s2, s2, s3
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    v_mov_b32_e32 v2, s2
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_alignbit_b32 v1, s2, v1, 7
+; GFX9-NEXT:    s_lshr_b32 s3, s3, 7
+; GFX9-NEXT:    s_lshl_b32 s2, s2, 25
+; GFX9-NEXT:    s_or_b32 s2, s2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_i32_imm:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
+; R600-NEXT:     LSHL T0.W, KC0[2].Z, literal.x,
+; R600-NEXT:     LSHR * T1.W, KC0[2].W, literal.y,
+; R600-NEXT:    25(3.503246e-44), 7(9.809089e-45)
+; R600-NEXT:     OR_INT T0.X, PV.W, PS,
+; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,
-; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v1, s2, s3, 7
+; GFX10-NEXT:    s_lshr_b32 s3, s3, 7
+; GFX10-NEXT:    s_lshl_b32 s2, s2, 25
+; GFX10-NEXT:    s_or_b32 s2, s2, s3
+; GFX10-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, s2, s3, 7
+; GFX11-NEXT:    s_lshr_b32 s3, s3, 7
+; GFX11-NEXT:    s_lshl_b32 s2, s2, 25
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_or_b32 s2, s2, s3
+; GFX11-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
 ; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 7)
   store i32 %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
 ; SI-LABEL: fshr_v2i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xf
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_mov_b32_e32 v1, s9
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s6
-; SI-NEXT:    v_mov_b32_e32 v2, s8
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, v2
+; SI-NEXT:    s_lshl_b32 s5, s5, 1
+; SI-NEXT:    s_lshr_b32 s7, s7, s9
+; SI-NEXT:    s_not_b32 s9, s9
+; SI-NEXT:    s_lshl_b32 s5, s5, s9
+; SI-NEXT:    s_or_b32 s5, s5, s7
+; SI-NEXT:    s_lshl_b32 s4, s4, 1
+; SI-NEXT:    s_not_b32 s7, s8
+; SI-NEXT:    s_lshr_b32 s6, s6, s8
+; SI-NEXT:    s_lshl_b32 s4, s4, s7
+; SI-NEXT:    s_or_b32 s4, s4, s6
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s5
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_v2i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_mov_b32_e32 v2, s6
-; VI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s2
-; VI-NEXT:    v_alignbit_b32 v0, s4, v2, v0
+; VI-NEXT:    s_lshl_b32 s5, s5, 1
+; VI-NEXT:    s_lshr_b32 s7, s7, s3
+; VI-NEXT:    s_not_b32 s3, s3
+; VI-NEXT:    s_lshl_b32 s3, s5, s3
+; VI-NEXT:    s_lshr_b32 s5, s6, s2
+; VI-NEXT:    s_lshl_b32 s4, s4, 1
+; VI-NEXT:    s_not_b32 s2, s2
+; VI-NEXT:    s_lshl_b32 s2, s4, s2
+; VI-NEXT:    s_or_b32 s3, s3, s7
+; VI-NEXT:    s_or_b32 s2, s2, s5
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_v2i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s6
-; GFX9-NEXT:    v_mov_b32_e32 v3, s2
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v3
+; GFX9-NEXT:    s_lshl_b32 s1, s5, 1
+; GFX9-NEXT:    s_lshr_b32 s0, s7, s3
+; GFX9-NEXT:    s_not_b32 s3, s3
+; GFX9-NEXT:    s_lshl_b32 s1, s1, s3
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    s_lshr_b32 s1, s6, s2
+; GFX9-NEXT:    s_lshl_b32 s3, s4, 1
+; GFX9-NEXT:    s_not_b32 s2, s2
+; GFX9-NEXT:    s_lshl_b32 s2, s3, s2
+; GFX9-NEXT:    s_or_b32 s1, s2, s1
+; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_v2i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 17, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     MOV * T0.W, KC0[4].X,
-; R600-NEXT:     BIT_ALIGN_INT T0.Y, KC0[3].X, KC0[3].Z, PV.W,
-; R600-NEXT:     MOV * T0.W, KC0[3].W,
-; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, PV.W,
+; R600-NEXT:     NOT_INT * T0.W, KC0[4].X,
+; R600-NEXT:     AND_INT T0.Y, KC0[4].X, literal.x,
+; R600-NEXT:     AND_INT T0.Z, PV.W, literal.x,
+; R600-NEXT:     LSHL * T0.W, KC0[3].X, 1,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     NOT_INT * T1.W, KC0[3].W,
+; R600-NEXT:     AND_INT T0.X, KC0[3].W, literal.x,
+; R600-NEXT:     AND_INT T1.Y, PV.W, literal.x,
+; R600-NEXT:     LSHL T1.Z, KC0[2].W, 1,
+; R600-NEXT:     LSHL T0.W, T0.W, T0.Z,
+; R600-NEXT:     LSHR * T1.W, KC0[3].Z, T0.Y,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     OR_INT T0.Y, PV.W, PS,
+; R600-NEXT:     LSHL T0.W, PV.Z, PV.Y,
+; R600-NEXT:     LSHR * T1.W, KC0[3].Y, PV.X,
+; R600-NEXT:     OR_INT T0.X, PV.W, PS,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_v2i32:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x2
-; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x3c
 ; GFX10-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
-; GFX10-NEXT:    v_mov_b32_e32 v3, 0
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, s3
-; GFX10-NEXT:    v_mov_b32_e32 v2, s2
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s7, v0
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s6, v2
-; GFX10-NEXT:    global_store_dwordx2 v3, v[0:1], s[8:9]
+; GFX10-NEXT:    s_lshl_b32 s1, s5, 1
+; GFX10-NEXT:    s_lshr_b32 s0, s7, s3
+; GFX10-NEXT:    s_not_b32 s3, s3
+; GFX10-NEXT:    s_lshl_b32 s4, s4, 1
+; GFX10-NEXT:    s_not_b32 s5, s2
+; GFX10-NEXT:    s_lshr_b32 s2, s6, s2
+; GFX10-NEXT:    s_lshl_b32 s4, s4, s5
+; GFX10-NEXT:    s_lshl_b32 s1, s1, s3
+; GFX10-NEXT:    s_or_b32 s2, s4, s2
+; GFX10-NEXT:    s_or_b32 s0, s1, s0
+; GFX10-NEXT:    v_mov_b32_e32 v0, s2
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
+; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_v2i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x3c
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
+; GFX11-NEXT:    s_load_b64 s[2:3], s[0:1], 0x3c
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s3
-; GFX11-NEXT:    v_mov_b32_e32 v2, s2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s7, v0
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s6, v2
-; GFX11-NEXT:    global_store_b64 v3, v[0:1], s[0:1]
+; GFX11-NEXT:    s_lshl_b32 s5, s5, 1
+; GFX11-NEXT:    s_lshr_b32 s7, s7, s3
+; GFX11-NEXT:    s_not_b32 s3, s3
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 1
+; GFX11-NEXT:    s_not_b32 s8, s2
+; GFX11-NEXT:    s_lshr_b32 s2, s6, s2
+; GFX11-NEXT:    s_lshl_b32 s4, s4, s8
+; GFX11-NEXT:    s_lshl_b32 s3, s5, s3
+; GFX11-NEXT:    s_or_b32 s2, s4, s2
+; GFX11-NEXT:    s_or_b32 s3, s3, s7
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
   store <2 x i32> %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
 ; SI-LABEL: fshr_v2i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s7
-; SI-NEXT:    v_mov_b32_e32 v2, s6
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 9
-; SI-NEXT:    v_alignbit_b32 v0, s4, v2, 7
+; SI-NEXT:    s_lshr_b32 s7, s7, 9
+; SI-NEXT:    s_lshl_b32 s5, s5, 23
+; SI-NEXT:    s_lshr_b32 s6, s6, 7
+; SI-NEXT:    s_lshl_b32 s4, s4, 25
+; SI-NEXT:    s_or_b32 s5, s5, s7
+; SI-NEXT:    s_or_b32 s4, s4, s6
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s5
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_v2i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s7
-; VI-NEXT:    v_mov_b32_e32 v2, s6
-; VI-NEXT:    v_alignbit_b32 v1, s5, v0, 9
-; VI-NEXT:    v_alignbit_b32 v0, s4, v2, 7
+; VI-NEXT:    s_lshr_b32 s2, s7, 9
+; VI-NEXT:    s_lshl_b32 s3, s5, 23
+; VI-NEXT:    s_lshr_b32 s5, s6, 7
+; VI-NEXT:    s_lshl_b32 s4, s4, 25
+; VI-NEXT:    s_or_b32 s2, s3, s2
+; VI-NEXT:    s_or_b32 s3, s4, s5
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s3
+; VI-NEXT:    v_mov_b32_e32 v1, s2
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_v2i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s7
-; GFX9-NEXT:    v_mov_b32_e32 v3, s6
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 9
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v3, 7
+; GFX9-NEXT:    s_lshr_b32 s0, s7, 9
+; GFX9-NEXT:    s_lshl_b32 s1, s5, 23
+; GFX9-NEXT:    s_lshr_b32 s5, s6, 7
+; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    s_lshl_b32 s1, s4, 25
+; GFX9-NEXT:    s_or_b32 s1, s1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_v2i32_imm:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 5, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
-; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
-; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)
+; R600-NEXT:     LSHL T0.W, KC0[3].X, literal.x,
+; R600-NEXT:     LSHR * T1.W, KC0[3].Z, literal.y,
+; R600-NEXT:    23(3.222986e-44), 9(1.261169e-44)
+; R600-NEXT:     OR_INT T0.Y, PV.W, PS,
+; R600-NEXT:     LSHL T0.W, KC0[2].W, literal.x,
+; R600-NEXT:     LSHR * T1.W, KC0[3].Y, literal.y,
+; R600-NEXT:    25(3.503246e-44), 7(9.809089e-45)
+; R600-NEXT:     OR_INT T0.X, PV.W, PS,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_v2i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s7, 9
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s6, 7
+; GFX10-NEXT:    s_lshr_b32 s0, s7, 9
+; GFX10-NEXT:    s_lshr_b32 s1, s6, 7
+; GFX10-NEXT:    s_lshl_b32 s4, s4, 25
+; GFX10-NEXT:    s_lshl_b32 s5, s5, 23
+; GFX10-NEXT:    s_or_b32 s1, s4, s1
+; GFX10-NEXT:    s_or_b32 s0, s5, s0
+; GFX10-NEXT:    v_mov_b32_e32 v0, s1
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_v2i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x2c
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s7, 9
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s6, 7
+; GFX11-NEXT:    s_lshr_b32 s2, s7, 9
+; GFX11-NEXT:    s_lshr_b32 s3, s6, 7
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 25
+; GFX11-NEXT:    s_lshl_b32 s5, s5, 23
+; GFX11-NEXT:    s_or_b32 s3, s4, s3
+; GFX11-NEXT:    s_or_b32 s2, s5, s2
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT:    v_mov_b32_e32 v0, s3
 ; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
   store <2 x i32> %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
 ; SI-LABEL: fshr_v4i32:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
 ; SI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x15
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    v_mov_b32_e32 v1, s15
-; SI-NEXT:    v_alignbit_b32 v3, s7, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s10
-; SI-NEXT:    v_mov_b32_e32 v1, s14
-; SI-NEXT:    v_alignbit_b32 v2, s6, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    v_mov_b32_e32 v1, s13
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; SI-NEXT:    v_mov_b32_e32 v0, s8
-; SI-NEXT:    v_mov_b32_e32 v4, s12
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
+; SI-NEXT:    s_lshl_b32 s7, s7, 1
+; SI-NEXT:    s_lshr_b32 s11, s11, s15
+; SI-NEXT:    s_not_b32 s15, s15
+; SI-NEXT:    s_lshl_b32 s7, s7, s15
+; SI-NEXT:    s_or_b32 s7, s7, s11
+; SI-NEXT:    s_lshl_b32 s6, s6, 1
+; SI-NEXT:    s_not_b32 s11, s14
+; SI-NEXT:    s_lshr_b32 s10, s10, s14
+; SI-NEXT:    s_lshl_b32 s6, s6, s11
+; SI-NEXT:    s_or_b32 s6, s6, s10
+; SI-NEXT:    s_lshl_b32 s5, s5, 1
+; SI-NEXT:    s_not_b32 s10, s13
+; SI-NEXT:    s_lshr_b32 s9, s9, s13
+; SI-NEXT:    s_lshl_b32 s5, s5, s10
+; SI-NEXT:    s_or_b32 s5, s5, s9
+; SI-NEXT:    s_lshl_b32 s4, s4, 1
+; SI-NEXT:    s_not_b32 s9, s12
+; SI-NEXT:    s_lshr_b32 s8, s8, s12
+; SI-NEXT:    s_lshl_b32 s4, s4, s9
+; SI-NEXT:    s_or_b32 s4, s4, s8
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s5
+; SI-NEXT:    v_mov_b32_e32 v2, s6
+; SI-NEXT:    v_mov_b32_e32 v3, s7
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_v4i32:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    v_mov_b32_e32 v1, s15
-; VI-NEXT:    v_mov_b32_e32 v2, s10
-; VI-NEXT:    v_alignbit_b32 v3, s7, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s14
-; VI-NEXT:    v_alignbit_b32 v2, s6, v2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s9
-; VI-NEXT:    v_mov_b32_e32 v1, s13
-; VI-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v0, s8
-; VI-NEXT:    v_mov_b32_e32 v4, s12
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, v4
+; VI-NEXT:    s_lshl_b32 s3, s7, 1
+; VI-NEXT:    s_not_b32 s7, s15
+; VI-NEXT:    s_lshr_b32 s2, s11, s15
+; VI-NEXT:    s_lshl_b32 s3, s3, s7
+; VI-NEXT:    s_lshl_b32 s6, s6, 1
+; VI-NEXT:    s_not_b32 s7, s14
+; VI-NEXT:    s_or_b32 s2, s3, s2
+; VI-NEXT:    s_lshr_b32 s3, s10, s14
+; VI-NEXT:    s_lshl_b32 s6, s6, s7
+; VI-NEXT:    s_lshl_b32 s5, s5, 1
+; VI-NEXT:    s_not_b32 s7, s13
+; VI-NEXT:    s_or_b32 s3, s6, s3
+; VI-NEXT:    s_lshr_b32 s6, s9, s13
+; VI-NEXT:    s_lshl_b32 s5, s5, s7
+; VI-NEXT:    s_lshl_b32 s4, s4, 1
+; VI-NEXT:    s_not_b32 s7, s12
+; VI-NEXT:    s_or_b32 s5, s5, s6
+; VI-NEXT:    s_lshr_b32 s6, s8, s12
+; VI-NEXT:    s_lshl_b32 s4, s4, s7
+; VI-NEXT:    s_or_b32 s4, s4, s6
 ; VI-NEXT:    v_mov_b32_e32 v5, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    v_mov_b32_e32 v2, s3
+; VI-NEXT:    v_mov_b32_e32 v3, s2
 ; VI-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_v4i32:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX9-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
-; GFX9-NEXT:    v_mov_b32_e32 v1, s15
-; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s10
-; GFX9-NEXT:    v_mov_b32_e32 v1, s14
-; GFX9-NEXT:    v_alignbit_b32 v2, s6, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s9
-; GFX9-NEXT:    v_mov_b32_e32 v1, s13
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s8
-; GFX9-NEXT:    v_mov_b32_e32 v5, s12
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, v5
+; GFX9-NEXT:    s_lshl_b32 s3, s7, 1
+; GFX9-NEXT:    s_not_b32 s7, s15
+; GFX9-NEXT:    s_lshr_b32 s2, s11, s15
+; GFX9-NEXT:    s_lshl_b32 s3, s3, s7
+; GFX9-NEXT:    s_lshl_b32 s6, s6, 1
+; GFX9-NEXT:    s_not_b32 s7, s14
+; GFX9-NEXT:    s_or_b32 s2, s3, s2
+; GFX9-NEXT:    s_lshr_b32 s3, s10, s14
+; GFX9-NEXT:    s_lshl_b32 s6, s6, s7
+; GFX9-NEXT:    s_lshl_b32 s5, s5, 1
+; GFX9-NEXT:    s_not_b32 s7, s13
+; GFX9-NEXT:    s_or_b32 s3, s6, s3
+; GFX9-NEXT:    s_lshr_b32 s6, s9, s13
+; GFX9-NEXT:    s_lshl_b32 s5, s5, s7
+; GFX9-NEXT:    s_lshl_b32 s4, s4, 1
+; GFX9-NEXT:    s_not_b32 s7, s12
+; GFX9-NEXT:    s_or_b32 s5, s5, s6
+; GFX9-NEXT:    s_lshr_b32 s6, s8, s12
+; GFX9-NEXT:    s_lshl_b32 s4, s4, s7
+; GFX9-NEXT:    s_or_b32 s4, s4, s6
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_v4i32:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 9, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; R600-NEXT:    ALU 35, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     MOV * T0.W, KC0[6].X,
-; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, PV.W,
-; R600-NEXT:     MOV * T1.W, KC0[5].W,
-; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, PV.W,
-; R600-NEXT:     MOV * T1.W, KC0[5].Z,
-; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, PV.W,
-; R600-NEXT:     MOV * T1.W, KC0[5].Y,
-; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, PV.W,
-; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
+; R600-NEXT:     AND_INT * T0.W, KC0[5].Y, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     LSHL T0.Z, KC0[3].Z, 1,
+; R600-NEXT:     NOT_INT T1.W, KC0[6].X,
+; R600-NEXT:     AND_INT * T2.W, KC0[6].X, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     AND_INT T0.X, KC0[5].Z, literal.x,
+; R600-NEXT:     LSHR T0.Y, KC0[5].X, PS,
+; R600-NEXT:     NOT_INT T1.Z, KC0[5].W,
+; R600-NEXT:     AND_INT * T1.W, PV.W, literal.x,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     LSHL * T2.W, KC0[4].X, 1,
+; R600-NEXT:     LSHL T1.X, PV.W, T1.W,
+; R600-NEXT:     AND_INT T1.Y, KC0[5].W, literal.x,
+; R600-NEXT:     AND_INT T1.Z, T1.Z, literal.x,
+; R600-NEXT:     LSHL T1.W, KC0[3].W, 1,
+; R600-NEXT:     NOT_INT * T2.W, KC0[5].Z,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     AND_INT T2.X, PS, literal.x,
+; R600-NEXT:     LSHL T2.Y, PV.W, PV.Z,
+; R600-NEXT:     LSHR T1.Z, KC0[4].W, PV.Y,
+; R600-NEXT:     NOT_INT T1.W, KC0[5].Y,
+; R600-NEXT:     OR_INT * T2.W, PV.X, T0.Y,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     AND_INT T1.X, PV.W, literal.x,
+; R600-NEXT:     LSHL T0.Y, KC0[3].Y, 1,
+; R600-NEXT:     OR_INT T2.Z, PV.Y, PV.Z,
+; R600-NEXT:     LSHL T1.W, T0.Z, PV.X,
+; R600-NEXT:     LSHR * T3.W, KC0[4].Z, T0.X,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     OR_INT T2.Y, PV.W, PS,
+; R600-NEXT:     LSHL T1.W, PV.Y, PV.X,
+; R600-NEXT:     LSHR * T0.W, KC0[4].Y, T0.W,
+; R600-NEXT:     OR_INT T2.X, PV.W, PS,
+; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_v4i32:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:    s_clause 0x2
-; GFX10-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
+; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX10-NEXT:    v_mov_b32_e32 v6, 0
+; GFX10-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x54
+; GFX10-NEXT:    v_mov_b32_e32 v4, 0
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_mov_b32_e32 v0, s15
-; GFX10-NEXT:    v_mov_b32_e32 v1, s14
-; GFX10-NEXT:    v_mov_b32_e32 v4, s13
-; GFX10-NEXT:    v_mov_b32_e32 v5, s12
-; GFX10-NEXT:    v_alignbit_b32 v3, s7, s11, v0
-; GFX10-NEXT:    v_alignbit_b32 v2, s6, s10, v1
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s9, v4
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s8, v5
-; GFX10-NEXT:    global_store_dwordx4 v6, v[0:3], s[2:3]
+; GFX10-NEXT:    s_lshl_b32 s3, s7, 1
+; GFX10-NEXT:    s_lshr_b32 s2, s11, s15
+; GFX10-NEXT:    s_not_b32 s7, s15
+; GFX10-NEXT:    s_lshl_b32 s6, s6, 1
+; GFX10-NEXT:    s_not_b32 s11, s14
+; GFX10-NEXT:    s_lshr_b32 s9, s9, s13
+; GFX10-NEXT:    s_lshl_b32 s5, s5, 1
+; GFX10-NEXT:    s_not_b32 s13, s13
+; GFX10-NEXT:    s_lshr_b32 s8, s8, s12
+; GFX10-NEXT:    s_lshl_b32 s4, s4, 1
+; GFX10-NEXT:    s_not_b32 s12, s12
+; GFX10-NEXT:    s_lshr_b32 s10, s10, s14
+; GFX10-NEXT:    s_lshl_b32 s3, s3, s7
+; GFX10-NEXT:    s_lshl_b32 s6, s6, s11
+; GFX10-NEXT:    s_lshl_b32 s5, s5, s13
+; GFX10-NEXT:    s_lshl_b32 s4, s4, s12
+; GFX10-NEXT:    s_or_b32 s2, s3, s2
+; GFX10-NEXT:    s_or_b32 s3, s6, s10
+; GFX10-NEXT:    s_or_b32 s4, s4, s8
+; GFX10-NEXT:    s_or_b32 s5, s5, s9
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v1, s5
+; GFX10-NEXT:    v_mov_b32_e32 v2, s3
+; GFX10-NEXT:    v_mov_b32_e32 v3, s2
+; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_v4i32:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x2
-; GFX11-NEXT:    s_load_b128 s[12:15], s[0:1], 0x54
 ; GFX11-NEXT:    s_load_b256 s[4:11], s[0:1], 0x34
+; GFX11-NEXT:    s_load_b128 s[12:15], s[0:1], 0x54
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_dual_mov_b32 v0, s15 :: v_dual_mov_b32 v1, s14
-; GFX11-NEXT:    v_dual_mov_b32 v4, s13 :: v_dual_mov_b32 v5, s12
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT:    v_alignbit_b32 v3, s7, s11, v0
-; GFX11-NEXT:    v_alignbit_b32 v2, s6, s10, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s9, v4
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s8, v5
-; GFX11-NEXT:    global_store_b128 v6, v[0:3], s[0:1]
+; GFX11-NEXT:    s_lshl_b32 s3, s7, 1
+; GFX11-NEXT:    s_lshr_b32 s2, s11, s15
+; GFX11-NEXT:    s_not_b32 s7, s15
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 1
+; GFX11-NEXT:    s_not_b32 s11, s14
+; GFX11-NEXT:    s_lshr_b32 s9, s9, s13
+; GFX11-NEXT:    s_lshl_b32 s5, s5, 1
+; GFX11-NEXT:    s_not_b32 s13, s13
+; GFX11-NEXT:    s_lshr_b32 s8, s8, s12
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 1
+; GFX11-NEXT:    s_not_b32 s12, s12
+; GFX11-NEXT:    s_lshr_b32 s10, s10, s14
+; GFX11-NEXT:    s_lshl_b32 s3, s3, s7
+; GFX11-NEXT:    s_lshl_b32 s6, s6, s11
+; GFX11-NEXT:    s_lshl_b32 s5, s5, s13
+; GFX11-NEXT:    s_lshl_b32 s4, s4, s12
+; GFX11-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-NEXT:    s_or_b32 s3, s6, s10
+; GFX11-NEXT:    s_or_b32 s4, s4, s8
+; GFX11-NEXT:    s_or_b32 s5, s5, s9
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
+; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT:    v_mov_b32_e32 v2, s3
+; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
   store <4 x i32> %0, ptr addrspace(1) %in
   ret void
 }
 
 define amdgpu_kernel void @fshr_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
 ; SI-LABEL: fshr_v4i32_imm:
 ; SI:       ; %bb.0: ; %entry
 ; SI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
 ; SI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-NEXT:    s_mov_b32 s2, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    v_mov_b32_e32 v0, s11
-; SI-NEXT:    v_mov_b32_e32 v1, s10
-; SI-NEXT:    v_alignbit_b32 v3, s7, v0, 1
-; SI-NEXT:    v_mov_b32_e32 v0, s9
-; SI-NEXT:    v_alignbit_b32 v2, s6, v1, 9
-; SI-NEXT:    v_alignbit_b32 v1, s5, v0, 7
-; SI-NEXT:    v_mov_b32_e32 v0, s8
-; SI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
+; SI-NEXT:    s_lshr_b32 s11, s11, 1
+; SI-NEXT:    s_lshl_b32 s7, s7, 31
+; SI-NEXT:    s_lshr_b32 s10, s10, 9
+; SI-NEXT:    s_lshl_b32 s6, s6, 23
+; SI-NEXT:    s_lshr_b32 s9, s9, 7
+; SI-NEXT:    s_lshl_b32 s5, s5, 25
+; SI-NEXT:    s_lshr_b32 s8, s8, 1
+; SI-NEXT:    s_lshl_b32 s4, s4, 31
+; SI-NEXT:    s_or_b32 s7, s7, s11
+; SI-NEXT:    s_or_b32 s6, s6, s10
+; SI-NEXT:    s_or_b32 s5, s5, s9
+; SI-NEXT:    s_or_b32 s4, s4, s8
+; SI-NEXT:    v_mov_b32_e32 v0, s4
+; SI-NEXT:    v_mov_b32_e32 v1, s5
+; SI-NEXT:    v_mov_b32_e32 v2, s6
+; SI-NEXT:    v_mov_b32_e32 v3, s7
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: fshr_v4i32_imm:
 ; VI:       ; %bb.0: ; %entry
 ; VI-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s11
-; VI-NEXT:    v_mov_b32_e32 v1, s10
-; VI-NEXT:    v_mov_b32_e32 v4, s9
-; VI-NEXT:    v_alignbit_b32 v3, s7, v0, 1
-; VI-NEXT:    v_alignbit_b32 v2, s6, v1, 9
-; VI-NEXT:    v_alignbit_b32 v1, s5, v4, 7
-; VI-NEXT:    v_mov_b32_e32 v0, s8
+; VI-NEXT:    s_lshr_b32 s2, s11, 1
+; VI-NEXT:    s_lshl_b32 s3, s7, 31
+; VI-NEXT:    s_lshr_b32 s7, s10, 9
+; VI-NEXT:    s_lshl_b32 s6, s6, 23
+; VI-NEXT:    s_or_b32 s2, s3, s2
+; VI-NEXT:    s_or_b32 s3, s6, s7
+; VI-NEXT:    s_lshr_b32 s6, s9, 7
+; VI-NEXT:    s_lshl_b32 s5, s5, 25
+; VI-NEXT:    s_or_b32 s5, s5, s6
+; VI-NEXT:    s_lshr_b32 s6, s8, 1
+; VI-NEXT:    s_lshl_b32 s4, s4, 31
+; VI-NEXT:    s_or_b32 s4, s4, s6
 ; VI-NEXT:    v_mov_b32_e32 v5, s1
-; VI-NEXT:    v_alignbit_b32 v0, s4, v0, 1
+; VI-NEXT:    v_mov_b32_e32 v0, s4
+; VI-NEXT:    v_mov_b32_e32 v1, s5
+; VI-NEXT:    v_mov_b32_e32 v2, s3
+; VI-NEXT:    v_mov_b32_e32 v3, s2
 ; VI-NEXT:    v_mov_b32_e32 v4, s0
 ; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: fshr_v4i32_imm:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    v_mov_b32_e32 v0, s11
-; GFX9-NEXT:    v_mov_b32_e32 v1, s10
-; GFX9-NEXT:    v_alignbit_b32 v3, s7, v0, 1
-; GFX9-NEXT:    v_mov_b32_e32 v0, s9
-; GFX9-NEXT:    v_alignbit_b32 v2, s6, v1, 9
-; GFX9-NEXT:    v_alignbit_b32 v1, s5, v0, 7
-; GFX9-NEXT:    v_mov_b32_e32 v0, s8
-; GFX9-NEXT:    v_alignbit_b32 v0, s4, v0, 1
+; GFX9-NEXT:    s_lshr_b32 s2, s11, 1
+; GFX9-NEXT:    s_lshl_b32 s3, s7, 31
+; GFX9-NEXT:    s_or_b32 s2, s3, s2
+; GFX9-NEXT:    s_lshl_b32 s3, s6, 23
+; GFX9-NEXT:    s_lshr_b32 s6, s9, 7
+; GFX9-NEXT:    s_lshl_b32 s5, s5, 25
+; GFX9-NEXT:    s_lshr_b32 s7, s10, 9
+; GFX9-NEXT:    s_or_b32 s5, s5, s6
+; GFX9-NEXT:    s_lshr_b32 s6, s8, 1
+; GFX9-NEXT:    s_lshl_b32 s4, s4, 31
+; GFX9-NEXT:    s_or_b32 s3, s3, s7
+; GFX9-NEXT:    s_or_b32 s4, s4, s6
+; GFX9-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v1, s5
+; GFX9-NEXT:    v_mov_b32_e32 v2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; R600-LABEL: fshr_v4i32_imm:
 ; R600:       ; %bb.0: ; %entry
-; R600-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT:    ALU 17, @4, KC0[CB0:0-32], KC1[]
 ; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
 ; R600-NEXT:    CF_END
 ; R600-NEXT:    PAD
 ; R600-NEXT:    ALU clause starting at 4:
-; R600-NEXT:     BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1,
-; R600-NEXT:     BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,
-; R600-NEXT:    9(1.261169e-44), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,
-; R600-NEXT:    7(9.809089e-45), 0(0.000000e+00)
-; R600-NEXT:     BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, 1,
+; R600-NEXT:     LSHL T0.W, KC0[4].X, literal.x,
+; R600-NEXT:     LSHR * T1.W, KC0[5].X, 1,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     LSHL T0.Z, KC0[3].W, literal.x,
+; R600-NEXT:     LSHR T2.W, KC0[4].W, literal.y,
+; R600-NEXT:     OR_INT * T0.W, PV.W, PS,
+; R600-NEXT:    23(3.222986e-44), 9(1.261169e-44)
+; R600-NEXT:     OR_INT T0.Z, PV.Z, PV.W,
+; R600-NEXT:     LSHL T1.W, KC0[3].Z, literal.x,
+; R600-NEXT:     LSHR * T2.W, KC0[4].Z, literal.y,
+; R600-NEXT:    25(3.503246e-44), 7(9.809089e-45)
+; R600-NEXT:     OR_INT T0.Y, PV.W, PS,
+; R600-NEXT:     LSHL T1.W, KC0[3].Y, literal.x,
+; R600-NEXT:     LSHR * T2.W, KC0[4].Y, 1,
+; R600-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; R600-NEXT:     OR_INT T0.X, PV.W, PS,
 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX10-LABEL: fshr_v4i32_imm:
 ; GFX10:       ; %bb.0: ; %entry
-; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
+; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_alignbit_b32 v3, s7, s11, 1
-; GFX10-NEXT:    v_alignbit_b32 v2, s6, s10, 9
-; GFX10-NEXT:    v_alignbit_b32 v1, s5, s9, 7
-; GFX10-NEXT:    v_alignbit_b32 v0, s4, s8, 1
-; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
+; GFX10-NEXT:    s_lshr_b32 s2, s11, 1
+; GFX10-NEXT:    s_lshl_b32 s3, s7, 31
+; GFX10-NEXT:    s_lshr_b32 s7, s10, 9
+; GFX10-NEXT:    s_lshl_b32 s6, s6, 23
+; GFX10-NEXT:    s_lshr_b32 s9, s9, 7
+; GFX10-NEXT:    s_lshl_b32 s5, s5, 25
+; GFX10-NEXT:    s_lshr_b32 s8, s8, 1
+; GFX10-NEXT:    s_lshl_b32 s4, s4, 31
+; GFX10-NEXT:    s_or_b32 s2, s3, s2
+; GFX10-NEXT:    s_or_b32 s3, s6, s7
+; GFX10-NEXT:    s_or_b32 s4, s4, s8
+; GFX10-NEXT:    s_or_b32 s5, s5, s9
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v1, s5
+; GFX10-NEXT:    v_mov_b32_e32 v2, s3
+; GFX10-NEXT:    v_mov_b32_e32 v3, s2
+; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: fshr_v4i32_imm:
 ; GFX11:       ; %bb.0: ; %entry
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b256 s[4:11], s[0:1], 0x34
 ; GFX11-NEXT:    s_load_b64 s[0:1], s[0:1], 0x24
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    v_alignbit_b32 v3, s7, s11, 1
-; GFX11-NEXT:    v_alignbit_b32 v2, s6, s10, 9
-; GFX11-NEXT:    v_alignbit_b32 v1, s5, s9, 7
-; GFX11-NEXT:    v_alignbit_b32 v0, s4, s8, 1
+; GFX11-NEXT:    s_lshr_b32 s2, s11, 1
+; GFX11-NEXT:    s_lshl_b32 s3, s7, 31
+; GFX11-NEXT:    s_lshr_b32 s7, s10, 9
+; GFX11-NEXT:    s_lshl_b32 s6, s6, 23
+; GFX11-NEXT:    s_lshr_b32 s9, s9, 7
+; GFX11-NEXT:    s_lshl_b32 s5, s5, 25
+; GFX11-NEXT:    s_lshr_b32 s8, s8, 1
+; GFX11-NEXT:    s_lshl_b32 s4, s4, 31
+; GFX11-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-NEXT:    s_or_b32 s3, s6, s7
+; GFX11-NEXT:    s_or_b32 s4, s4, s8
+; GFX11-NEXT:    s_or_b32 s5, s5, s9
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s5
+; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT:    v_mov_b32_e32 v2, s3
 ; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
 ; GFX11-NEXT:    s_endpgm
 entry:
   %0 = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
   store <4 x i32> %0, ptr addrspace(1) %in
   ret void
 }

llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

 ;
 ; VI-LABEL: s_insertelement_v2i16_0_reghi:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; VI-NEXT:    s_load_dword s4, s[4:5], 0x30
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_load_dword s2, s[2:3], 0x0
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    s_lshr_b32 s0, s4, 16
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_lshr_b32 s0, s2, 16
-; VI-NEXT:    v_alignbit_b32 v2, s0, v2, 16
+; VI-NEXT:    s_and_b32 s1, s2, 0xffff0000
+; VI-NEXT:    s_or_b32 s0, s0, s1
+; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: s_insertelement_v2i16_0_reghi:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; CI-NEXT:    s_load_dword s4, s[4:5], 0xc
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
 ; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v2, s4
 ; CI-NEXT:    v_mov_b32_e32 v1, s1
+; CI-NEXT:    s_lshr_b32 s0, s4, 16
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_lshr_b32 s0, s2, 16
-; CI-NEXT:    v_alignbit_b32 v2, s0, v2, 16
+; CI-NEXT:    s_and_b32 s1, s2, 0xffff0000
+; CI-NEXT:    s_or_b32 s0, s1, s0
+; CI-NEXT:    v_mov_b32_e32 v2, s0
 ; CI-NEXT:    flat_store_dword v[0:1], v2
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: s_insertelement_v2i16_0_reghi:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x0
 ; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x30

 ; GFX9-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_load_dword s2, s[2:3], 0x0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    s_lshr_b32 s0, s4, 16
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_lshr_b32 s1, s2, 16
-; VI-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; VI-NEXT:    s_and_b32 s1, s2, 0xffff0000
+; VI-NEXT:    s_or_b32 s1, s0, s1
+; VI-NEXT:    v_mov_b32_e32 v2, s1
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    ;;#ASMSTART
 ; VI-NEXT:    ; use s0
 ; VI-NEXT:    ;;#ASMEND
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_mov_b32_e32 v2, s4
 ; CI-NEXT:    v_mov_b32_e32 v0, s0
+; CI-NEXT:    v_mov_b32_e32 v1, s1
 ; CI-NEXT:    s_lshr_b32 s0, s4, 16
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_lshr_b32 s1, s2, 16
-; CI-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; CI-NEXT:    s_and_b32 s1, s2, 0xffff0000
+; CI-NEXT:    s_or_b32 s1, s1, s0
+; CI-NEXT:    v_mov_b32_e32 v2, s1
 ; CI-NEXT:    flat_store_dword v[0:1], v2
 ; CI-NEXT:    ;;#ASMSTART
 ; CI-NEXT:    ; use s0
 ; CI-NEXT:    ;;#ASMEND
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: s_insertelement_v2i16_0_reghi_multi_use_1:
 ; GFX11:       ; %bb.0:

 ; GFX9-NEXT:    s_endpgm
 ;
 ; VI-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; VI-NEXT:    s_load_dword s4, s[4:5], 0x10
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_load_dword s2, s[2:3], 0x0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    s_lshr_b32 s0, s4, 16
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_lshr_b32 s1, s2, 16
-; VI-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; VI-NEXT:    s_and_b32 s2, s2, 0xffff0000
+; VI-NEXT:    s_or_b32 s2, s0, s2
+; VI-NEXT:    v_mov_b32_e32 v2, s2
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    ;;#ASMSTART
 ; VI-NEXT:    ; use s0
 ; VI-NEXT:    ;;#ASMEND
 ; VI-NEXT:    ;;#ASMSTART
 ; VI-NEXT:    ; use s1
 ; VI-NEXT:    ;;#ASMEND
 ; VI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; CI-NEXT:    s_load_dword s4, s[4:5], 0x4
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    s_load_dword s2, s[2:3], 0x0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_mov_b32_e32 v2, s4
 ; CI-NEXT:    v_mov_b32_e32 v0, s0
+; CI-NEXT:    v_mov_b32_e32 v1, s1
 ; CI-NEXT:    s_lshr_b32 s0, s4, 16
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_lshr_b32 s1, s2, 16
-; CI-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; CI-NEXT:    s_and_b32 s1, s2, 0xffff0000
+; CI-NEXT:    s_or_b32 s1, s1, s0
+; CI-NEXT:    v_mov_b32_e32 v2, s1
+; CI-NEXT:    s_lshr_b32 s2, s2, 16
 ; CI-NEXT:    flat_store_dword v[0:1], v2
 ; CI-NEXT:    ;;#ASMSTART
 ; CI-NEXT:    ; use s0
 ; CI-NEXT:    ;;#ASMEND
 ; CI-NEXT:    ;;#ASMSTART
-; CI-NEXT:    ; use s1
+; CI-NEXT:    ; use s2
 ; CI-NEXT:    ;;#ASMEND
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: s_insertelement_v2i16_0_reghi_both_multi_use_1:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[4:7], s[0:1], 0x0
 ; GFX11-NEXT:    s_load_b32 s0, s[0:1], 0x10

llvm/test/CodeGen/AMDGPU/load-constant-i8.ll

; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   ret void
 }
 
 define amdgpu_kernel void @constant_zextload_v4i8_to_v4i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
 ; GFX6-NOHSA-LABEL: constant_zextload_v4i8_to_v4i16:
 ; GFX6-NOHSA:       ; %bb.0:
 ; GFX6-NOHSA-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GFX6-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT:    s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT:    s_load_dword s2, s[2:3], 0x0
 ; GFX6-NOHSA-NEXT:    s_mov_b32 s3, 0xf000
-; GFX6-NOHSA-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT:    s_and_b32 s5, s4, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s6, s4, 24
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s4
-; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v0, s6, v0, 16
-; GFX6-NOHSA-NEXT:    s_lshl_b32 s5, s5, 8
-; GFX6-NOHSA-NEXT:    s_or_b32 s4, s4, s5
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v0
+; GFX6-NOHSA-NEXT:    s_and_b32 s4, s2, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s5, s2, 0xff
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s6, s2, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX6-NOHSA-NEXT:    s_lshl_b32 s4, s4, 8
+; GFX6-NOHSA-NEXT:    s_and_b32 s2, s2, 0xff0000
+; GFX6-NOHSA-NEXT:    s_or_b32 s4, s5, s4
+; GFX6-NOHSA-NEXT:    s_or_b32 s2, s2, s6
+; GFX6-NOHSA-NEXT:    s_and_b32 s5, s2, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NOHSA-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX6-NOHSA-NEXT:    s_endpgm
 ;
 ; GFX7-HSA-LABEL: constant_zextload_v4i8_to_v4i16:
 ; GFX7-HSA:       ; %bb.0:
 ; GFX7-HSA-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX7-HSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7-HSA-NEXT:    s_load_dword s2, s[2:3], 0x0
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX7-HSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7-HSA-NEXT:    s_and_b32 s0, s2, 0xff00
-; GFX7-HSA-NEXT:    s_lshr_b32 s1, s2, 24
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s2
-; GFX7-HSA-NEXT:    s_and_b32 s2, s2, 0xff
+; GFX7-HSA-NEXT:    s_and_b32 s1, s2, 0xff
+; GFX7-HSA-NEXT:    s_lshr_b32 s3, s2, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s2, s2, 8
 ; GFX7-HSA-NEXT:    s_lshl_b32 s0, s0, 8
-; GFX7-HSA-NEXT:    v_alignbit_b32 v2, s1, v2, 16
-; GFX7-HSA-NEXT:    s_or_b32 s0, s2, s0
-; GFX7-HSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v2
+; GFX7-HSA-NEXT:    s_and_b32 s2, s2, 0xff0000
+; GFX7-HSA-NEXT:    s_or_b32 s0, s1, s0
+; GFX7-HSA-NEXT:    s_or_b32 s1, s2, s3
+; GFX7-HSA-NEXT:    s_and_b32 s1, s1, 0xff00ff
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX7-HSA-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; GFX7-HSA-NEXT:    s_endpgm
 ;
 ; GFX8-NOHSA-LABEL: constant_zextload_v4i8_to_v4i16:
 ; GFX8-NOHSA:       ; %bb.0:
 ; GFX8-NOHSA-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX8-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NOHSA-NEXT:    s_load_dword s2, s[2:3], 0x0
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX8-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v2, 8, s2
 ; GFX8-NOHSA-NEXT:    s_lshr_b32 s0, s2, 24
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s2
-; GFX8-NOHSA-NEXT:    s_and_b32 s1, s2, 0xff
-; GFX8-NOHSA-NEXT:    v_alignbit_b32 v3, s0, v3, 16
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v2, 8, s2
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s1, s2, 0x80010
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT:    s_and_b32 s2, s2, 0xff
 ; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NOHSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v3
-; GFX8-NOHSA-NEXT:    v_or_b32_e32 v2, s1, v2
+; GFX8-NOHSA-NEXT:    s_or_b32 s0, s1, s0
+; GFX8-NOHSA-NEXT:    v_or_b32_e32 v2, s2, v2
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX8-NOHSA-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; GFX8-NOHSA-NEXT:    s_endpgm
 ;
 ; EG-LABEL: constant_zextload_v4i8_to_v4i16:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 1, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6
 ; EG-NEXT:    ALU 31, @10, KC0[CB0:0-32], KC1[]

 
 define amdgpu_kernel void @constant_zextload_v8i8_to_v8i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
 ; GFX6-NOHSA-LABEL: constant_zextload_v8i8_to_v8i16:
 ; GFX6-NOHSA:       ; %bb.0:
 ; GFX6-NOHSA-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GFX6-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NOHSA-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
 ; GFX6-NOHSA-NEXT:    s_mov_b32 s3, 0xf000
-; GFX6-NOHSA-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NOHSA-NEXT:    s_and_b32 s6, s4, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s7, s4, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s8, s5, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s9, s5, 24
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s5
-; GFX6-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v1, s4
-; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v0, s9, v0, 16
-; GFX6-NOHSA-NEXT:    s_lshl_b32 s8, s8, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v1, s7, v1, 16
+; GFX6-NOHSA-NEXT:    s_and_b32 s2, s4, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s6, s5, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s7, s5, 0xff
+; GFX6-NOHSA-NEXT:    s_and_b32 s8, s4, 0xff
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s9, s5, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s5, s5, 8
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s10, s4, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s4, s4, 8
 ; GFX6-NOHSA-NEXT:    s_lshl_b32 s6, s6, 8
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v0
-; GFX6-NOHSA-NEXT:    s_or_b32 s5, s5, s8
-; GFX6-NOHSA-NEXT:    s_or_b32 s4, s4, s6
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v1
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s4
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT:    s_lshl_b32 s2, s2, 8
+; GFX6-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff0000
+; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff0000
+; GFX6-NOHSA-NEXT:    s_or_b32 s6, s7, s6
+; GFX6-NOHSA-NEXT:    s_or_b32 s7, s8, s2
+; GFX6-NOHSA-NEXT:    s_or_b32 s2, s5, s9
+; GFX6-NOHSA-NEXT:    s_or_b32 s4, s4, s10
+; GFX6-NOHSA-NEXT:    s_and_b32 s5, s2, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v1, s4
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v3, s5
 ; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; GFX6-NOHSA-NEXT:    s_endpgm
 ;
 ; GFX7-HSA-LABEL: constant_zextload_v8i8_to_v8i16:
 ; GFX7-HSA:       ; %bb.0:
 ; GFX7-HSA-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX7-HSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7-HSA-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX7-HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT:    s_lshr_b32 s5, s3, 24
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s3
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s5, v0, 16
+; GFX7-HSA-NEXT:    s_and_b32 s1, s3, 0xff00
+; GFX7-HSA-NEXT:    s_and_b32 s4, s3, 0xff
+; GFX7-HSA-NEXT:    s_lshl_b32 s1, s1, 8
 ; GFX7-HSA-NEXT:    s_and_b32 s0, s2, 0xff00
-; GFX7-HSA-NEXT:    s_lshr_b32 s1, s2, 24
-; GFX7-HSA-NEXT:    s_and_b32 s4, s3, 0xff00
-; GFX7-HSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s2
-; GFX7-HSA-NEXT:    s_and_b32 s3, s3, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s4, s4, 8
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s1, v0, 16
-; GFX7-HSA-NEXT:    s_and_b32 s1, s2, 0xff
+; GFX7-HSA-NEXT:    s_and_b32 s5, s2, 0xff
+; GFX7-HSA-NEXT:    s_lshr_b32 s6, s3, 16
+; GFX7-HSA-NEXT:    s_or_b32 s1, s4, s1
+; GFX7-HSA-NEXT:    s_lshr_b32 s3, s3, 8
+; GFX7-HSA-NEXT:    s_lshr_b32 s4, s2, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX7-HSA-NEXT:    s_and_b32 s3, s3, 0xff0000
+; GFX7-HSA-NEXT:    s_and_b32 s2, s2, 0xff0000
 ; GFX7-HSA-NEXT:    s_lshl_b32 s0, s0, 8
-; GFX7-HSA-NEXT:    s_or_b32 s3, s3, s4
-; GFX7-HSA-NEXT:    s_or_b32 s0, s1, s0
-; GFX7-HSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v0
+; GFX7-HSA-NEXT:    s_or_b32 s3, s3, s6
+; GFX7-HSA-NEXT:    s_or_b32 s2, s2, s4
+; GFX7-HSA-NEXT:    s_or_b32 s0, s5, s0
+; GFX7-HSA-NEXT:    s_and_b32 s3, s3, 0xff00ff
+; GFX7-HSA-NEXT:    s_and_b32 s2, s2, 0xff00ff
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v1, s2
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX7-HSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; GFX7-HSA-NEXT:    s_endpgm
 ;
 ; GFX8-NOHSA-LABEL: constant_zextload_v8i8_to_v8i16:
 ; GFX8-NOHSA:       ; %bb.0:
 ; GFX8-NOHSA-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX8-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NOHSA-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s1
 ; GFX8-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v0, s2
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s0, s2, 24
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s1, s3, 24
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v3, 8, s2
-; GFX8-NOHSA-NEXT:    s_bfe_u32 s4, s3, 0x80010
-; GFX8-NOHSA-NEXT:    s_lshl_b32 s1, s1, 16
-; GFX8-NOHSA-NEXT:    v_alignbit_b32 v0, s0, v0, 16
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v2, 8, s3
-; GFX8-NOHSA-NEXT:    s_or_b32 s0, s4, s1
-; GFX8-NOHSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v0
-; GFX8-NOHSA-NEXT:    s_and_b32 s1, s2, 0xff
-; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v0, 16, v3
-; GFX8-NOHSA-NEXT:    v_or_b32_e32 v0, s1, v0
-; GFX8-NOHSA-NEXT:    s_and_b32 s1, s3, 0xff
-; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NOHSA-NEXT:    v_or_b32_e32 v2, s1, v2
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v0, 8, s2
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s0, s3, 24
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s4, s2, 24
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v1, 8, s3
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s1, s3, 0x80010
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s5, s2, 0x80010
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s4, s4, 16
+; GFX8-NOHSA-NEXT:    s_and_b32 s2, s2, 0xff
+; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT:    s_or_b32 s0, s1, s0
+; GFX8-NOHSA-NEXT:    s_or_b32 s1, s5, s4
+; GFX8-NOHSA-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX8-NOHSA-NEXT:    s_and_b32 s2, s3, 0xff
+; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NOHSA-NEXT:    v_or_b32_e32 v2, s2, v1
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; GFX8-NOHSA-NEXT:    s_endpgm
 ;
 ; EG-LABEL: constant_zextload_v8i8_to_v8i16:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 1, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6

 ; GFX6-NOHSA:       ; %bb.0:
 ; GFX6-NOHSA-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GFX6-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NOHSA-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
 ; GFX6-NOHSA-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NOHSA-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NOHSA-NEXT:    s_and_b32 s8, s6, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s9, s6, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s10, s7, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s11, s7, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s12, s4, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s13, s4, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s14, s5, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s15, s5, 24
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s5
-; GFX6-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v1, s4
-; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v2, s7
-; GFX6-NOHSA-NEXT:    s_and_b32 s7, s7, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v3, s6
-; GFX6-NOHSA-NEXT:    s_and_b32 s6, s6, 0xff
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v0, s15, v0, 16
-; GFX6-NOHSA-NEXT:    s_lshl_b32 s14, s14, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v1, s13, v1, 16
-; GFX6-NOHSA-NEXT:    s_lshl_b32 s12, s12, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v2, s11, v2, 16
+; GFX6-NOHSA-NEXT:    s_and_b32 s9, s7, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s10, s4, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s11, s5, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s12, s5, 0xff
+; GFX6-NOHSA-NEXT:    s_and_b32 s13, s4, 0xff
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s14, s5, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s5, s5, 8
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s15, s4, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s4, s4, 8
+; GFX6-NOHSA-NEXT:    s_and_b32 s16, s7, 0xff
+; GFX6-NOHSA-NEXT:    s_and_b32 s17, s6, 0xff
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s18, s7, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s7, s7, 8
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s19, s6, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s6, s6, 8
+; GFX6-NOHSA-NEXT:    s_lshl_b32 s11, s11, 8
 ; GFX6-NOHSA-NEXT:    s_lshl_b32 s10, s10, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v4, s9, v3, 16
+; GFX6-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff0000
+; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff0000
+; GFX6-NOHSA-NEXT:    s_lshl_b32 s9, s9, 8
 ; GFX6-NOHSA-NEXT:    s_lshl_b32 s8, s8, 8
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v0
+; GFX6-NOHSA-NEXT:    s_and_b32 s7, s7, 0xff0000
+; GFX6-NOHSA-NEXT:    s_and_b32 s6, s6, 0xff0000
+; GFX6-NOHSA-NEXT:    s_or_b32 s11, s12, s11
+; GFX6-NOHSA-NEXT:    s_or_b32 s10, s13, s10
 ; GFX6-NOHSA-NEXT:    s_or_b32 s5, s5, s14
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v1
-; GFX6-NOHSA-NEXT:    s_or_b32 s4, s4, s12
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v7, 0xff00ff, v2
-; GFX6-NOHSA-NEXT:    s_or_b32 s7, s7, s10
-; GFX6-NOHSA-NEXT:    s_or_b32 s6, s6, s8
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v5, 0xff00ff, v4
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v4, s6
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v6, s7
-; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s4
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v2, s5
-; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT:    s_or_b32 s4, s4, s15
+; GFX6-NOHSA-NEXT:    s_or_b32 s9, s16, s9
+; GFX6-NOHSA-NEXT:    s_or_b32 s8, s17, s8
+; GFX6-NOHSA-NEXT:    s_or_b32 s7, s7, s18
+; GFX6-NOHSA-NEXT:    s_or_b32 s6, s6, s19
+; GFX6-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s7, s7, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s6, s6, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff00ff
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v2, s9
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v4, s10
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v6, s11
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v1, s6
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v5, s4
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v7, s5
+; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0
 ; GFX6-NOHSA-NEXT:    s_endpgm
 ;
 ; GFX7-HSA-LABEL: constant_zextload_v16i8_to_v16i16:
 ; GFX7-HSA:       ; %bb.0:
 ; GFX7-HSA-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX7-HSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7-HSA-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
 ; GFX7-HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT:    s_lshr_b32 s13, s5, 24
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s5
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s13, v0, 16
-; GFX7-HSA-NEXT:    s_lshr_b32 s11, s4, 24
-; GFX7-HSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s11, v0, 16
-; GFX7-HSA-NEXT:    s_lshr_b32 s9, s7, 24
-; GFX7-HSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s7
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s9, v0, 16
+; GFX7-HSA-NEXT:    s_and_b32 s9, s5, 0xff00
+; GFX7-HSA-NEXT:    s_and_b32 s10, s5, 0xff
+; GFX7-HSA-NEXT:    s_lshl_b32 s9, s9, 8
+; GFX7-HSA-NEXT:    s_and_b32 s8, s4, 0xff00
+; GFX7-HSA-NEXT:    s_and_b32 s11, s4, 0xff
+; GFX7-HSA-NEXT:    s_or_b32 s9, s10, s9
+; GFX7-HSA-NEXT:    s_lshr_b32 s10, s4, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s4, s4, 8
+; GFX7-HSA-NEXT:    s_and_b32 s3, s7, 0xff00
+; GFX7-HSA-NEXT:    s_and_b32 s4, s4, 0xff0000
 ; GFX7-HSA-NEXT:    s_and_b32 s2, s6, 0xff00
-; GFX7-HSA-NEXT:    s_lshr_b32 s3, s6, 24
-; GFX7-HSA-NEXT:    s_and_b32 s8, s7, 0xff00
-; GFX7-HSA-NEXT:    s_and_b32 s10, s4, 0xff00
-; GFX7-HSA-NEXT:    s_and_b32 s12, s5, 0xff00
-; GFX7-HSA-NEXT:    v_and_b32_e32 v7, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s6
-; GFX7-HSA-NEXT:    s_and_b32 s5, s5, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s12, s12, 8
-; GFX7-HSA-NEXT:    s_and_b32 s4, s4, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s10, s10, 8
-; GFX7-HSA-NEXT:    s_and_b32 s7, s7, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s8, s8, 8
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s3, v0, 16
-; GFX7-HSA-NEXT:    s_and_b32 s3, s6, 0xff
+; GFX7-HSA-NEXT:    s_or_b32 s4, s4, s10
+; GFX7-HSA-NEXT:    s_and_b32 s10, s7, 0xff
+; GFX7-HSA-NEXT:    s_lshl_b32 s3, s3, 8
+; GFX7-HSA-NEXT:    s_or_b32 s3, s10, s3
+; GFX7-HSA-NEXT:    s_and_b32 s10, s6, 0xff
 ; GFX7-HSA-NEXT:    s_lshl_b32 s2, s2, 8
+; GFX7-HSA-NEXT:    s_or_b32 s2, s10, s2
+; GFX7-HSA-NEXT:    s_lshr_b32 s10, s7, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s7, s7, 8
+; GFX7-HSA-NEXT:    s_and_b32 s7, s7, 0xff0000
+; GFX7-HSA-NEXT:    s_lshr_b32 s12, s5, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s5, s5, 8
+; GFX7-HSA-NEXT:    s_or_b32 s7, s7, s10
+; GFX7-HSA-NEXT:    s_lshr_b32 s10, s6, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s6, s6, 8
+; GFX7-HSA-NEXT:    s_and_b32 s5, s5, 0xff0000
+; GFX7-HSA-NEXT:    s_and_b32 s6, s6, 0xff0000
+; GFX7-HSA-NEXT:    s_lshl_b32 s8, s8, 8
 ; GFX7-HSA-NEXT:    s_or_b32 s5, s5, s12
-; GFX7-HSA-NEXT:    s_or_b32 s4, s4, s10
-; GFX7-HSA-NEXT:    s_or_b32 s7, s7, s8
-; GFX7-HSA-NEXT:    s_or_b32 s2, s3, s2
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT:    s_or_b32 s6, s6, s10
+; GFX7-HSA-NEXT:    s_or_b32 s8, s11, s8
+; GFX7-HSA-NEXT:    s_and_b32 s5, s5, 0xff00ff
+; GFX7-HSA-NEXT:    s_and_b32 s4, s4, 0xff00ff
+; GFX7-HSA-NEXT:    s_and_b32 s7, s7, 0xff00ff
+; GFX7-HSA-NEXT:    s_and_b32 s6, s6, 0xff00ff
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX7-HSA-NEXT:    s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s3
 ; GFX7-HSA-NEXT:    s_addc_u32 s3, s1, 0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v9, s3
-; GFX7-HSA-NEXT:    v_and_b32_e32 v5, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v6, s7
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v8, s2
-; GFX7-HSA-NEXT:    flat_store_dwordx4 v[8:9], v[4:7]
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v1, s6
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v5, s1
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v3, s5
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX7-HSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; GFX7-HSA-NEXT:    s_endpgm
 ;
 ; GFX8-NOHSA-LABEL: constant_zextload_v16i8_to_v16i16:
 ; GFX8-NOHSA:       ; %bb.0:
 ; GFX8-NOHSA-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX8-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NOHSA-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
 ; GFX8-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v0, 8, s4
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s3, s4, 24
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v1, s4
-; GFX8-NOHSA-NEXT:    v_alignbit_b32 v1, s3, v1, 16
-; GFX8-NOHSA-NEXT:    s_and_b32 s3, s4, 0xff
-; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NOHSA-NEXT:    v_or_b32_e32 v0, s3, v0
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s3, s7, 24
-; GFX8-NOHSA-NEXT:    s_lshl_b32 s3, s3, 16
-; GFX8-NOHSA-NEXT:    s_bfe_u32 s4, s7, 0x80010
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s8, s5, 24
-; GFX8-NOHSA-NEXT:    s_bfe_u32 s9, s5, 0x80010
-; GFX8-NOHSA-NEXT:    s_and_b32 s10, s5, 0xff
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s2, s5, 24
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s3, s5, 0x80010
+; GFX8-NOHSA-NEXT:    s_and_b32 s8, s5, 0xff
 ; GFX8-NOHSA-NEXT:    s_lshl_b32 s5, s5, 8
-; GFX8-NOHSA-NEXT:    s_or_b32 s3, s4, s3
-; GFX8-NOHSA-NEXT:    s_and_b32 s4, s7, 0xff
-; GFX8-NOHSA-NEXT:    s_lshl_b32 s7, s7, 8
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v2, 8, s6
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s2, s6, 24
-; GFX8-NOHSA-NEXT:    s_lshl_b32 s8, s8, 16
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s9, s4, 24
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s2, s2, 16
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v0, 8, s4
 ; GFX8-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff0000
-; GFX8-NOHSA-NEXT:    s_and_b32 s7, s7, 0xff0000
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s6
-; GFX8-NOHSA-NEXT:    s_or_b32 s8, s9, s8
-; GFX8-NOHSA-NEXT:    s_or_b32 s5, s10, s5
-; GFX8-NOHSA-NEXT:    s_or_b32 s4, s4, s7
-; GFX8-NOHSA-NEXT:    v_alignbit_b32 v3, s2, v3, 16
-; GFX8-NOHSA-NEXT:    s_and_b32 s2, s6, 0xff
-; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NOHSA-NEXT:    v_or_b32_e32 v2, s2, v2
+; GFX8-NOHSA-NEXT:    s_or_b32 s10, s3, s2
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s2, s9, 16
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s3, s4, 0x80010
+; GFX8-NOHSA-NEXT:    s_or_b32 s5, s8, s5
+; GFX8-NOHSA-NEXT:    s_or_b32 s8, s3, s2
+; GFX8-NOHSA-NEXT:    s_and_b32 s2, s4, 0xff
+; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT:    v_or_b32_e32 v0, s2, v0
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s2, s7, 24
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s2, s2, 16
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s3, s7, 0x80010
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s4, s7, 8
+; GFX8-NOHSA-NEXT:    s_or_b32 s2, s3, s2
+; GFX8-NOHSA-NEXT:    s_and_b32 s3, s7, 0xff
+; GFX8-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff0000
+; GFX8-NOHSA-NEXT:    s_or_b32 s3, s3, s4
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s4, s6, 24
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s4, s4, 16
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s7, s6, 0x80010
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v1, 8, s6
+; GFX8-NOHSA-NEXT:    s_or_b32 s4, s7, s4
+; GFX8-NOHSA-NEXT:    s_and_b32 s6, s6, 0xff
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s2
 ; GFX8-NOHSA-NEXT:    s_add_u32 s2, s0, 16
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX8-NOHSA-NEXT:    s_addc_u32 s3, s1, 0
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v7, s3
-; GFX8-NOHSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v3
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s4
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v6, s2
-; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[6:7], v[2:5]
-; GFX8-NOHSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v1
+; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v6, s3
+; GFX8-NOHSA-NEXT:    v_or_b32_e32 v1, s6, v1
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v2, s4
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s2
+; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[5:6], v[1:4]
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v1, s8
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v2, s5
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s8
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s10
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; GFX8-NOHSA-NEXT:    s_endpgm
 ;
 ; EG-LABEL: constant_zextload_v16i8_to_v16i16:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 1, @10, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @8

 ; GFX6-NOHSA:       ; %bb.0:
 ; GFX6-NOHSA-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
 ; GFX6-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NOHSA-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
 ; GFX6-NOHSA-NEXT:    s_mov_b32 s11, 0xf000
 ; GFX6-NOHSA-NEXT:    s_mov_b32 s10, -1
 ; GFX6-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NOHSA-NEXT:    s_and_b32 s12, s6, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s13, s6, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s14, s7, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s15, s7, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s16, s4, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s17, s4, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s18, s5, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s19, s5, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s20, s2, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s21, s2, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s22, s3, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s23, s3, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s24, s0, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s25, s0, 24
-; GFX6-NOHSA-NEXT:    s_and_b32 s26, s1, 0xff00
-; GFX6-NOHSA-NEXT:    s_lshr_b32 s27, s1, 24
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s1
-; GFX6-NOHSA-NEXT:    s_and_b32 s1, s1, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v1, s0
-; GFX6-NOHSA-NEXT:    s_and_b32 s0, s0, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v2, s3
-; GFX6-NOHSA-NEXT:    s_and_b32 s3, s3, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v3, s2
-; GFX6-NOHSA-NEXT:    s_and_b32 s2, s2, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v4, s5
-; GFX6-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v5, s4
-; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v6, s7
-; GFX6-NOHSA-NEXT:    s_and_b32 s7, s7, 0xff
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v7, s6
-; GFX6-NOHSA-NEXT:    s_and_b32 s6, s6, 0xff
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v0, s27, v0, 16
-; GFX6-NOHSA-NEXT:    s_lshl_b32 s26, s26, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v1, s25, v1, 16
-; GFX6-NOHSA-NEXT:    s_lshl_b32 s24, s24, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v2, s23, v2, 16
-; GFX6-NOHSA-NEXT:    s_lshl_b32 s22, s22, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v8, s21, v3, 16
-; GFX6-NOHSA-NEXT:    s_lshl_b32 s20, s20, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v4, s19, v4, 16
+; GFX6-NOHSA-NEXT:    s_and_b32 s13, s7, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s14, s4, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s15, s5, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s16, s2, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s17, s3, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s18, s0, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s19, s1, 0xff00
+; GFX6-NOHSA-NEXT:    s_and_b32 s20, s1, 0xff
+; GFX6-NOHSA-NEXT:    s_and_b32 s21, s0, 0xff
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s22, s1, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s1, s1, 8
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s23, s0, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s0, s0, 8
+; GFX6-NOHSA-NEXT:    s_and_b32 s24, s3, 0xff
+; GFX6-NOHSA-NEXT:    s_and_b32 s25, s2, 0xff
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s26, s3, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s3, s3, 8
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s27, s2, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s2, s2, 8
+; GFX6-NOHSA-NEXT:    s_and_b32 s28, s5, 0xff
+; GFX6-NOHSA-NEXT:    s_and_b32 s29, s4, 0xff
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s30, s5, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s5, s5, 8
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s31, s4, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s4, s4, 8
+; GFX6-NOHSA-NEXT:    s_and_b32 s33, s7, 0xff
+; GFX6-NOHSA-NEXT:    s_and_b32 s34, s6, 0xff
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s35, s7, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s7, s7, 8
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s36, s6, 16
+; GFX6-NOHSA-NEXT:    s_lshr_b32 s6, s6, 8
+; GFX6-NOHSA-NEXT:    s_lshl_b32 s19, s19, 8
 ; GFX6-NOHSA-NEXT:    s_lshl_b32 s18, s18, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v9, s17, v5, 16
+; GFX6-NOHSA-NEXT:    s_and_b32 s1, s1, 0xff0000
+; GFX6-NOHSA-NEXT:    s_and_b32 s0, s0, 0xff0000
+; GFX6-NOHSA-NEXT:    s_lshl_b32 s17, s17, 8
 ; GFX6-NOHSA-NEXT:    s_lshl_b32 s16, s16, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v6, s15, v6, 16
+; GFX6-NOHSA-NEXT:    s_and_b32 s3, s3, 0xff0000
+; GFX6-NOHSA-NEXT:    s_and_b32 s2, s2, 0xff0000
+; GFX6-NOHSA-NEXT:    s_lshl_b32 s15, s15, 8
 ; GFX6-NOHSA-NEXT:    s_lshl_b32 s14, s14, 8
-; GFX6-NOHSA-NEXT:    v_alignbit_b32 v10, s13, v7, 16
+; GFX6-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff0000
+; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff0000
+; GFX6-NOHSA-NEXT:    s_lshl_b32 s13, s13, 8
 ; GFX6-NOHSA-NEXT:    s_lshl_b32 s12, s12, 8
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v0
-; GFX6-NOHSA-NEXT:    s_or_b32 s1, s1, s26
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v1
-; GFX6-NOHSA-NEXT:    s_or_b32 s0, s0, s24
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v7, 0xff00ff, v2
-; GFX6-NOHSA-NEXT:    s_or_b32 s3, s3, s22
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v5, 0xff00ff, v8
-; GFX6-NOHSA-NEXT:    s_or_b32 s2, s2, s20
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v11, 0xff00ff, v4
-; GFX6-NOHSA-NEXT:    s_or_b32 s5, s5, s18
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v9, 0xff00ff, v9
-; GFX6-NOHSA-NEXT:    s_or_b32 s4, s4, s16
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v15, 0xff00ff, v6
-; GFX6-NOHSA-NEXT:    s_or_b32 s7, s7, s14
-; GFX6-NOHSA-NEXT:    s_or_b32 s6, s6, s12
-; GFX6-NOHSA-NEXT:    v_and_b32_e32 v13, 0xff00ff, v10
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v12, s6
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v14, s7
-; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[12:15], off, s[8:11], 0 offset:48
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v8, s4
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v10, s5
-; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[8:11], off, s[8:11], 0 offset:32
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v4, s2
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v6, s3
-; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v2, s1
-; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT:    s_and_b32 s7, s7, 0xff0000
+; GFX6-NOHSA-NEXT:    s_and_b32 s6, s6, 0xff0000
+; GFX6-NOHSA-NEXT:    s_or_b32 s19, s20, s19
+; GFX6-NOHSA-NEXT:    s_or_b32 s18, s21, s18
+; GFX6-NOHSA-NEXT:    s_or_b32 s1, s1, s22
+; GFX6-NOHSA-NEXT:    s_or_b32 s0, s0, s23
+; GFX6-NOHSA-NEXT:    s_or_b32 s17, s24, s17
+; GFX6-NOHSA-NEXT:    s_or_b32 s16, s25, s16
+; GFX6-NOHSA-NEXT:    s_or_b32 s3, s3, s26
+; GFX6-NOHSA-NEXT:    s_or_b32 s2, s2, s27
+; GFX6-NOHSA-NEXT:    s_or_b32 s15, s28, s15
+; GFX6-NOHSA-NEXT:    s_or_b32 s14, s29, s14
+; GFX6-NOHSA-NEXT:    s_or_b32 s5, s5, s30
+; GFX6-NOHSA-NEXT:    s_or_b32 s4, s4, s31
+; GFX6-NOHSA-NEXT:    s_or_b32 s13, s33, s13
+; GFX6-NOHSA-NEXT:    s_or_b32 s12, s34, s12
+; GFX6-NOHSA-NEXT:    s_or_b32 s7, s7, s35
+; GFX6-NOHSA-NEXT:    s_or_b32 s6, s6, s36
+; GFX6-NOHSA-NEXT:    s_and_b32 s1, s1, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s0, s0, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s3, s3, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s2, s2, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s5, s5, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s7, s7, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s6, s6, 0xff00ff
+; GFX6-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff00ff
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v2, s13
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v4, s14
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v6, s15
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v8, s16
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v10, s17
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v12, s18
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v14, s19
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v1, s6
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v5, s4
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v7, s5
+; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v9, s2
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v11, s3
+; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[8:11], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v13, s0
+; GFX6-NOHSA-NEXT:    v_mov_b32_e32 v15, s1
+; GFX6-NOHSA-NEXT:    buffer_store_dwordx4 v[12:15], off, s[8:11], 0
 ; GFX6-NOHSA-NEXT:    s_endpgm
 ;
 ; GFX7-HSA-LABEL: constant_zextload_v32i8_to_v32i16:
 ; GFX7-HSA:       ; %bb.0:
 ; GFX7-HSA-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x0
 ; GFX7-HSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7-HSA-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
 ; GFX7-HSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-HSA-NEXT:    s_lshr_b32 s25, s1, 24
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s1
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s25, v0, 16
-; GFX7-HSA-NEXT:    s_lshr_b32 s23, s0, 24
-; GFX7-HSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s0
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s23, v0, 16
-; GFX7-HSA-NEXT:    s_lshr_b32 s21, s3, 24
-; GFX7-HSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s3
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s21, v0, 16
-; GFX7-HSA-NEXT:    s_lshr_b32 s19, s2, 24
-; GFX7-HSA-NEXT:    s_and_b32 s24, s1, 0xff00
-; GFX7-HSA-NEXT:    v_and_b32_e32 v7, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s2
-; GFX7-HSA-NEXT:    s_and_b32 s22, s0, 0xff00
-; GFX7-HSA-NEXT:    s_and_b32 s1, s1, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s24, s24, 8
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s19, v0, 16
-; GFX7-HSA-NEXT:    s_lshr_b32 s17, s5, 24
-; GFX7-HSA-NEXT:    s_and_b32 s20, s3, 0xff00
-; GFX7-HSA-NEXT:    s_or_b32 s24, s1, s24
-; GFX7-HSA-NEXT:    s_and_b32 s0, s0, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s1, s22, 8
-; GFX7-HSA-NEXT:    v_and_b32_e32 v5, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s5
-; GFX7-HSA-NEXT:    s_and_b32 s18, s2, 0xff00
-; GFX7-HSA-NEXT:    s_or_b32 s22, s0, s1
+; GFX7-HSA-NEXT:    s_and_b32 s17, s1, 0xff00
+; GFX7-HSA-NEXT:    s_and_b32 s16, s0, 0xff00
+; GFX7-HSA-NEXT:    s_and_b32 s18, s1, 0xff
+; GFX7-HSA-NEXT:    s_lshl_b32 s17, s17, 8
+; GFX7-HSA-NEXT:    s_or_b32 s17, s18, s17
+; GFX7-HSA-NEXT:    s_and_b32 s18, s0, 0xff
+; GFX7-HSA-NEXT:    s_lshl_b32 s16, s16, 8
+; GFX7-HSA-NEXT:    s_or_b32 s16, s18, s16
+; GFX7-HSA-NEXT:    s_lshr_b32 s18, s1, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s1, s1, 8
+; GFX7-HSA-NEXT:    s_and_b32 s1, s1, 0xff0000
+; GFX7-HSA-NEXT:    s_or_b32 s1, s1, s18
+; GFX7-HSA-NEXT:    s_and_b32 s18, s1, 0xff00ff
+; GFX7-HSA-NEXT:    s_lshr_b32 s1, s0, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s0, s0, 8
+; GFX7-HSA-NEXT:    s_and_b32 s0, s0, 0xff0000
+; GFX7-HSA-NEXT:    s_and_b32 s15, s3, 0xff00
+; GFX7-HSA-NEXT:    s_or_b32 s0, s0, s1
+; GFX7-HSA-NEXT:    s_and_b32 s14, s2, 0xff00
+; GFX7-HSA-NEXT:    s_and_b32 s19, s0, 0xff00ff
 ; GFX7-HSA-NEXT:    s_and_b32 s0, s3, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s1, s20, 8
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s17, v0, 16
-; GFX7-HSA-NEXT:    s_lshr_b32 s15, s4, 24
-; GFX7-HSA-NEXT:    s_and_b32 s16, s5, 0xff00
-; GFX7-HSA-NEXT:    s_or_b32 s3, s0, s1
+; GFX7-HSA-NEXT:    s_lshl_b32 s1, s15, 8
+; GFX7-HSA-NEXT:    s_or_b32 s15, s0, s1
 ; GFX7-HSA-NEXT:    s_and_b32 s0, s2, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s1, s18, 8
-; GFX7-HSA-NEXT:    v_and_b32_e32 v11, 0xff00ff, v0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s4
-; GFX7-HSA-NEXT:    s_and_b32 s14, s4, 0xff00
-; GFX7-HSA-NEXT:    s_or_b32 s2, s0, s1
+; GFX7-HSA-NEXT:    s_lshl_b32 s1, s14, 8
+; GFX7-HSA-NEXT:    s_or_b32 s14, s0, s1
+; GFX7-HSA-NEXT:    s_lshr_b32 s1, s3, 8
+; GFX7-HSA-NEXT:    s_lshr_b32 s0, s3, 16
+; GFX7-HSA-NEXT:    s_and_b32 s1, s1, 0xff0000
+; GFX7-HSA-NEXT:    s_or_b32 s0, s1, s0
+; GFX7-HSA-NEXT:    s_lshr_b32 s1, s2, 8
+; GFX7-HSA-NEXT:    s_and_b32 s3, s0, 0xff00ff
+; GFX7-HSA-NEXT:    s_lshr_b32 s0, s2, 16
+; GFX7-HSA-NEXT:    s_and_b32 s1, s1, 0xff0000
+; GFX7-HSA-NEXT:    s_and_b32 s13, s5, 0xff00
+; GFX7-HSA-NEXT:    s_or_b32 s0, s1, s0
+; GFX7-HSA-NEXT:    s_and_b32 s12, s4, 0xff00
+; GFX7-HSA-NEXT:    s_and_b32 s2, s0, 0xff00ff
 ; GFX7-HSA-NEXT:    s_and_b32 s0, s5, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s1, s16, 8
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s15, v0, 16
-; GFX7-HSA-NEXT:    s_and_b32 s12, s7, 0xff00
-; GFX7-HSA-NEXT:    s_lshr_b32 s13, s7, 24
-; GFX7-HSA-NEXT:    s_or_b32 s5, s0, s1
-; GFX7-HSA-NEXT:    v_and_b32_e32 v9, 0xff00ff, v0
+; GFX7-HSA-NEXT:    s_lshl_b32 s1, s13, 8
+; GFX7-HSA-NEXT:    s_or_b32 s13, s0, s1
 ; GFX7-HSA-NEXT:    s_and_b32 s0, s4, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s1, s14, 8
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s7
+; GFX7-HSA-NEXT:    s_lshl_b32 s1, s12, 8
+; GFX7-HSA-NEXT:    s_or_b32 s12, s0, s1
+; GFX7-HSA-NEXT:    s_lshr_b32 s1, s5, 8
+; GFX7-HSA-NEXT:    s_lshr_b32 s0, s5, 16
+; GFX7-HSA-NEXT:    s_and_b32 s1, s1, 0xff0000
+; GFX7-HSA-NEXT:    s_or_b32 s0, s1, s0
+; GFX7-HSA-NEXT:    s_lshr_b32 s1, s4, 8
+; GFX7-HSA-NEXT:    s_and_b32 s5, s0, 0xff00ff
+; GFX7-HSA-NEXT:    s_lshr_b32 s0, s4, 16
+; GFX7-HSA-NEXT:    s_and_b32 s1, s1, 0xff0000
+; GFX7-HSA-NEXT:    s_and_b32 s11, s7, 0xff00
+; GFX7-HSA-NEXT:    s_or_b32 s0, s1, s0
 ; GFX7-HSA-NEXT:    s_and_b32 s10, s6, 0xff00
-; GFX7-HSA-NEXT:    s_or_b32 s4, s0, s1
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s13, v0, 16
+; GFX7-HSA-NEXT:    s_and_b32 s4, s0, 0xff00ff
 ; GFX7-HSA-NEXT:    s_and_b32 s0, s7, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s1, s12, 8
-; GFX7-HSA-NEXT:    s_lshr_b32 s11, s6, 24
-; GFX7-HSA-NEXT:    v_and_b32_e32 v15, 0xff00ff, v0
+; GFX7-HSA-NEXT:    s_lshl_b32 s1, s11, 8
 ; GFX7-HSA-NEXT:    s_or_b32 s0, s0, s1
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX7-HSA-NEXT:    s_and_b32 s1, s6, 0xff
-; GFX7-HSA-NEXT:    s_lshl_b32 s6, s10, 8
-; GFX7-HSA-NEXT:    s_or_b32 s1, s1, s6
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v14, s0
+; GFX7-HSA-NEXT:    s_lshl_b32 s10, s10, 8
+; GFX7-HSA-NEXT:    s_or_b32 s1, s1, s10
+; GFX7-HSA-NEXT:    s_lshr_b32 s10, s7, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s7, s7, 8
+; GFX7-HSA-NEXT:    s_and_b32 s7, s7, 0xff0000
+; GFX7-HSA-NEXT:    s_or_b32 s7, s7, s10
+; GFX7-HSA-NEXT:    s_lshr_b32 s10, s6, 16
+; GFX7-HSA-NEXT:    s_lshr_b32 s6, s6, 8
+; GFX7-HSA-NEXT:    s_and_b32 s6, s6, 0xff0000
+; GFX7-HSA-NEXT:    s_or_b32 s6, s6, s10
+; GFX7-HSA-NEXT:    s_and_b32 s7, s7, 0xff00ff
+; GFX7-HSA-NEXT:    s_and_b32 s6, s6, 0xff00ff
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX7-HSA-NEXT:    s_add_u32 s0, s8, 48
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v12, s1
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX7-HSA-NEXT:    s_addc_u32 s1, s9, 0
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v17, s1
-; GFX7-HSA-NEXT:    v_alignbit_b32 v0, s11, v0, 16
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v16, s0
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX7-HSA-NEXT:    s_add_u32 s0, s8, 32
-; GFX7-HSA-NEXT:    v_and_b32_e32 v13, 0xff00ff, v0
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v1, s6
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v3, s7
 ; GFX7-HSA-NEXT:    s_addc_u32 s1, s9, 0
-; GFX7-HSA-NEXT:    flat_store_dwordx4 v[16:17], v[12:15]
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v8, s4
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v13, s1
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v12, s0
+; GFX7-HSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX7-HSA-NEXT:    s_add_u32 s0, s8, 16
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v10, s5
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v1, s4
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v3, s5
 ; GFX7-HSA-NEXT:    s_addc_u32 s1, s9, 0
-; GFX7-HSA-NEXT:    flat_store_dwordx4 v[12:13], v[8:11]
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s2
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v9, s1
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v6, s3
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v8, s0
-; GFX7-HSA-NEXT:    flat_store_dwordx4 v[8:9], v[4:7]
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s22
+; GFX7-HSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v1, s2
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v4, s8
-; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s24
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v2, s17
+; GFX7-HSA-NEXT:    v_mov_b32_e32 v3, s18
 ; GFX7-HSA-NEXT:    v_mov_b32_e32 v5, s9
 ; GFX7-HSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; GFX7-HSA-NEXT:    s_endpgm
 ;
 ; GFX8-NOHSA-LABEL: constant_zextload_v32i8_to_v32i16:
 ; GFX8-NOHSA:       ; %bb.0:
 ; GFX8-NOHSA-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x24
 ; GFX8-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NOHSA-NEXT:    s_load_dwordx8 s[0:7], s[10:11], 0x0
 ; GFX8-NOHSA-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s14, s1, 24
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v0, 8, s0
-; GFX8-NOHSA-NEXT:    s_lshl_b32 s14, s14, 16
-; GFX8-NOHSA-NEXT:    s_bfe_u32 s15, s1, 0x80010
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s13, s0, 24
-; GFX8-NOHSA-NEXT:    s_or_b32 s14, s15, s14
-; GFX8-NOHSA-NEXT:    s_and_b32 s15, s1, 0xff
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s10, s1, 24
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s11, s1, 0x80010
+; GFX8-NOHSA-NEXT:    s_and_b32 s12, s1, 0xff
 ; GFX8-NOHSA-NEXT:    s_lshl_b32 s1, s1, 8
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v1, s0
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v0, 8, s0
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s10, s10, 16
+; GFX8-NOHSA-NEXT:    s_and_b32 s1, s1, 0xff0000
+; GFX8-NOHSA-NEXT:    s_or_b32 s10, s11, s10
+; GFX8-NOHSA-NEXT:    s_or_b32 s11, s12, s1
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s1, s0, 24
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s12, s0, 0x80010
 ; GFX8-NOHSA-NEXT:    s_and_b32 s0, s0, 0xff
 ; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NOHSA-NEXT:    s_and_b32 s1, s1, 0xff0000
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s1, s1, 16
 ; GFX8-NOHSA-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX8-NOHSA-NEXT:    s_lshr_b32 s0, s3, 24
-; GFX8-NOHSA-NEXT:    s_or_b32 s15, s15, s1
+; GFX8-NOHSA-NEXT:    s_or_b32 s12, s12, s1
 ; GFX8-NOHSA-NEXT:    s_lshl_b32 s0, s0, 16
 ; GFX8-NOHSA-NEXT:    s_bfe_u32 s1, s3, 0x80010
-; GFX8-NOHSA-NEXT:    v_alignbit_b32 v1, s13, v1, 16
 ; GFX8-NOHSA-NEXT:    s_or_b32 s13, s1, s0
 ; GFX8-NOHSA-NEXT:    s_lshl_b32 s1, s3, 8
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v2, 8, s2
 ; GFX8-NOHSA-NEXT:    s_and_b32 s0, s3, 0xff
 ; GFX8-NOHSA-NEXT:    s_and_b32 s1, s1, 0xff0000
 ; GFX8-NOHSA-NEXT:    s_or_b32 s3, s0, s1
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s0, s2, 24
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v1, 8, s2
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s1, s2, 0x80010
+; GFX8-NOHSA-NEXT:    s_or_b32 s14, s1, s0
 ; GFX8-NOHSA-NEXT:    s_and_b32 s0, s2, 0xff
-; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NOHSA-NEXT:    v_or_b32_e32 v2, s0, v2
+; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NOHSA-NEXT:    v_or_b32_e32 v1, s0, v1
 ; GFX8-NOHSA-NEXT:    s_lshr_b32 s0, s5, 24
 ; GFX8-NOHSA-NEXT:    s_lshl_b32 s0, s0, 16
 ; GFX8-NOHSA-NEXT:    s_bfe_u32 s1, s5, 0x80010
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s12, s2, 24
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX8-NOHSA-NEXT:    s_or_b32 s2, s1, s0
 ; GFX8-NOHSA-NEXT:    s_lshl_b32 s1, s5, 8
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v4, 8, s4
 ; GFX8-NOHSA-NEXT:    s_and_b32 s0, s5, 0xff
 ; GFX8-NOHSA-NEXT:    s_and_b32 s1, s1, 0xff0000
 ; GFX8-NOHSA-NEXT:    s_or_b32 s5, s0, s1
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s0, s4, 24
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v2, 8, s4
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s1, s4, 0x80010
+; GFX8-NOHSA-NEXT:    s_or_b32 s15, s1, s0
 ; GFX8-NOHSA-NEXT:    s_and_b32 s0, s4, 0xff
-; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX8-NOHSA-NEXT:    v_or_b32_e32 v4, s0, v4
+; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NOHSA-NEXT:    v_or_b32_e32 v2, s0, v2
 ; GFX8-NOHSA-NEXT:    s_lshr_b32 s0, s7, 24
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s11, s4, 24
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s4
 ; GFX8-NOHSA-NEXT:    s_lshl_b32 s0, s0, 16
 ; GFX8-NOHSA-NEXT:    s_bfe_u32 s1, s7, 0x80010
 ; GFX8-NOHSA-NEXT:    s_lshl_b32 s4, s7, 8
 ; GFX8-NOHSA-NEXT:    s_or_b32 s0, s1, s0
 ; GFX8-NOHSA-NEXT:    s_and_b32 s1, s7, 0xff
 ; GFX8-NOHSA-NEXT:    s_and_b32 s4, s4, 0xff0000
-; GFX8-NOHSA-NEXT:    s_lshr_b32 s10, s6, 24
 ; GFX8-NOHSA-NEXT:    s_or_b32 s1, s1, s4
-; GFX8-NOHSA-NEXT:    s_and_b32 s4, s6, 0xff
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v9, s0
+; GFX8-NOHSA-NEXT:    s_lshr_b32 s4, s6, 24
+; GFX8-NOHSA-NEXT:    s_lshl_b32 s4, s4, 16
+; GFX8-NOHSA-NEXT:    s_bfe_u32 s7, s6, 0x80010
+; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v3, 8, s6
+; GFX8-NOHSA-NEXT:    s_or_b32 s4, s7, s4
+; GFX8-NOHSA-NEXT:    s_and_b32 s6, s6, 0xff
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v6, s0
 ; GFX8-NOHSA-NEXT:    s_add_u32 s0, s8, 48
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v8, s1
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s1
 ; GFX8-NOHSA-NEXT:    s_addc_u32 s1, s9, 0
-; GFX8-NOHSA-NEXT:    v_lshrrev_b16_e64 v6, 8, s6
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v7, s6
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v11, s1
-; GFX8-NOHSA-NEXT:    v_alignbit_b32 v7, s10, v7, 16
-; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v10, s0
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v8, s1
+; GFX8-NOHSA-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v7, s0
 ; GFX8-NOHSA-NEXT:    s_add_u32 s0, s8, 32
-; GFX8-NOHSA-NEXT:    v_and_b32_e32 v7, 0xff00ff, v7
-; GFX8-NOHSA-NEXT:    v_or_b32_e32 v6, s4, v6
-; GFX8-NOHSA-NEXT:    s_addc_u32 s1, s9, 0
-; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[10:11], v[6:9]
-; GFX8-NOHSA-NEXT:    v_alignbit_b32 v5, s11, v5, 16
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v9, s1
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v8, s0
-; GFX8-NOHSA-NEXT:    s_add_u32 s0, s8, 16
-; GFX8-NOHSA-NEXT:    v_and_b32_e32 v5, 0xff00ff, v5
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v6, s5
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v7, s2
+; GFX8-NOHSA-NEXT:    v_or_b32_e32 v3, s6, v3
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s4
 ; GFX8-NOHSA-NEXT:    s_addc_u32 s1, s9, 0
-; GFX8-NOHSA-NEXT:    v_alignbit_b32 v3, s12, v3, 16
-; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[8:9], v[4:7]
-; GFX8-NOHSA-NEXT:    v_and_b32_e32 v3, 0xff00ff, v3
+; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[7:8], v[3:6]
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v7, s1
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s3
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s13
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v6, s0
+; GFX8-NOHSA-NEXT:    s_add_u32 s0, s8, 16
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s15
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s5
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s2
+; GFX8-NOHSA-NEXT:    s_addc_u32 s1, s9, 0
 ; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[6:7], v[2:5]
-; GFX8-NOHSA-NEXT:    v_and_b32_e32 v1, 0xff00ff, v1
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v6, s1
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v2, s14
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s13
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s0
+; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[5:6], v[1:4]
+; GFX8-NOHSA-NEXT:    s_nop 0
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v4, s8
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v2, s15
-; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s14
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v1, s12
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v2, s11
+; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v3, s10
 ; GFX8-NOHSA-NEXT:    v_mov_b32_e32 v5, s9
 ; GFX8-NOHSA-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; GFX8-NOHSA-NEXT:    s_endpgm
 ;
 ; EG-LABEL: constant_zextload_v32i8_to_v32i16:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 1, @14, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 1 @10

llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll

 ; SI-NEXT:    s_mov_b32 s10, s6
 ; SI-NEXT:    s_mov_b32 s11, s7
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_mov_b32 s8, s2
 ; SI-NEXT:    s_mov_b32 s9, s3
 ; SI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
 ; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; SI-NEXT:    s_mov_b32 s4, s0
 ; SI-NEXT:    s_mov_b32 s5, s1
 ; SI-NEXT:    v_mov_b32_e32 v1, v0
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: scalar_to_vector_v2i32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s7, 0xf000
 ; VI-NEXT:    s_mov_b32 s6, -1
 ; VI-NEXT:    s_mov_b32 s10, s6
 ; VI-NEXT:    s_mov_b32 s11, s7
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_mov_b32 s8, s2
 ; VI-NEXT:    s_mov_b32 s9, s3
 ; VI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; VI-NEXT:    s_mov_b32 s4, s0
 ; VI-NEXT:    s_mov_b32 s5, s1
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v0
+; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; VI-NEXT:    v_mov_b32_e32 v1, v0
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
   %tmp1 = load i32, ptr addrspace(1) %in, align 4
   %bc = bitcast i32 %tmp1 to <2 x i16>
   %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   store <4 x i16> %tmp2, ptr addrspace(1) %out, align 8
   ret void
 }
 
 define amdgpu_kernel void @scalar_to_vector_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {
 ; SI-LABEL: scalar_to_vector_v2f32:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_mov_b32 s10, s6
 ; SI-NEXT:    s_mov_b32 s11, s7
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
 ; SI-NEXT:    s_mov_b32 s8, s2
 ; SI-NEXT:    s_mov_b32 s9, s3
 ; SI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
 ; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0
+; SI-NEXT:    v_or_b32_e32 v0, v0, v1
 ; SI-NEXT:    s_mov_b32 s4, s0
 ; SI-NEXT:    s_mov_b32 s5, s1
 ; SI-NEXT:    v_mov_b32_e32 v1, v0
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: scalar_to_vector_v2f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    s_mov_b32 s7, 0xf000
 ; VI-NEXT:    s_mov_b32 s6, -1
 ; VI-NEXT:    s_mov_b32 s10, s6
 ; VI-NEXT:    s_mov_b32 s11, s7
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    s_mov_b32 s8, s2
 ; VI-NEXT:    s_mov_b32 s9, s3
 ; VI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; VI-NEXT:    s_mov_b32 s4, s0
 ; VI-NEXT:    s_mov_b32 s5, s1
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT:    v_alignbit_b32 v0, v1, v0, 16
+; VI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v0
+; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; VI-NEXT:    v_mov_b32_e32 v1, v0
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
   %tmp1 = load float, ptr addrspace(1) %in, align 4
   %bc = bitcast float %tmp1 to <2 x i16>
   %tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   store <4 x i16> %tmp2, ptr addrspace(1) %out, align 8
   ret void

llvm/test/CodeGen/AMDGPU/shl.ll

 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: shl_i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6
-; EG-NEXT:    ALU 12, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 18, @9, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 8:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 9:
-; EG-NEXT:     AND_INT T1.Y, T0.Z, literal.x,
-; EG-NEXT:     LSHR T1.Z, T0.Y, 1,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1,
+; EG-NEXT:     LSHL T1.Z, T0.Y, literal.x,
+; EG-NEXT:     LSHR T0.W, T0.X, 1,
 ; EG-NEXT:     NOT_INT * T1.W, T0.Z,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T1.Z, PV.Z, PV.W, PS,
-; EG-NEXT:     LSHL T0.W, T0.X, PV.Y,
+; EG-NEXT:     AND_INT T0.Y, T0.Y, literal.x,
+; EG-NEXT:     AND_INT T2.Z, T0.Z, literal.y,
+; EG-NEXT:     AND_INT T1.W, PS, literal.y,
+; EG-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
+; EG-NEXT:    -2(nan), 31(4.344025e-44)
+; EG-NEXT:     LSHR T0.W, PS, PV.W,
+; EG-NEXT:     LSHL * T1.W, PV.Y, PV.Z,
+; EG-NEXT:     OR_INT T1.Z, PS, PV.W,
+; EG-NEXT:     LSHL T0.W, T0.X, T2.Z,
 ; EG-NEXT:     AND_INT * T1.W, T0.Z, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.Z, PV.W,
 ; EG-NEXT:     CNDE_INT T0.X, T1.W, T0.W, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 1
   %a = load i64, ptr addrspace(1) %in

 ; VI-NEXT:    v_mov_b32_e32 v3, s3
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: shl_v2i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @10, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 1 @6
-; EG-NEXT:    ALU 22, @11, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1
+; EG-NEXT:    ALU 35, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
-; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 16, #1
-; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 0, #1
+; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 16, #1
 ; EG-NEXT:    ALU clause starting at 10:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 11:
-; EG-NEXT:     AND_INT T1.Y, T1.Z, literal.x,
-; EG-NEXT:     LSHR T2.Z, T0.W, 1,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.W, T0.Z, 1,
-; EG-NEXT:     NOT_INT * T1.W, T1.Z,
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T0.W, PV.Z, PV.W, PS,
-; EG-NEXT:     LSHL * T1.W, T0.Z, PV.Y,
-; EG-NEXT:     AND_INT T2.X, T1.Z, literal.x,
-; EG-NEXT:     AND_INT T1.Y, T1.X, literal.y,
-; EG-NEXT:     LSHR T0.Z, T0.Y, 1,
-; EG-NEXT:     BIT_ALIGN_INT T2.W, T0.Y, T0.X, 1,
-; EG-NEXT:     NOT_INT * T3.W, T1.X,
-; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
-; EG-NEXT:     BIT_ALIGN_INT T0.Y, PV.Z, PV.W, PS,
-; EG-NEXT:     LSHL T0.Z, T0.X, PV.Y,
-; EG-NEXT:     AND_INT T2.W, T1.X, literal.x, BS:VEC_120/SCL_212
-; EG-NEXT:     CNDE_INT * T3.W, PV.X, T0.W, T1.W,
+; EG-NEXT:     AND_INT * T0.W, T1.Y, literal.x,
+; EG-NEXT:    -2(nan), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T2.X, T1.W, literal.x,
+; EG-NEXT:     AND_INT T0.Y, T0.Z, literal.y,
+; EG-NEXT:     LSHL T2.Z, T1.W, literal.y,
+; EG-NEXT:     LSHR T1.W, T1.Z, 1, BS:VEC_120/SCL_212
+; EG-NEXT:     NOT_INT * T2.W, T0.Z,
+; EG-NEXT:    -2(nan), 31(4.344025e-44)
+; EG-NEXT:     AND_INT T3.X, PS, literal.x,
+; EG-NEXT:     OR_INT T2.Y, PV.Z, PV.W,
+; EG-NEXT:     LSHL T2.Z, T1.Y, literal.x,
+; EG-NEXT:     LSHR T1.W, T1.X, 1,
+; EG-NEXT:     NOT_INT * T2.W, T0.X,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T4.X, T0.X, literal.x,
+; EG-NEXT:     AND_INT T1.Y, PS, literal.x,
+; EG-NEXT:     OR_INT T2.Z, PV.Z, PV.W,
+; EG-NEXT:     LSHR T1.W, PV.Y, PV.X,
+; EG-NEXT:     LSHL * T2.W, T2.X, T0.Y,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     OR_INT T2.X, PS, PV.W,
+; EG-NEXT:     LSHL T0.Y, T1.Z, T0.Y,
+; EG-NEXT:     AND_INT T0.Z, T0.Z, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT:     LSHR T1.W, PV.Z, PV.Y,
+; EG-NEXT:     LSHL * T0.W, T0.W, PV.X,
+; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     OR_INT T1.Y, PS, PV.W,
+; EG-NEXT:     LSHL T1.Z, T1.X, T4.X,
+; EG-NEXT:     AND_INT T0.W, T0.X, literal.x, BS:VEC_201
+; EG-NEXT:     CNDE_INT * T2.W, PV.Z, PV.X, PV.Y,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T3.Y, PV.W, PV.Y, PV.Z,
-; EG-NEXT:     CNDE_INT * T3.Z, T2.X, T1.W, 0.0,
-; EG-NEXT:     CNDE_INT T3.X, T2.W, T0.Z, 0.0,
+; EG-NEXT:     CNDE_INT T2.Y, PV.W, PV.Y, PV.Z,
+; EG-NEXT:     CNDE_INT * T2.Z, T0.Z, T0.Y, 0.0,
+; EG-NEXT:     CNDE_INT T2.X, T0.W, T1.Z, 0.0,
 ; EG-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %in, i64 1
   %a = load <2 x i64>, ptr addrspace(1) %in
   %b = load <2 x i64>, ptr addrspace(1) %b_ptr
   %result = shl <2 x i64> %a, %b
   store <2 x i64> %result, ptr addrspace(1) %out
   ret void

 ; VI-NEXT:    v_mov_b32_e32 v3, s3
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[16:19], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: shl_v4i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @14, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 3 @6
-; EG-NEXT:    ALU 47, @15, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1
+; EG-NEXT:    ALU 72, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T2.X, 0
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    Fetch clause starting at 6:
-; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 48, #1
-; EG-NEXT:     VTX_READ_128 T2.XYZW, T0.X, 0, #1
-; EG-NEXT:     VTX_READ_128 T3.XYZW, T0.X, 32, #1
-; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 16, #1
+; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 0, #1
+; EG-NEXT:     VTX_READ_128 T2.XYZW, T0.X, 48, #1
+; EG-NEXT:     VTX_READ_128 T3.XYZW, T0.X, 16, #1
+; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 32, #1
 ; EG-NEXT:    ALU clause starting at 14:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 15:
-; EG-NEXT:     AND_INT T4.Z, T1.Z, literal.x,
-; EG-NEXT:     LSHR T1.W, T0.W, 1,
-; EG-NEXT:     NOT_INT * T3.W, T1.Z,
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T4.X, T0.W, T0.Z, 1,
-; EG-NEXT:     AND_INT T1.Y, T3.Z, literal.x, BS:VEC_201
-; EG-NEXT:     LSHR T5.Z, T2.W, 1, BS:VEC_120/SCL_212
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T2.W, T2.Z, 1, BS:VEC_102/SCL_221
-; EG-NEXT:     NOT_INT * T2.W, T3.Z,
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T3.Y, PV.Z, PV.W, PS,
-; EG-NEXT:     LSHL T2.Z, T2.Z, PV.Y,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T1.W, PV.X, T3.W,
-; EG-NEXT:     LSHL * T1.W, T0.Z, T4.Z,
-; EG-NEXT:     AND_INT T4.X, T1.Z, literal.x,
-; EG-NEXT:     AND_INT T1.Y, T1.X, literal.y,
-; EG-NEXT:     LSHR T0.Z, T0.Y, 1,
-; EG-NEXT:     BIT_ALIGN_INT T2.W, T0.Y, T0.X, 1,
-; EG-NEXT:     NOT_INT * T3.W, T1.X,
+; EG-NEXT:     LSHL T4.Z, T1.W, literal.x,
+; EG-NEXT:     LSHR T0.W, T1.Z, 1,
+; EG-NEXT:     NOT_INT * T2.W, T0.Z,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT T0.Y, T1.W, literal.x,
+; EG-NEXT:     AND_INT T5.Z, T0.Z, literal.y,
+; EG-NEXT:     AND_INT T1.W, PS, literal.y,
+; EG-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
+; EG-NEXT:    -2(nan), 31(4.344025e-44)
+; EG-NEXT:     LSHL T4.X, T3.W, literal.x,
+; EG-NEXT:     LSHR T2.Y, T3.Z, 1,
+; EG-NEXT:     NOT_INT T4.Z, T2.Z, BS:VEC_120/SCL_212
+; EG-NEXT:     LSHR T0.W, PS, PV.W,
+; EG-NEXT:     LSHL * T1.W, PV.Y, PV.Z,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     OR_INT T5.X, PS, PV.W,
+; EG-NEXT:     AND_INT T0.Y, T3.W, literal.x,
+; EG-NEXT:     AND_INT T6.Z, T2.Z, literal.y,
+; EG-NEXT:     AND_INT T0.W, PV.Z, literal.y,
+; EG-NEXT:     OR_INT * T1.W, PV.X, PV.Y,
+; EG-NEXT:    -2(nan), 31(4.344025e-44)
+; EG-NEXT:     AND_INT T4.X, T1.Y, literal.x,
+; EG-NEXT:     AND_INT T2.Y, T0.X, literal.y,
+; EG-NEXT:     LSHR T4.Z, PS, PV.W,
+; EG-NEXT:     LSHL T0.W, PV.Y, PV.Z,
+; EG-NEXT:     NOT_INT * T1.W, T0.X,
+; EG-NEXT:    -2(nan), 31(4.344025e-44)
+; EG-NEXT:     AND_INT T6.X, PS, literal.x,
+; EG-NEXT:     OR_INT T0.Y, PV.W, PV.Z,
+; EG-NEXT:     LSHL T4.Z, T3.Y, literal.x,
+; EG-NEXT:     LSHR T0.W, T3.X, 1,
+; EG-NEXT:     NOT_INT * T1.W, T2.X,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T7.X, T3.Z, T6.Z,
+; EG-NEXT:     AND_INT T3.Y, T3.Y, literal.x,
+; EG-NEXT:     AND_INT T3.Z, T2.X, literal.y,
+; EG-NEXT:     AND_INT T1.W, PS, literal.y,
+; EG-NEXT:     OR_INT * T0.W, PV.Z, PV.W,
+; EG-NEXT:    -2(nan), 31(4.344025e-44)
+; EG-NEXT:     AND_INT T8.X, T2.Z, literal.x,
+; EG-NEXT:     LSHR T4.Y, PS, PV.W,
+; EG-NEXT:     LSHL T2.Z, PV.Y, PV.Z,
+; EG-NEXT:     LSHL T0.W, T1.Y, literal.y,
+; EG-NEXT:     LSHR * T1.W, T1.X, 1,
 ; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
-; EG-NEXT:     AND_INT T5.X, T3.Z, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T0.Y, PV.Z, PV.W, PS,
-; EG-NEXT:     LSHL T0.Z, T0.X, PV.Y,
-; EG-NEXT:     AND_INT T2.W, T1.X, literal.x, BS:VEC_120/SCL_212
-; EG-NEXT:     CNDE_INT * T4.W, PV.X, T0.W, T1.W,
+; EG-NEXT:     OR_INT T9.X, PV.W, PS,
+; EG-NEXT:     OR_INT T1.Y, PV.Z, PV.Y,
+; EG-NEXT:     LSHL T2.Z, T3.X, T3.Z, BS:VEC_120/SCL_212
+; EG-NEXT:     AND_INT T0.W, T2.X, literal.x, BS:VEC_201
+; EG-NEXT:     CNDE_INT * T1.W, PV.X, T0.Y, T7.X,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T0.X, T3.X, literal.x,
-; EG-NEXT:     CNDE_INT T4.Y, PV.W, PV.Y, PV.Z,
-; EG-NEXT:     LSHR T1.Z, T2.Y, 1,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T2.Y, T2.X, 1,
-; EG-NEXT:     NOT_INT * T3.W, T3.X,
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T1.X, PV.Z, PV.W, PS,
-; EG-NEXT:     LSHL T0.Y, T2.X, PV.X,
-; EG-NEXT:     CNDE_INT T4.Z, T4.X, T1.W, 0.0, BS:VEC_120/SCL_212
-; EG-NEXT:     AND_INT * T0.W, T3.X, literal.x, BS:VEC_201
+; EG-NEXT:     LSHL T2.X, T1.Z, T5.Z,
+; EG-NEXT:     CNDE_INT T1.Y, PV.W, PV.Y, PV.Z,
+; EG-NEXT:     AND_INT T0.Z, T0.Z, literal.x, BS:VEC_201
+; EG-NEXT:     LSHR T2.W, PV.X, T6.X,
+; EG-NEXT:     LSHL * T3.W, T4.X, T2.Y,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT * T1.W, T5.X, T3.Y, T2.Z,
-; EG-NEXT:     CNDE_INT T4.X, T2.W, T0.Z, 0.0,
-; EG-NEXT:     CNDE_INT T1.Y, T0.W, T1.X, T0.Y, BS:VEC_120/SCL_212
-; EG-NEXT:     ADD_INT * T2.W, KC0[2].Y, literal.x,
+; EG-NEXT:     OR_INT T3.X, PS, PV.W,
+; EG-NEXT:     LSHL T0.Y, T1.X, T2.Y,
+; EG-NEXT:     CNDE_INT * T1.Z, T8.X, T7.X, 0.0, BS:VEC_120/SCL_212
+; EG-NEXT:     AND_INT T2.W, T0.X, literal.x, BS:VEC_201
+; EG-NEXT:     CNDE_INT * T3.W, T0.Z, T5.X, T2.X,
+; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     CNDE_INT T1.X, T0.W, T2.Z, 0.0,
+; EG-NEXT:     CNDE_INT T3.Y, PV.W, T3.X, T0.Y,
+; EG-NEXT:     ADD_INT * T0.W, KC0[2].Y, literal.x,
 ; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
 ; EG-NEXT:     LSHR T0.X, PV.W, literal.x,
-; EG-NEXT:     CNDE_INT T1.Z, T5.X, T2.Z, 0.0,
-; EG-NEXT:     CNDE_INT * T1.X, T0.W, T0.Y, 0.0,
+; EG-NEXT:     CNDE_INT T3.Z, T0.Z, T2.X, 0.0,
+; EG-NEXT:     CNDE_INT * T3.X, T2.W, T0.Y, 0.0,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ; EG-NEXT:     LSHR * T2.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %in, i64 1
   %a = load <4 x i64>, ptr addrspace(1) %in
   %b = load <4 x i64>, ptr addrspace(1) %b_ptr
   %result = shl <4 x i64> %a, %b
   store <4 x i64> %result, ptr addrspace(1) %out

 ; VI-NEXT:    s_lshl_b64 s[0:1], s[8:9], s2
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_constant_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 15, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     AND_INT T0.Z, KC0[2].W, literal.x,
-; EG-NEXT:     MOV T0.W, literal.y,
-; EG-NEXT:     NOT_INT * T1.W, KC0[2].W,
-; EG-NEXT:    31(4.344025e-44), -1(nan)
-; EG-NEXT:     BIT_ALIGN_INT T1.Z, literal.x, PV.W, PS,
-; EG-NEXT:     LSHL T0.W, literal.y, PV.Z,
-; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.z,
-; EG-NEXT:    32767(4.591635e-41), -1(nan)
-; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     NOT_INT T0.W, KC0[2].W,
+; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHR T0.W, literal.x, PV.W,
+; EG-NEXT:     LSHL * T2.W, literal.y, T1.W,
+; EG-NEXT:    -1(nan), 65534(9.183269e-41)
+; EG-NEXT:     OR_INT T0.Z, PS, PV.W,
+; EG-NEXT:     LSHL T0.W, literal.x, T1.W,
+; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
+; EG-NEXT:    -1(nan), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.Z, PV.W,
 ; EG-NEXT:     CNDE_INT T0.X, T1.W, T0.W, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 281474976710655, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: v_shl_constant_i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6
-; EG-NEXT:    ALU 12, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 15, @9, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 8:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 9:
-; EG-NEXT:     NOT_INT T0.Z, T0.X,
-; EG-NEXT:     MOV T0.W, literal.x,
-; EG-NEXT:     AND_INT * T1.W, T0.X, literal.y,
-; EG-NEXT:    1435293955(1.935796e+13), 31(4.344025e-44)
-; EG-NEXT:     LSHL T1.Z, literal.x, PS,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.y, PV.W, PV.Z,
-; EG-NEXT:     AND_INT * T1.W, T0.X, literal.z,
-; EG-NEXT:    -1424379385(-5.460358e-13), 143(2.003857e-43)
-; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, PV.Z,
-; EG-NEXT:     CNDE_INT T0.X, T1.W, T1.Z, 0.0,
+; EG-NEXT:     NOT_INT T0.W, T0.X,
+; EG-NEXT:     AND_INT * T1.W, T0.X, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHR T0.W, literal.x, PV.W,
+; EG-NEXT:     LSHL * T2.W, literal.y, T1.W,
+; EG-NEXT:    1435293955(1.935796e+13), 286(4.007714e-43)
+; EG-NEXT:     OR_INT T0.Z, PS, PV.W,
+; EG-NEXT:     AND_INT T0.W, T0.X, literal.x,
+; EG-NEXT:     LSHL * T1.W, literal.y, T1.W,
+; EG-NEXT:    32(4.484155e-44), -1424379385(-5.460358e-13)
+; EG-NEXT:     CNDE_INT * T0.Y, PV.W, PV.Z, PS,
+; EG-NEXT:     CNDE_INT T0.X, T0.W, T1.W, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %a = load i64, ptr addrspace(1) %aptr, align 8
   %shl = shl i64 1231231234567, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }
 

 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: v_shl_i64_32_bit_constant:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6
-; EG-NEXT:    ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 13, @9, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 8:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 9:
-; EG-NEXT:     AND_INT T0.W, T0.X, literal.x,
-; EG-NEXT:     NOT_INT * T1.W, T0.X,
+; EG-NEXT:     NOT_INT T0.W, T0.X,
+; EG-NEXT:     AND_INT * T1.W, T0.X, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT * T0.W, PV.W, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,
-; EG-NEXT:     LSHL T0.W, literal.y, PV.W,
+; EG-NEXT:     LSHR T0.Z, literal.x, PV.W,
+; EG-NEXT:     LSHL T0.W, literal.y, T1.W,
 ; EG-NEXT:     AND_INT * T1.W, T0.X, literal.z,
 ; EG-NEXT:    617283(8.649977e-40), 1234567(1.729997e-39)
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.Z, PV.W,
 ; EG-NEXT:     CNDE_INT T0.X, T1.W, T0.W, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %a = load i64, ptr addrspace(1) %aptr, align 8

 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: v_shl_inline_imm_64_i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6
-; EG-NEXT:    ALU 10, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 12, @9, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_32 T0.X, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 8:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 9:
-; EG-NEXT:     AND_INT T0.W, T0.X, literal.x,
-; EG-NEXT:     NOT_INT * T1.W, T0.X,
+; EG-NEXT:     NOT_INT T0.W, T0.X,
+; EG-NEXT:     AND_INT * T1.W, T0.X, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,
-; EG-NEXT:     LSHL T0.W, literal.y, PV.W,
+; EG-NEXT:     AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHR T0.Z, literal.x, PV.W,
+; EG-NEXT:     LSHL T0.W, literal.y, T1.W,
 ; EG-NEXT:     AND_INT * T1.W, T0.X, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 64(8.968310e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.Z, PV.W,
 ; EG-NEXT:     CNDE_INT T0.X, T1.W, T0.W, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %a = load i64, ptr addrspace(1) %aptr, align 8
   %shl = shl i64 64, %a

 ; VI-NEXT:    s_lshl_b64 s[4:5], 64, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_64_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 10, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 11, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT T0.W, KC0[2].W,
+; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
+; EG-NEXT:     AND_INT T0.W, PV.W, literal.x,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     LSHL T0.Z, literal.x, PS,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, literal.y, PV.W,
+; EG-NEXT:     LSHR T0.W, literal.y, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
 ; EG-NEXT:    64(8.968310e-44), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, PV.Z,
 ; EG-NEXT:     CNDE_INT T0.X, T1.W, T0.Z, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 64, %a
   store i64 %shl, ptr addrspace(1) %out, align 8

 ; VI-NEXT:    s_lshl_b64 s[4:5], 1.0, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_1_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    536346624(1.050321e-19), 32(4.484155e-44)
+; EG-NEXT:    1072693248(1.875000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 4607182418800017408, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[4:5], -1.0, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_neg_1_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    1610088448(3.574057e+19), 32(4.484155e-44)
+; EG-NEXT:    -1074790400(-1.875000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 13830554455654793216, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[4:5], 0.5, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_0_5_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    535822336(1.016440e-19), 32(4.484155e-44)
+; EG-NEXT:    1071644672(1.750000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 4602678819172646912, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[4:5], -0.5, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_neg_0_5_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    1609564160(3.458765e+19), 32(4.484155e-44)
+; EG-NEXT:    -1075838976(-1.750000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 13826050856027422720, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[4:5], 2.0, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_2_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    536870912(1.084202e-19), 32(4.484155e-44)
+; EG-NEXT:    1073741824(2.000000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 4611686018427387904, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[4:5], -2.0, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_neg_2_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    1610612736(3.689349e+19), 32(4.484155e-44)
+; EG-NEXT:    -1073741824(-2.000000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 13835058055282163712, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[4:5], 4.0, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_4_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    537395200(1.151965e-19), 32(4.484155e-44)
+; EG-NEXT:    1074790400(2.250000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 4616189618054758400, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[4:5], -4.0, s4
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_neg_4_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    1611137024(3.919933e+19), 32(4.484155e-44)
+; EG-NEXT:    -1072693248(-2.250000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 13839561654909534208, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_f32_4_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 11, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT T0.W, KC0[2].W,
+; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
+; EG-NEXT:     AND_INT T0.W, PV.W, literal.x,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
 ; EG-NEXT:     LSHL T0.Z, literal.x, PS,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, 0.0, literal.y, PV.W,
+; EG-NEXT:     LSHR T0.W, literal.y, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.z,
 ; EG-NEXT:    1082130432(4.000000e+00), 541065216(1.626303e-19)
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, PV.Z,
 ; EG-NEXT:     CNDE_INT T0.X, T1.W, T0.Z, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 1082130432, %a

 ; VI-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_imm_f32_neg_4_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 12, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 15, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     AND_INT T0.Z, KC0[2].W, literal.x,
-; EG-NEXT:     MOV T0.W, literal.y,
-; EG-NEXT:     NOT_INT * T1.W, KC0[2].W,
-; EG-NEXT:    31(4.344025e-44), -532676608(-5.534023e+19)
-; EG-NEXT:     BIT_ALIGN_INT T1.Z, literal.x, PV.W, PS,
-; EG-NEXT:     LSHL T0.W, literal.y, PV.Z,
-; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.z,
-; EG-NEXT:    2147483647(nan), -1065353216(-4.000000e+00)
-; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     NOT_INT T0.W, KC0[2].W,
+; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHR T0.W, literal.x, PV.W,
+; EG-NEXT:     LSHL * T2.W, literal.y, T1.W,
+; EG-NEXT:    -532676608(-5.534023e+19), -2(nan)
+; EG-NEXT:     OR_INT T0.Z, PS, PV.W,
+; EG-NEXT:     LSHL T0.W, literal.x, T1.W,
+; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
+; EG-NEXT:    -1065353216(-4.000000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.Z, PV.W,
 ; EG-NEXT:     CNDE_INT T0.X, T1.W, T0.W, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 -1065353216, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_high_imm_f32_4_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    541065216(1.626303e-19), 32(4.484155e-44)
+; EG-NEXT:    1082130432(4.000000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 4647714815446351872, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

 ; VI-NEXT:    s_lshl_b64 s[0:1], s[0:1], s2
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64:
 ; EG:       ; %bb.0:
-; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 8, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     NOT_INT * T0.W, KC0[2].W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
+; EG-NEXT:     AND_INT * T0.W, KC0[2].W, literal.x,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T0.W, literal.x, PV.W,
 ; EG-NEXT:     AND_INT * T1.W, KC0[2].W, literal.y,
-; EG-NEXT:    1614807040(5.534023e+19), 32(4.484155e-44)
+; EG-NEXT:    -1065353216(-4.000000e+00), 32(4.484155e-44)
 ; EG-NEXT:     CNDE_INT * T0.Y, PS, PV.W, 0.0,
 ; EG-NEXT:     MOV T0.X, 0.0,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %shl = shl i64 13871086852301127680, %a
   store i64 %shl, ptr addrspace(1) %out, align 8
   ret void
 }

llvm/test/CodeGen/AMDGPU/sra.ll

 ; VI-NEXT:    s_ashr_i64 s[4:5], s[4:5], 8
 ; VI-NEXT:    v_mov_b32_e32 v0, s4
 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: s_ashr_i64:
 ; EG:       ; %bb.0: ; %entry
-; EG-NEXT:    ALU 4, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 7, @4, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    ALU clause starting at 4:
-; EG-NEXT:     ASHR * T0.Y, KC0[2].Z, literal.x,
-; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T0.X, PV.Y, KC0[2].Z, literal.x,
-; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
-; EG-NEXT:    8(1.121039e-44), 2(2.802597e-45)
+; EG-NEXT:     ASHR T0.Y, KC0[2].Z, literal.x,
+; EG-NEXT:     LSHR * T0.W, KC0[2].Z, literal.y,
+; EG-NEXT:    31(4.344025e-44), 8(1.121039e-44)
+; EG-NEXT:     LSHL * T1.W, PV.Y, literal.x,
+; EG-NEXT:    24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT:     OR_INT T0.X, PV.W, T0.W,
+; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 entry:
   %in.ext = sext i32 %in to i64
   %ashr = ashr i64 %in.ext, 8
   store i64 %ashr, ptr addrspace(1) %out
   ret void
 }
 
 define amdgpu_kernel void @ashr_i64_2(ptr addrspace(1) %out, ptr addrspace(1) %in) {

 ; VI-NEXT:    v_ashrrev_i64 v[0:1], v2, v[0:1]
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: ashr_i64_2:
 ; EG:       ; %bb.0: ; %entry
 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6
-; EG-NEXT:    ALU 10, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 15, @9, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 8:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 9:
-; EG-NEXT:     AND_INT * T0.W, T0.Z, literal.x,
+; EG-NEXT:     NOT_INT * T0.W, T0.Z,
+; EG-NEXT:     AND_INT T1.Z, T0.Z, literal.x,
+; EG-NEXT:     AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT:     LSHL * T1.W, T0.Y, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     ASHR T1.Z, T0.Y, PV.W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, T0.Z,
+; EG-NEXT:     LSHL T0.W, PS, PV.W,
+; EG-NEXT:     LSHR * T1.W, T0.X, PV.Z,
+; EG-NEXT:     OR_INT T2.Z, PV.W, PS,
+; EG-NEXT:     ASHR T0.W, T0.Y, T1.Z,
 ; EG-NEXT:     AND_INT * T1.W, T0.Z, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, PV.Z,
-; EG-NEXT:     ASHR T0.W, T0.Y, literal.x,
+; EG-NEXT:     CNDE_INT T0.X, PS, PV.Z, PV.W,
+; EG-NEXT:     ASHR T2.W, T0.Y, literal.x,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.y,
 ; EG-NEXT:    31(4.344025e-44), 2(2.802597e-45)
-; EG-NEXT:     CNDE_INT * T0.Y, T1.W, T1.Z, PV.W,
+; EG-NEXT:     CNDE_INT * T0.Y, T1.W, T0.W, PV.W,
 entry:
   %b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 1
   %a = load i64, ptr addrspace(1) %in
   %b = load i64, ptr addrspace(1) %b_ptr
   %result = ashr i64 %a, %b
   store i64 %result, ptr addrspace(1) %out
   ret void
 }

 ; VI-NEXT:    v_ashrrev_i64 v[0:1], v4, v[0:1]
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: ashr_v2i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @10, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 1 @6
-; EG-NEXT:    ALU 19, @11, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT:    ALU 30, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 16, #1
 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 10:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 11:
-; EG-NEXT:     AND_INT * T1.W, T1.Z, literal.x,
+; EG-NEXT:     NOT_INT * T1.W, T1.Z,
+; EG-NEXT:     AND_INT T1.Y, T1.Z, literal.x,
+; EG-NEXT:     AND_INT T2.Z, PV.W, literal.x,
+; EG-NEXT:     LSHL T1.W, T0.W, 1,
+; EG-NEXT:     NOT_INT * T2.W, T1.X,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     ASHR T1.Y, T0.W, PV.W,
-; EG-NEXT:     AND_INT T2.Z, T1.Z, literal.x,
-; EG-NEXT:     BIT_ALIGN_INT T1.W, T0.W, T0.Z, T1.Z,
-; EG-NEXT:     AND_INT * T2.W, T1.X, literal.y,
-; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
-; EG-NEXT:     ASHR T2.Y, T0.Y, PS,
-; EG-NEXT:     CNDE_INT T0.Z, PV.Z, PV.W, PV.Y,
-; EG-NEXT:     BIT_ALIGN_INT T1.W, T0.Y, T0.X, T1.X,
-; EG-NEXT:     AND_INT * T2.W, T1.X, literal.x,
+; EG-NEXT:     AND_INT T2.X, T1.X, literal.x,
+; EG-NEXT:     AND_INT T2.Y, PS, literal.x,
+; EG-NEXT:     LSHL T3.Z, T0.Y, 1,
+; EG-NEXT:     LSHL T1.W, PV.W, PV.Z,
+; EG-NEXT:     LSHR * T2.W, T0.Z, PV.Y,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     OR_INT T3.X, PV.W, PS,
+; EG-NEXT:     ASHR T1.Y, T0.W, T1.Y,
+; EG-NEXT:     AND_INT T0.Z, T1.Z, literal.x,
+; EG-NEXT:     LSHL T1.W, PV.Z, PV.Y,
+; EG-NEXT:     LSHR * T2.W, T0.X, PV.X,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, PV.Y,
+; EG-NEXT:     OR_INT T2.Y, PV.W, PS,
+; EG-NEXT:     CNDE_INT T1.Z, PV.Z, PV.X, PV.Y,
+; EG-NEXT:     ASHR T2.W, T0.Y, T2.X,
+; EG-NEXT:     AND_INT * T3.W, T1.X, literal.x,
+; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     CNDE_INT T1.X, PS, PV.Y, PV.W,
 ; EG-NEXT:     ASHR T0.W, T0.W, literal.x,
-; EG-NEXT:     ASHR * T1.W, T0.Y, literal.x,
+; EG-NEXT:     ASHR * T4.W, T0.Y, literal.x,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT * T0.W, T2.Z, T1.Y, PV.W,
-; EG-NEXT:     LSHR T1.X, KC0[2].Y, literal.x,
-; EG-NEXT:     CNDE_INT * T0.Y, T2.W, T2.Y, T1.W,
+; EG-NEXT:     CNDE_INT * T1.W, T0.Z, T1.Y, PV.W,
+; EG-NEXT:     LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT:     CNDE_INT * T1.Y, T3.W, T2.W, T4.W,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %in, i64 1
   %a = load <2 x i64>, ptr addrspace(1) %in
   %b = load <2 x i64>, ptr addrspace(1) %b_ptr
   %result = ashr <2 x i64> %a, %b
   store <2 x i64> %result, ptr addrspace(1) %out
   ret void
 }

 ; VI-NEXT:    buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: ashr_v4i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @14, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 3 @6
-; EG-NEXT:    ALU 39, @15, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T3.X, 0
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT:    ALU 61, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T3.X, 0
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 32, #1
 ; EG-NEXT:     VTX_READ_128 T2.XYZW, T0.X, 48, #1
-; EG-NEXT:     VTX_READ_128 T3.XYZW, T0.X, 0, #1
-; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 16, #1
+; EG-NEXT:     VTX_READ_128 T3.XYZW, T0.X, 16, #1
+; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 14:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 15:
-; EG-NEXT:     AND_INT * T1.W, T1.Z, literal.x,
+; EG-NEXT:     NOT_INT * T1.W, T1.Z,
+; EG-NEXT:     AND_INT T4.Z, T1.Z, literal.x,
+; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
+; EG-NEXT:     LSHL * T2.W, T0.W, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     ASHR T1.Y, T0.W, literal.x,
-; EG-NEXT:     ASHR T4.Z, T3.W, PV.W, BS:VEC_120/SCL_212
-; EG-NEXT:     AND_INT T1.W, T1.Z, literal.y,
-; EG-NEXT:     AND_INT * T2.W, T2.Z, literal.x,
-; EG-NEXT:    31(4.344025e-44), 32(4.484155e-44)
-; EG-NEXT:     BIT_ALIGN_INT T4.X, T3.W, T3.Z, T1.Z,
-; EG-NEXT:     ASHR T2.Y, T0.W, PS, BS:VEC_120/SCL_212
-; EG-NEXT:     AND_INT * T1.Z, T2.Z, literal.x,
-; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.W, T0.Z, T2.Z,
-; EG-NEXT:     AND_INT * T2.W, T2.X, literal.x,
+; EG-NEXT:     LSHL T1.W, PS, PV.W,
+; EG-NEXT:     LSHR * T2.W, T0.Z, PV.Z,
+; EG-NEXT:     ASHR T1.Y, T3.W, literal.x,
+; EG-NEXT:     OR_INT T0.Z, PV.W, PS,
+; EG-NEXT:     ASHR T1.W, T0.W, T4.Z, BS:VEC_102/SCL_221
+; EG-NEXT:     NOT_INT * T2.W, T2.Z,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T5.X, T1.X, literal.x,
-; EG-NEXT:     ASHR T4.Y, T0.Y, PS,
-; EG-NEXT:     CNDE_INT T0.Z, T1.Z, PV.W, T2.Y,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, T2.X,
-; EG-NEXT:     AND_INT * T2.W, T2.X, literal.y,
-; EG-NEXT:    31(4.344025e-44), 32(4.484155e-44)
-; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, PV.Y,
-; EG-NEXT:     ASHR T5.Y, T3.Y, PV.X,
-; EG-NEXT:     CNDE_INT T2.Z, T1.W, T4.X, T4.Z,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T3.Y, T3.X, T1.X, BS:VEC_102/SCL_221
-; EG-NEXT:     AND_INT * T4.W, T1.X, literal.x,
+; EG-NEXT:     AND_INT T4.X, T1.Z, literal.x,
+; EG-NEXT:     NOT_INT T2.Y, T1.X,
+; EG-NEXT:     AND_INT T1.Z, T2.Z, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     AND_INT T2.W, PS, literal.y,
+; EG-NEXT:     LSHL * T4.W, T3.W, 1,
+; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
+; EG-NEXT:     NOT_INT T5.X, T2.X,
+; EG-NEXT:     LSHL T4.Y, PS, PV.W,
+; EG-NEXT:     LSHR T3.Z, T3.Z, PV.Z,
+; EG-NEXT:     AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT:     LSHL * T4.W, T0.Y, 1,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T6.X, PS, PV.W,
+; EG-NEXT:     OR_INT T2.Y, PV.Y, PV.Z,
+; EG-NEXT:     AND_INT T3.Z, T2.X, literal.x,
+; EG-NEXT:     AND_INT T2.W, PV.X, literal.x,
+; EG-NEXT:     LSHL * T4.W, T3.Y, 1,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     ASHR T5.X, T3.W, T1.Z,
+; EG-NEXT:     AND_INT T4.Y, T2.Z, literal.x,
+; EG-NEXT:     LSHL T1.Z, PS, PV.W,
+; EG-NEXT:     LSHR T2.W, T3.X, PV.Z,
+; EG-NEXT:     AND_INT * T3.W, T1.X, literal.y,
+; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
+; EG-NEXT:     LSHR T0.X, T0.X, PS,
+; EG-NEXT:     OR_INT T5.Y, PV.Z, PV.W,
+; EG-NEXT:     CNDE_INT T2.Z, PV.Y, T2.Y, PV.X,
+; EG-NEXT:     ASHR T4.W, T3.Y, T3.Z,
+; EG-NEXT:     AND_INT * T5.W, T2.X, literal.x,
+; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     CNDE_INT T2.X, PS, PV.Y, PV.W,
+; EG-NEXT:     OR_INT T2.Y, T6.X, PV.X,
+; EG-NEXT:     CNDE_INT T0.Z, T4.X, T0.Z, T1.W, BS:VEC_120/SCL_212
+; EG-NEXT:     ASHR T3.W, T0.Y, T3.W,
+; EG-NEXT:     AND_INT * T6.W, T1.X, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, PV.Y,
-; EG-NEXT:     ASHR T6.Y, T3.W, literal.x,
-; EG-NEXT:     ASHR T3.Z, T0.Y, literal.x, BS:VEC_201
-; EG-NEXT:     ADD_INT T3.W, KC0[2].Y, literal.y,
-; EG-NEXT:     CNDE_INT * T0.W, T1.Z, T2.Y, T1.Y,
+; EG-NEXT:     CNDE_INT T0.X, PS, PV.Y, PV.W,
+; EG-NEXT:     ASHR T5.Y, T0.W, literal.x,
+; EG-NEXT:     ASHR T1.Z, T3.Y, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT:     ADD_INT T0.W, KC0[2].Y, literal.y,
+; EG-NEXT:     CNDE_INT * T2.W, T4.Y, T5.X, T1.Y,
 ; EG-NEXT:    31(4.344025e-44), 16(2.242078e-44)
 ; EG-NEXT:     LSHR T1.X, PV.W, literal.x,
-; EG-NEXT:     CNDE_INT T0.Y, T2.W, T4.Y, PV.Z,
-; EG-NEXT:     ASHR T3.W, T3.Y, literal.y,
-; EG-NEXT:     CNDE_INT * T2.W, T1.W, T4.Z, PV.Y,
+; EG-NEXT:     CNDE_INT T2.Y, T5.W, T4.W, PV.Z, BS:VEC_021/SCL_122
+; EG-NEXT:     ASHR T4.W, T0.Y, literal.y,
+; EG-NEXT:     CNDE_INT * T0.W, T4.X, T1.W, PV.Y,
 ; EG-NEXT:    2(2.802597e-45), 31(4.344025e-44)
 ; EG-NEXT:     LSHR T3.X, KC0[2].Y, literal.x,
-; EG-NEXT:     CNDE_INT * T2.Y, T4.W, T5.Y, PV.W,
+; EG-NEXT:     CNDE_INT * T0.Y, T6.W, T3.W, PV.W,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
   %b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %in, i64 1
   %a = load <4 x i64>, ptr addrspace(1) %in
   %b = load <4 x i64>, ptr addrspace(1) %b_ptr
   %result = ashr <4 x i64> %a, %b
   store <4 x i64> %result, ptr addrspace(1) %out
   ret void
 }

llvm/test/CodeGen/AMDGPU/srl.ll

 ; VI-NEXT:    v_mov_b32_e32 v1, s5
 ; VI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: lshr_i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @8, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 0 @6
-; EG-NEXT:    ALU 9, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    ALU 14, @9, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    PAD
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 8:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 9:
-; EG-NEXT:     AND_INT * T0.W, T0.Z, literal.x,
+; EG-NEXT:     NOT_INT * T0.W, T0.Z,
+; EG-NEXT:     AND_INT T1.Z, T0.Z, literal.x,
+; EG-NEXT:     AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT:     LSHL * T1.W, T0.Y, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     LSHR T1.Z, T0.Y, PV.W,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, T0.Z,
+; EG-NEXT:     LSHL T0.W, PS, PV.W,
+; EG-NEXT:     LSHR * T1.W, T0.X, PV.Z,
+; EG-NEXT:     OR_INT T2.Z, PV.W, PS,
+; EG-NEXT:     LSHR T0.W, T0.Y, T1.Z,
 ; EG-NEXT:     AND_INT * T1.W, T0.Z, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T0.X, PS, PV.W, PV.Z,
+; EG-NEXT:     CNDE_INT T0.X, PS, PV.Z, PV.W,
 ; EG-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT * T0.Y, T1.W, T1.Z, 0.0,
+; EG-NEXT:     CNDE_INT * T0.Y, T1.W, T0.W, 0.0,
   %b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 1
   %a = load i64, ptr addrspace(1) %in
   %b = load i64, ptr addrspace(1) %b_ptr
   %result = lshr i64 %a, %b
   store i64 %result, ptr addrspace(1) %out
   ret void
 }
 

 ; VI-NEXT:    v_mov_b32_e32 v3, s3
 ; VI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[16:19], 0
 ; VI-NEXT:    s_endpgm
 ;
 ; EG-LABEL: lshr_v4i64:
 ; EG:       ; %bb.0:
 ; EG-NEXT:    ALU 0, @14, KC0[CB0:0-32], KC1[]
 ; EG-NEXT:    TEX 3 @6
-; EG-NEXT:    ALU 34, @15, KC0[CB0:0-32], KC1[]
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0
-; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
+; EG-NEXT:    ALU 55, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 0
+; EG-NEXT:    MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T1.X, 1
 ; EG-NEXT:    CF_END
 ; EG-NEXT:    Fetch clause starting at 6:
 ; EG-NEXT:     VTX_READ_128 T1.XYZW, T0.X, 32, #1
 ; EG-NEXT:     VTX_READ_128 T2.XYZW, T0.X, 16, #1
 ; EG-NEXT:     VTX_READ_128 T3.XYZW, T0.X, 48, #1
 ; EG-NEXT:     VTX_READ_128 T0.XYZW, T0.X, 0, #1
 ; EG-NEXT:    ALU clause starting at 14:
 ; EG-NEXT:     MOV * T0.X, KC0[2].Z,
 ; EG-NEXT:    ALU clause starting at 15:
-; EG-NEXT:     AND_INT * T1.W, T1.Z, literal.x,
+; EG-NEXT:     NOT_INT * T1.W, T1.Z,
+; EG-NEXT:     AND_INT T4.Z, T1.Z, literal.x,
+; EG-NEXT:     AND_INT T1.W, PV.W, literal.x,
+; EG-NEXT:     LSHL * T3.W, T0.W, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     LSHR T4.Z, T0.W, PV.W,
-; EG-NEXT:     AND_INT T1.W, T1.Z, literal.x,
-; EG-NEXT:     AND_INT * T3.W, T3.Z, literal.y,
+; EG-NEXT:     LSHL T1.W, PS, PV.W,
+; EG-NEXT:     LSHR * T3.W, T0.Z, PV.Z,
+; EG-NEXT:     OR_INT T0.Z, PV.W, PS,
+; EG-NEXT:     LSHR T0.W, T0.W, T4.Z,
+; EG-NEXT:     NOT_INT * T1.W, T3.Z,
+; EG-NEXT:     AND_INT T4.X, T1.Z, literal.x,
+; EG-NEXT:     NOT_INT T1.Y, T1.X,
+; EG-NEXT:     AND_INT T1.Z, T3.Z, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT:     AND_INT T1.W, PS, literal.y,
+; EG-NEXT:     LSHL * T3.W, T2.W, 1,
 ; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
-; EG-NEXT:     BIT_ALIGN_INT T4.X, T0.W, T0.Z, T1.Z,
-; EG-NEXT:     LSHR T1.Y, T2.W, PS, BS:VEC_120/SCL_212
-; EG-NEXT:     AND_INT * T0.Z, T3.Z, literal.x,
-; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T2.W, T2.Z, T3.Z,
-; EG-NEXT:     AND_INT * T2.W, T3.X, literal.x,
+; EG-NEXT:     NOT_INT T5.X, T3.X,
+; EG-NEXT:     LSHL T3.Y, PS, PV.W,
+; EG-NEXT:     LSHR T2.Z, T2.Z, PV.Z,
+; EG-NEXT:     AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT:     LSHL * T3.W, T0.Y, 1,
+; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT:     LSHL T6.X, PS, PV.W,
+; EG-NEXT:     OR_INT T1.Y, PV.Y, PV.Z,
+; EG-NEXT:     AND_INT T2.Z, T3.X, literal.x,
+; EG-NEXT:     AND_INT T1.W, PV.X, literal.x,
+; EG-NEXT:     LSHL * T3.W, T2.Y, 1,
 ; EG-NEXT:    31(4.344025e-44), 0(0.000000e+00)
-; EG-NEXT:     AND_INT T5.X, T1.X, literal.x,
-; EG-NEXT:     LSHR T3.Y, T2.Y, PS,
-; EG-NEXT:     CNDE_INT T2.Z, T0.Z, PV.W, T1.Y,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T2.Y, T2.X, T3.X,
-; EG-NEXT:     AND_INT * T3.W, T3.X, literal.y,
-; EG-NEXT:    31(4.344025e-44), 32(4.484155e-44)
-; EG-NEXT:     CNDE_INT T2.X, PS, PV.W, PV.Y,
-; EG-NEXT:     LSHR T4.Y, T0.Y, PV.X,
-; EG-NEXT:     CNDE_INT T1.Z, T1.W, T4.X, T4.Z,
-; EG-NEXT:     BIT_ALIGN_INT T0.W, T0.Y, T0.X, T1.X, BS:VEC_102/SCL_221
-; EG-NEXT:     AND_INT * T4.W, T1.X, literal.x,
+; EG-NEXT:     LSHR T5.X, T2.W, T1.Z,
+; EG-NEXT:     AND_INT T3.Y, T3.Z, literal.x,
+; EG-NEXT:     LSHL T1.Z, PS, PV.W,
+; EG-NEXT:     LSHR T1.W, T2.X, PV.Z,
+; EG-NEXT:     AND_INT * T2.W, T1.X, literal.y,
+; EG-NEXT:    32(4.484155e-44), 31(4.344025e-44)
+; EG-NEXT:     LSHR T0.X, T0.X, PS,
+; EG-NEXT:     OR_INT T4.Y, PV.Z, PV.W,
+; EG-NEXT:     CNDE_INT T3.Z, PV.Y, T1.Y, PV.X,
+; EG-NEXT:     LSHR T1.W, T2.Y, T2.Z,
+; EG-NEXT:     AND_INT * T4.W, T3.X, literal.x,
+; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT:     CNDE_INT T3.X, PS, PV.Y, PV.W,
+; EG-NEXT:     OR_INT T1.Y, T6.X, PV.X,
+; EG-NEXT:     CNDE_INT T0.Z, T4.X, T0.Z, T0.W, BS:VEC_120/SCL_212
+; EG-NEXT:     LSHR T2.W, T0.Y, T2.W,
+; EG-NEXT:     AND_INT * T5.W, T1.X, literal.x,
 ; EG-NEXT:    32(4.484155e-44), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT T1.X, PS, PV.W, PV.Y,
-; EG-NEXT:     ADD_INT T0.W, KC0[2].Y, literal.x,
-; EG-NEXT:     CNDE_INT * T2.W, T0.Z, T1.Y, 0.0,
+; EG-NEXT:     CNDE_INT T0.X, PS, PV.Y, PV.W,
+; EG-NEXT:     ADD_INT T6.W, KC0[2].Y, literal.x,
+; EG-NEXT:     CNDE_INT * T3.W, T3.Y, T5.X, 0.0,
 ; EG-NEXT:    16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT:     LSHR T0.X, PV.W, literal.x,
-; EG-NEXT:     CNDE_INT T2.Y, T3.W, T3.Y, 0.0,
-; EG-NEXT:     CNDE_INT T1.W, T1.W, T4.Z, 0.0, BS:VEC_120/SCL_212
-; EG-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
+; EG-NEXT:     LSHR T1.X, PV.W, literal.x,
+; EG-NEXT:     CNDE_INT T3.Y, T4.W, T1.W, 0.0,
+; EG-NEXT:     CNDE_INT T0.W, T4.X, T0.W, 0.0, BS:VEC_021/SCL_122
+; EG-NEXT:     LSHR * T2.X, KC0[2].Y, literal.x,
 ; EG-NEXT:    2(2.802597e-45), 0(0.000000e+00)
-; EG-NEXT:     CNDE_INT * T1.Y, T4.W, T4.Y, 0.0,
+; EG-NEXT:     CNDE_INT * T0.Y, T5.W, T2.W, 0.0,
   %b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %in, i64 1
   %a = load <4 x i64>, ptr addrspace(1) %in
   %b = load <4 x i64>, ptr addrspace(1) %b_ptr
   %result = lshr <4 x i64> %a, %b
   store <4 x i64> %result, ptr addrspace(1) %out
   ret void
 }