[SystemZ] Allow symbols in immediate asm operands

[iii]

Summary

Currently mentioning any symbols in immediate asm operands is not
supported, for example:

error: invalid operand for instruction
lghi %r4,foo_end-foo

The immediate problem is that is*Imm() and print*Operand() functions do
not accept MCExprs, but simply relaxing these checks is not enough:
after symbol addresses are computed, range checks need to run against
resolved values.

Add a number of SystemZ::FixupKind members for each kind of immediate
value and process them in SystemZMCAsmBackend::applyFixup(). Only
perform the range checks, do not change anything.

In order to create fixups, one needs to know the operand offsets.
Unfortunately the existing LLVM infrastructure does not provide this
information. Implement generating getOperandBitOffset(), which provides
this information. It does not return useful values for multi-lit
operands, such as SystemZ vector registers, but this is not important
for its intended use case.

Finally, adjust the tests: move previously failing cases like the
one shown above out of insn-bad.s.

[iii]

• Remove an unused variable.
• Remove an irrelevant whitespace change.

[uweigand]

Thanks for working on that, Ilya! If we do allow symbols in immediates (and I agree we should), we should then also handle the case where they don't completely resolve, but result in relocations. This should be straightforward to add once we already have fixups. In addition to R_S390_12 (which is already emitted, and should be used for the U12Imm cases as well), we do support 1-, 2-, 4-, and 8-byte relocations. The sub-byte (U1Imm, U2Imm, U3Imm, U4Imm) and .insn opcode (U48Imm) cases don't have corresponding relocations, but I believe for those we should not allow any symbolic expressions anyway.

Also, it would be good to have tests for the PC-relative cases (symbol-.), both where those resolve at assemble time (symbol in the current section), and where a PC-relative reloc is required (symbol in another section).

Finally, for the tablegen changes I'd prefer to have someone more familiar with that code base to review it. Maybe we can split this off into a separate diff (possibly combined with a getDispOpValue change to make use of it for displacements)?

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp

88

I don't think we should have the "imm" markup for expressions.

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

207

I think this should rather go into getDispOpValue ... a displacement is in fact simply an immediate.

The getOperandBitOffset logic should allow us to replace the MemOpsEmitted hack we currently have there, and then generalize it to all immediates.

The getMachineOpValue will then be only used for registers.

[iii]

• Emit relocations.
• Add various tests.
• Remove "imm" markup for expressions.
• Move the isExpr() logic to getDispOpValue().

[iii]

I've added pc-relative tests, but only for PC32. For PC32DBL I tried (src-.)/2, but the common code does not recognize division as a relocatable expression, and does not let the backend to handle it either. GAS does not handle it either though, so it's probably fine:

lgfi %r0,(foo-.)/2
1.s:1: Error: invalid operands (*UND* and .text sections) for `-'

[uweigand]

Thanks for the updates, looking really good now. Just a few cosmetic comments inline.

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

82

Can we rename this to something like getImmOpValue - it's no longer just displacements. Also the comment should be updated.

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h

24

Can we integrate the handling of displacements into the new scheme and use FK_390_U12Imm and FK_390_S20Imm here (and elsewhere)? In generals, displacements should just be a type of immediates.

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp

60 ↗

(On Diff #542478)

Would be nicer to reformat those cases as well so that all use the same style.

llvm/test/MC/SystemZ/fixups.s

8

Would it make sense to add CHECK-DIS lines to the existing tests as well?

[uweigand]

In D154899#4518775, @iii wrote:

I've added pc-relative tests, but only for PC32. For PC32DBL I tried (src-.)/2, but the common code does not recognize division as a relocatable expression, and does not let the backend to handle it either. GAS does not handle it either though, so it's probably fine:

Agreed, I think this is fine. The DBL relocations really are intended for the LARL-type instructions, where the /2 is implicit.

[iii]

• Rename getDispOpValue() to getImmOpValue().
• Rename FK_390_12 to FK_390_U12Imm and FK_390_20 to FK_390_S20Imm.
• Reformat.

llvm/test/MC/SystemZ/fixups.s

8

For the new tests it's important, because it allows us to check the resolved immediate value. The existing tests depend relocations, so it's going to be only zeroes anyway.

[uweigand]

LGTM, thanks!

llvm/test/MC/SystemZ/fixups.s

8

OK, makes sense.

llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

unsigned getReg() const override {
     return Reg.Num;
   }
 
   // Immediate operands.
   bool isImm() const override {
     return Kind == KindImm;
   }
   bool isImm(int64_t MinValue, int64_t MaxValue) const {
-    return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
+    return Kind == KindImm && inRange(Imm, MinValue, MaxValue, true);
   }
   const MCExpr *getImm() const {
     assert(Kind == KindImm && "Not an immediate");
     return Imm;
   }
 
   // Immediate operands with optional TLS symbol.
   bool isImmTLS() const {

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp

void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                    raw_ostream &O) {
   printInstruction(MI, Address, O);
   printAnnotation(O, Annot);
 }
 
 template <unsigned N>
 void SystemZInstPrinter::printUImmOperand(const MCInst *MI, int OpNum,
                                           raw_ostream &O) {
-  int64_t Value = MI->getOperand(OpNum).getImm();
+  const MCOperand &MO = MI->getOperand(OpNum);
+  if (MO.isExpr()) {
+    O << markup("<imm:") << *MO.getExpr() << markup(">");
+    return;
+  }
+  uint64_t Value = static_cast<uint64_t>(MO.getImm());
   assert(isUInt<N>(Value) && "Invalid uimm argument");
   O << markup("<imm:") << Value << markup(">");
 }
 
 template <unsigned N>
 void SystemZInstPrinter::printSImmOperand(const MCInst *MI, int OpNum,
                                           raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNum);
+  if (MO.isExpr()) {
+    O << markup("<imm:") << *MO.getExpr() << markup(">");
+    return;
+  }
   int64_t Value = MI->getOperand(OpNum).getImm();
   assert(isInt<N>(Value) && "Invalid simm argument");
   O << markup("<imm:") << Value << markup(">");
 }
 
 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
   printUImmOperand<1>(MI, OpNum, O);

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
   auto handlePCRelFixupValue = [&](unsigned W) -> uint64_t {
     if (Value % 2 != 0)
       Ctx.reportError(Fixup.getLoc(), "Non-even PC relative offset.");
     if (!checkFixupInRange(minIntN(W) * 2, maxIntN(W) * 2))
       return 0;
     return (int64_t)Value / 2;
   };
 
+  auto handleImmValue = [&](bool IsSigned, unsigned W) -> uint64_t {
+    if (!(IsSigned ? checkFixupInRange(minIntN(W), maxIntN(W))
+                   : checkFixupInRange(0, maxUIntN(W))))
+      return 0;
+    return Value;
+  };
+
   switch (unsigned(Kind)) {
   case SystemZ::FK_390_PC12DBL:
     return handlePCRelFixupValue(12);
   case SystemZ::FK_390_PC16DBL:
     return handlePCRelFixupValue(16);
   case SystemZ::FK_390_PC24DBL:
     return handlePCRelFixupValue(24);
   case SystemZ::FK_390_PC32DBL:
case SystemZ::FK_390_20: {
     // The high byte of a 20 bit displacement value comes first.
     uint64_t DLo = Value & 0xfff;
     uint64_t DHi = (Value >> 12) & 0xff;
     return (DLo << 8) | DHi;
   }
 
   case SystemZ::FK_390_TLS_CALL:
     return 0;
+
+  case SystemZ::FK_390_S8Imm:
+    return handleImmValue(true, 8);
+  case SystemZ::FK_390_S16Imm:
+    return handleImmValue(true, 16);
+  case SystemZ::FK_390_S32Imm:
+    return handleImmValue(true, 32);
+  case SystemZ::FK_390_U1Imm:
+    return handleImmValue(false, 1);
+  case SystemZ::FK_390_U2Imm:
+    return handleImmValue(false, 2);
+  case SystemZ::FK_390_U3Imm:
+    return handleImmValue(false, 3);
+  case SystemZ::FK_390_U4Imm:
+    return handleImmValue(false, 4);
+  case SystemZ::FK_390_U8Imm:
+    return handleImmValue(false, 8);
+  case SystemZ::FK_390_U12Imm:
+    return handleImmValue(false, 12);
+  case SystemZ::FK_390_U16Imm:
+    return handleImmValue(false, 16);
+  case SystemZ::FK_390_U32Imm:
+    return handleImmValue(false, 32);
+  case SystemZ::FK_390_U48Imm:
+    return handleImmValue(false, 48);
   }
 
   llvm_unreachable("Unknown fixup kind!");
 }
 
 namespace {
 class SystemZMCAsmBackend : public MCAsmBackend {
   uint8_t OSABI;
#undef ELF_RELOC
   if (Type != -1u)
     return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
   return std::nullopt;
 }
 
 const MCFixupKindInfo &
 SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
   const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = {
-    { "FK_390_PC12DBL",  4, 12, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_390_PC16DBL",  0, 16, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_390_PC24DBL",  0, 24, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_390_PC32DBL",  0, 32, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_390_TLS_CALL", 0, 0, 0 },
-    { "FK_390_12",       4, 12, 0 },
-    { "FK_390_20",       4, 20, 0 }
+      {"FK_390_PC12DBL", 4, 12, MCFixupKindInfo::FKF_IsPCRel},
+      {"FK_390_PC16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
+      {"FK_390_PC24DBL", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
+      {"FK_390_PC32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+      {"FK_390_TLS_CALL", 0, 0, 0},
+      {"FK_390_12", 4, 12, 0},
+      {"FK_390_20", 4, 20, 0},
+      {"FK_390_S8Imm", 0, 8, 0},
+      {"FK_390_S16Imm", 0, 16, 0},
+      {"FK_390_S32Imm", 0, 32, 0},
+      {"FK_390_U1Imm", 0, 1, 0},
+      {"FK_390_U2Imm", 0, 2, 0},
+      {"FK_390_U3Imm", 0, 3, 0},
+      {"FK_390_U4Imm", 0, 4, 0},
+      {"FK_390_U8Imm", 0, 8, 0},
+      {"FK_390_U12Imm", 0, 12, 0},
+      {"FK_390_U16Imm", 0, 16, 0},
+      {"FK_390_U32Imm", 0, 32, 0},
+      {"FK_390_U48Imm", 0, 48, 0},
   };
 
   // Fixup kinds from .reloc directive are like R_390_NONE. They
   // do not require any extra processing.
   if (Kind >= FirstLiteralRelocationKind)
     return MCAsmBackend::getFixupKindInfo(FK_NONE);
 
   if (Kind < FirstTargetFixupKind)

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
                          const MCSubtargetInfo &STI) const override;
 
 private:
   // Automatically generated by TableGen.
   uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 
+  // Automatically generated by TableGen.
+  uint32_t getOperandBitOffset(const MCInst &MI, unsigned OpNum,
+                               const MCSubtargetInfo &STI) const;
+
   // Called by the TableGen code to get the binary encoding of operand
   // MO in MI.  Fixups is the list of fixups against MI.
   uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
-                             const MCSubtargetInfo &STI) const;
+                             const MCSubtargetInfo &STI, unsigned OpNum = 0,
+                             SystemZ::FixupKind FixupKind =
+                                 SystemZ::FixupKind::LastTargetFixupKind) const;
+
+  template <SystemZ::FixupKind FixupKind>
+  uint64_t encodeImmOperand(const MCInst &MI, unsigned OpNum,
+                            SmallVectorImpl<MCFixup> &Fixups,
+                            const MCSubtargetInfo &STI) const {
+    return getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI, OpNum,
+                             FixupKind);
+  }
 
   // Return the displacement value for the OpNum operand. If it is a symbol,
   // add a fixup for it and return 0.
   uint64_t getDispOpValue(const MCInst &MI, unsigned OpNum,
                           SmallVectorImpl<MCFixup> &Fixups,
                           SystemZ::FixupKind Kind) const;
 
   // Called by the TableGen code to get the binary encoding of an address.
   // The index or length, if any, is encoded first, followed by the base,
   // followed by the displacement.  In a 20-bit displacement,
   // the low 12 bits are encoded before the high 8 bits.
   uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
void SystemZMCCodeEmitter::encodeInstruction(const MCInst &MI,
   // Big-endian insertion of Size bytes.
   unsigned ShiftValue = (Size * 8) - 8;
   for (unsigned I = 0; I != Size; ++I) {
     CB.push_back(uint8_t(Bits >> ShiftValue));
     ShiftValue -= 8;
   }
 }
 
-uint64_t SystemZMCCodeEmitter::
-getMachineOpValue(const MCInst &MI, const MCOperand &MO,
-                  SmallVectorImpl<MCFixup> &Fixups,
-                  const MCSubtargetInfo &STI) const {
+uint64_t SystemZMCCodeEmitter::getMachineOpValue(
+    const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI, unsigned OpNum,
+    SystemZ::FixupKind FixupKind) const {
   if (MO.isReg())
     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
   if (MO.isImm())
     return static_cast<uint64_t>(MO.getImm());
+  if (MO.isExpr()) {
+    if (FixupKind == SystemZ::FixupKind::LastTargetFixupKind) {
+      Ctx.reportError(MI.getLoc(), "invalid operand for instruction");
+      return 0;
+    }
+    uint32_t BitOffset = getOperandBitOffset(MI, OpNum, STI);
+    if (BitOffset & 7) {
+      Ctx.reportError(MI.getLoc(), "invalid operand for instruction");
+      return 0;
+    }
+    Fixups.push_back(MCFixup::create(BitOffset >> 3, MO.getExpr(),
+                                     (MCFixupKind)FixupKind, MI.getLoc()));
+    return 0;
+  }
   llvm_unreachable("Unexpected operand type!");
 }
 
 uint64_t SystemZMCCodeEmitter::
 getDispOpValue(const MCInst &MI, unsigned OpNum,
                SmallVectorImpl<MCFixup> &Fixups,
                SystemZ::FixupKind Kind) const {
   const MCOperand &MO = MI.getOperand(OpNum);
SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
   if (AllowTLS && OpNum + 1 < MI.getNumOperands()) {
     const MCOperand &MOTLS = MI.getOperand(OpNum + 1);
     Fixups.push_back(MCFixup::create(
         0, MOTLS.getExpr(), (MCFixupKind)SystemZ::FK_390_TLS_CALL, Loc));
   }
   return 0;
 }
 
+#define GET_OPERAND_BIT_OFFSET
 #include "SystemZGenMCCodeEmitter.inc"
 
 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
                                                 MCContext &Ctx) {
   return new SystemZMCCodeEmitter(MCII, Ctx);
 }

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h

 enum FixupKind {
   // These correspond directly to R_390_* relocations.
   FK_390_PC12DBL = FirstTargetFixupKind,
   FK_390_PC16DBL,
   FK_390_PC24DBL,
   FK_390_PC32DBL,
   FK_390_TLS_CALL,
   FK_390_12,
   FK_390_20,
 
+  FK_390_S8Imm,
+  FK_390_S16Imm,
+  FK_390_S32Imm,
+  FK_390_U1Imm,
+  FK_390_U2Imm,
+  FK_390_U3Imm,
+  FK_390_U4Imm,
+  FK_390_U8Imm,
+  FK_390_U12Imm,
+  FK_390_U16Imm,
+  FK_390_U32Imm,
+  FK_390_U48Imm,
+
   // Marker
   LastTargetFixupKind,
   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
 };
 } // end namespace SystemZ
 } // end namespace llvm
 
 #endif

llvm/lib/Target/SystemZ/SystemZOperands.td

 class ImmediateTLSAsmOperand<string name>
   : AsmOperandClass {
   let Name = name;
   let RenderMethod = "addImmTLSOperands";
 }
 
 class ImmediateOp<ValueType vt, string asmop> : Operand<vt> {
   let PrintMethod = "print"#asmop#"Operand";
+  let EncoderMethod = "encodeImmOperand<SystemZ::FK_390_"#asmop#">";
   let DecoderMethod = "decode"#asmop#"Operand";
   let ParserMatchClass = !cast<AsmOperandClass>(asmop);
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
 class ImmOpWithPattern<ValueType vt, string asmop, code pred, SDNodeXForm xform,
       SDNode ImmNode = imm> :
   ImmediateOp<vt, asmop>, PatLeaf<(vt ImmNode), pred, xform>;

llvm/test/MC/SystemZ/fixups.s

 
 # RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 --show-encoding %s | FileCheck %s
 
 # RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \
 # RUN: llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL
 
+# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \
+# RUN: llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-DIS
+
 # CHECK: larl %r14, target                      # encoding: [0xc0,0xe0,A,A,A,A]
 # CHECK-NEXT:                                   # fixup A - offset: 2, value: target+2, kind: FK_390_PC32DBL
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PC32DBL target 0x2
   .align 16
   larl %r14, target
 
 # CHECK: larl %r14, target@GOT                  # encoding: [0xc0,0xe0,A,A,A,A]
 # CHECK-NEXT:                                   # fixup A - offset: 2, value: target@GOT+2, kind: FK_390_PC32DBL
# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
         vgeg %v0, src(%v0,%r1), 0
 
 ## Fixup for second operand only
 # CHECK:  mvc     32(8,%r0), src                # encoding: [0xd2,0x07,0x00,0x20,0b0000AAAA,A]
 # CHECK-NEXT:                                   # fixup A - offset: 4, value: src, kind: FK_390_12
         .align 16
         mvc     32(8,%r0),src
 
+## Symbol calculations.
+# CHECK:  lghi %r0, lghi_b-lghi_a               # encoding: [0xa7,0x09,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: lghi_b-lghi_a, kind: FK_390_S16Imm
+# CHECK-DIS:                                    <lghi_a_b>:
+# CHECK-DIS-NEXT:                               a7 09 00 08   lghi    %r0, 8
+  .align 16
+lghi_a_b:
+  lghi %r0, lghi_b-lghi_a
+lghi_a: .quad 0
+lghi_b:
+
 # Data relocs
 # llvm-mc does not show any "encoding" string for data, so we just check the relocs
 
 # CHECK-REL: .rela.data
   .data
 
 # CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LE64 target 0x0
   .align 16

llvm/test/MC/SystemZ/insn-bad-z196.s

#CHECK: adtra %f0, %f0, %f0, 16
 
   adtra %f0, %f0, %f0, -1
   adtra %f0, %f0, %f0, 16
 
 #CHECK: error: invalid operand
 #CHECK: aghik %r0, %r1, -32769
 #CHECK: error: invalid operand
 #CHECK: aghik %r0, %r1, 32768
-#CHECK: error: invalid operand
-#CHECK: aghik %r0, %r1, foo
 
   aghik %r0, %r1, -32769
   aghik %r0, %r1, 32768
-  aghik %r0, %r1, foo
 
 #CHECK: error: invalid operand
 #CHECK: ahik  %r0, %r1, -32769
 #CHECK: error: invalid operand
 #CHECK: ahik  %r0, %r1, 32768
-#CHECK: error: invalid operand
-#CHECK: ahik  %r0, %r1, foo
 
   ahik  %r0, %r1, -32769
   ahik  %r0, %r1, 32768
-  ahik  %r0, %r1, foo
 
 #CHECK: error: invalid operand
 #CHECK: aih %r0, (-1 << 31) - 1
 #CHECK: error: invalid operand
 #CHECK: aih %r0, (1 << 31)
 
   aih  %r0, (-1 << 31) - 1
   aih %r0, (1 << 31)

llvm/test/MC/SystemZ/insn-bad.s

#CHECK: agfi  %r0, (1 << 31)
 
   agfi  %r0, (-1 << 31) - 1
   agfi  %r0, (1 << 31)
 
 #CHECK: error: invalid operand
 #CHECK: aghi  %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: aghi  %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: aghi  %r0, foo
 
   aghi  %r0, -32769
   aghi  %r0, 32768
-  aghi  %r0, foo
 
 #CHECK: error: instruction requires: distinct-ops
 #CHECK: aghik %r1, %r2, 3
 
   aghik %r1, %r2, 3
 
 #CHECK: error: instruction requires: distinct-ops
 #CHECK: agrk  %r2,%r3,%r4

 #CHECK: ahhlr %r0, %r0, %r0
 
   ahhlr %r0, %r0, %r0
 
 #CHECK: error: invalid operand
 #CHECK: ahi %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: ahi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: ahi %r0, foo
 
   ahi %r0, -32769
   ahi %r0, 32768
-  ahi %r0, foo
 
 #CHECK: error: instruction requires: distinct-ops
 #CHECK: ahik  %r1, %r2, 3
 
   ahik  %r1, %r2, 3
 
 #CHECK: error: invalid operand
 #CHECK: ahy %r0, -524289
#CHECK: jlno    label
   jlm label
   jlnm  label
   jllh  label
   jllnlh  label
   jlo label
   jlno  label
 
 #CHECK: error: invalid operand
-#CHECK: brc foo, bar
-#CHECK: error: invalid operand
 #CHECK: brc -1, bar
 #CHECK: error: invalid operand
 #CHECK: brc 16, bar
 
-  brc foo, bar
   brc -1, bar
   brc 16, bar
 
 #CHECK: error: offset out of range
 #CHECK: brcl  0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: brcl  0, -1
 #CHECK: error: offset out of range
#CHECK: jgnop 0x100000000
   jgnop 0x100000000
 
 
 #CHECK: error: invalid instruction
 #CHECK: jlnop label
   jlnop label
 
 #CHECK: error: invalid operand
-#CHECK: brcl  foo, bar
-#CHECK: error: invalid operand
 #CHECK: brcl  -1, bar
 #CHECK: error: invalid operand
 #CHECK: brcl  16, bar
 
-  brcl  foo, bar
   brcl  -1, bar
   brcl  16, bar
 
 #CHECK: error: offset out of range
 #CHECK: brct  %r0, -0x100002
 #CHECK: error: offset out of range
 #CHECK: brct  %r0, -1
 #CHECK: error: offset out of range
#CHECK: cgh %r0, 524288
 
   cgh %r0, -524289
   cgh %r0, 524288
 
 #CHECK: error: invalid operand
 #CHECK: cghi  %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: cghi  %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: cghi  %r0, foo
 
   cghi  %r0, -32769
   cghi  %r0, 32768
-  cghi  %r0, foo
 
 #CHECK: error: offset out of range
 #CHECK: cghrl %r0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: cghrl %r0, -1
 #CHECK: error: offset out of range
 #CHECK: cghrl %r0, 1
 #CHECK: error: offset out of range
#CHECK: chhsi 0, 32768
   chhsi 0(%r1,%r2), 0
   chhsi 0, -32769
   chhsi 0, 32768
 
 #CHECK: error: invalid operand
 #CHECK: chi %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: chi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: chi %r0, foo
 
   chi %r0, -32769
   chi %r0, 32768
-  chi %r0, foo
 
 #CHECK: error: instruction requires: high-word
 #CHECK: chlr  %r0, %r0
 
   chlr  %r0, %r0
 
 #CHECK: error: offset out of range
 #CHECK: chrl  %r0, -0x1000000002
#CHECK: lgh %r0, 524288
 
   lgh %r0, -524289
   lgh %r0, 524288
 
 #CHECK: error: invalid operand
 #CHECK: lghi  %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: lghi  %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: lghi  %r0, foo
 
   lghi  %r0, -32769
   lghi  %r0, 32768
-  lghi  %r0, foo
 
 #CHECK: error: offset out of range
 #CHECK: lghrl %r0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: lghrl %r0, -1
 #CHECK: error: offset out of range
 #CHECK: lghrl %r0, 1
 #CHECK: error: offset out of range

 #CHECK: lhh %r0, 0
 
   lhh %r0, 0
 
 #CHECK: error: invalid operand
 #CHECK: lhi %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: lhi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: lhi %r0, foo
 
   lhi %r0, -32769
   lhi %r0, 32768
-  lhi %r0, foo
 
 #CHECK: error: offset out of range
 #CHECK: lhrl  %r0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: lhrl  %r0, -1
 #CHECK: error: offset out of range
 #CHECK: lhrl  %r0, 1
 #CHECK: error: offset out of range
#CHECK: mfy %r1, 0
   mfy %r0, -524289
   mfy %r0, 524288
   mfy %r1, 0
 
 #CHECK: error: invalid operand
 #CHECK: mghi  %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: mghi  %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: mghi  %r0, foo
 
   mghi  %r0, -32769
   mghi  %r0, 32768
-  mghi  %r0, foo
 
 #CHECK: error: invalid operand
 #CHECK: mh  %r0, -1
 #CHECK: error: invalid operand
 #CHECK: mh  %r0, 4096
 
   mh  %r0, -1
   mh  %r0, 4096
 
 #CHECK: error: invalid operand
 #CHECK: mhi %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: mhi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: mhi %r0, foo
 
   mhi %r0, -32769
   mhi %r0, 32768
-  mhi %r0, foo
 
 #CHECK: error: invalid operand
 #CHECK: mhy %r0, -524289
 #CHECK: error: invalid operand
 #CHECK: mhy %r0, 524288
 
   mhy %r0, -524289
   mhy %r0, 524288

llvm/test/MC/SystemZ/insn-good-z196.s

 #CHECK: aghik %r0, %r0, -32768        # encoding: [0xec,0x00,0x80,0x00,0x00,0xd9]
 #CHECK: aghik %r0, %r0, -1            # encoding: [0xec,0x00,0xff,0xff,0x00,0xd9]
 #CHECK: aghik %r0, %r0, 0             # encoding: [0xec,0x00,0x00,0x00,0x00,0xd9]
 #CHECK: aghik %r0, %r0, 1             # encoding: [0xec,0x00,0x00,0x01,0x00,0xd9]
 #CHECK: aghik %r0, %r0, 32767         # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd9]
 #CHECK: aghik %r0, %r15, 0            # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd9]
 #CHECK: aghik %r15, %r0, 0            # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd9]
 #CHECK: aghik %r7, %r8, -16           # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd9]
+#CHECK: aghik %r0, %r1, foo           # encoding: [0xec,0x01,A,A,0x00,0xd9]
 
   aghik %r0, %r0, -32768
   aghik %r0, %r0, -1
   aghik %r0, %r0, 0
   aghik %r0, %r0, 1
   aghik %r0, %r0, 32767
   aghik %r0, %r15, 0
   aghik %r15, %r0, 0
   aghik %r7, %r8, -16
+  aghik %r0, %r1, foo
 
 #CHECK: agrk  %r0, %r0, %r0           # encoding: [0xb9,0xe8,0x00,0x00]
 #CHECK: agrk  %r0, %r0, %r15          # encoding: [0xb9,0xe8,0xf0,0x00]
 #CHECK: agrk  %r0, %r15, %r0          # encoding: [0xb9,0xe8,0x00,0x0f]
 #CHECK: agrk  %r15, %r0, %r0          # encoding: [0xb9,0xe8,0x00,0xf0]
 #CHECK: agrk  %r7, %r8, %r9           # encoding: [0xb9,0xe8,0x90,0x78]
 
   agrk  %r0,%r0,%r0

 #CHECK: ahik  %r0, %r0, -32768        # encoding: [0xec,0x00,0x80,0x00,0x00,0xd8]
 #CHECK: ahik  %r0, %r0, -1            # encoding: [0xec,0x00,0xff,0xff,0x00,0xd8]
 #CHECK: ahik  %r0, %r0, 0             # encoding: [0xec,0x00,0x00,0x00,0x00,0xd8]
 #CHECK: ahik  %r0, %r0, 1             # encoding: [0xec,0x00,0x00,0x01,0x00,0xd8]
 #CHECK: ahik  %r0, %r0, 32767         # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd8]
 #CHECK: ahik  %r0, %r15, 0            # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd8]
 #CHECK: ahik  %r15, %r0, 0            # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd8]
 #CHECK: ahik  %r7, %r8, -16           # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd8]
+#CHECK: ahik  %r0, %r1, foo           # encoding: [0xec,0x01,A,A,0x00,0xd8]
 
   ahik  %r0, %r0, -32768
   ahik  %r0, %r0, -1
   ahik  %r0, %r0, 0
   ahik  %r0, %r0, 1
   ahik  %r0, %r0, 32767
   ahik  %r0, %r15, 0
   ahik  %r15, %r0, 0
   ahik  %r7, %r8, -16
+  ahik  %r0, %r1, foo
 
 #CHECK: aih %r0, -2147483648        # encoding: [0xcc,0x08,0x80,0x00,0x00,0x00]
 #CHECK: aih %r0, -1                 # encoding: [0xcc,0x08,0xff,0xff,0xff,0xff]
 #CHECK: aih %r0, 0                  # encoding: [0xcc,0x08,0x00,0x00,0x00,0x00]
 #CHECK: aih %r0, 1                  # encoding: [0xcc,0x08,0x00,0x00,0x00,0x01]
 #CHECK: aih %r0, 2147483647         # encoding: [0xcc,0x08,0x7f,0xff,0xff,0xff]
 #CHECK: aih %r15, 0                 # encoding: [0xcc,0xf8,0x00,0x00,0x00,0x00]
 

llvm/test/MC/SystemZ/insn-good.s

#CHECK: agfr  %r7, %r8                # encoding: [0xb9,0x18,0x00,0x78]
   agfr  %r7,%r8
 
 #CHECK: aghi  %r0, -32768             # encoding: [0xa7,0x0b,0x80,0x00]
 #CHECK: aghi  %r0, -1                 # encoding: [0xa7,0x0b,0xff,0xff]
 #CHECK: aghi  %r0, 0                  # encoding: [0xa7,0x0b,0x00,0x00]
 #CHECK: aghi  %r0, 1                  # encoding: [0xa7,0x0b,0x00,0x01]
 #CHECK: aghi  %r0, 32767              # encoding: [0xa7,0x0b,0x7f,0xff]
 #CHECK: aghi  %r15, 0                 # encoding: [0xa7,0xfb,0x00,0x00]
+#CHECK: aghi  %r0, foo                # encoding: [0xa7,0x0b,A,A]
 
   aghi  %r0, -32768
   aghi  %r0, -1
   aghi  %r0, 0
   aghi  %r0, 1
   aghi  %r0, 32767
   aghi  %r15, 0
+  aghi  %r0, foo
 
 #CHECK: agr %r0, %r0                # encoding: [0xb9,0x08,0x00,0x00]
 #CHECK: agr %r0, %r15               # encoding: [0xb9,0x08,0x00,0x0f]
 #CHECK: agr %r15, %r0               # encoding: [0xb9,0x08,0x00,0xf0]
 #CHECK: agr %r7, %r8                # encoding: [0xb9,0x08,0x00,0x78]
 
   agr %r0,%r0
   agr %r0,%r15
#CHECK: ah  %r15, 0                 # encoding: [0x4a,0xf0,0x00,0x00]
   ah  %r15, 0
 
 #CHECK: ahi %r0, -32768             # encoding: [0xa7,0x0a,0x80,0x00]
 #CHECK: ahi %r0, -1                 # encoding: [0xa7,0x0a,0xff,0xff]
 #CHECK: ahi %r0, 0                  # encoding: [0xa7,0x0a,0x00,0x00]
 #CHECK: ahi %r0, 1                  # encoding: [0xa7,0x0a,0x00,0x01]
 #CHECK: ahi %r0, 32767              # encoding: [0xa7,0x0a,0x7f,0xff]
 #CHECK: ahi %r15, 0                 # encoding: [0xa7,0xfa,0x00,0x00]
+#CHECK: ahi %r0, foo                # encoding: [0xa7,0x0a,A,A]
 
   ahi %r0, -32768
   ahi %r0, -1
   ahi %r0, 0
   ahi %r0, 1
   ahi %r0, 32767
   ahi %r15, 0
+  ahi %r0, foo
 
 #CHECK: ahy %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x7a]
 #CHECK: ahy %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x7a]
 #CHECK: ahy %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x7a]
 #CHECK: ahy %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x7a]
 #CHECK: ahy %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x7a]
 #CHECK: ahy %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x7a]
 #CHECK: ahy %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x7a]
#CHECK: cgh %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x34]
   cgh %r15, 0
 
 #CHECK: cghi  %r0, -32768             # encoding: [0xa7,0x0f,0x80,0x00]
 #CHECK: cghi  %r0, -1                 # encoding: [0xa7,0x0f,0xff,0xff]
 #CHECK: cghi  %r0, 0                  # encoding: [0xa7,0x0f,0x00,0x00]
 #CHECK: cghi  %r0, 1                  # encoding: [0xa7,0x0f,0x00,0x01]
 #CHECK: cghi  %r0, 32767              # encoding: [0xa7,0x0f,0x7f,0xff]
 #CHECK: cghi  %r15, 0                 # encoding: [0xa7,0xff,0x00,0x00]
+#CHECK: cghi  %r0, foo                # encoding: [0xa7,0x0f,A,A]
 
   cghi  %r0, -32768
   cghi  %r0, -1
   cghi  %r0, 0
   cghi  %r0, 1
   cghi  %r0, 32767
   cghi  %r15, 0
+  cghi  %r0, foo
 
 #CHECK: cghrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x04,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
   cghrl %r0, -0x100000000
 #CHECK: cghrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x04,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL
   cghrl %r0, -2
 #CHECK: cghrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x04,A,A,A,A]
#CHECK: chhsi 4095(%r15), 42          # encoding: [0xe5,0x54,0xff,0xff,0x00,0x2a]
   chhsi 4095(%r15), 42
 
 #CHECK: chi %r0, -32768             # encoding: [0xa7,0x0e,0x80,0x00]
 #CHECK: chi %r0, -1                 # encoding: [0xa7,0x0e,0xff,0xff]
 #CHECK: chi %r0, 0                  # encoding: [0xa7,0x0e,0x00,0x00]
 #CHECK: chi %r0, 1                  # encoding: [0xa7,0x0e,0x00,0x01]
 #CHECK: chi %r0, 32767              # encoding: [0xa7,0x0e,0x7f,0xff]
 #CHECK: chi %r15, 0                 # encoding: [0xa7,0xfe,0x00,0x00]
+#CHECK: chi %r0, foo                # encoding: [0xa7,0x0e,A,A]
 
   chi %r0, -32768
   chi %r0, -1
   chi %r0, 0
   chi %r0, 1
   chi %r0, 32767
   chi %r15, 0
+  chi %r0, foo
 
 #CHECK: chrl  %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x05,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
   chrl  %r0, -0x100000000
 #CHECK: chrl  %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x05,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL
   chrl  %r0, -2
 #CHECK: chrl  %r0, .[[LAB:L.*]] # encoding: [0xc6,0x05,A,A,A,A]

 
 
 #CHECK: lghi  %r0, -32768             # encoding: [0xa7,0x09,0x80,0x00]
 #CHECK: lghi  %r0, -1                 # encoding: [0xa7,0x09,0xff,0xff]
 #CHECK: lghi  %r0, 0                  # encoding: [0xa7,0x09,0x00,0x00]
 #CHECK: lghi  %r0, 1                  # encoding: [0xa7,0x09,0x00,0x01]
 #CHECK: lghi  %r0, 32767              # encoding: [0xa7,0x09,0x7f,0xff]
 #CHECK: lghi  %r15, 0                 # encoding: [0xa7,0xf9,0x00,0x00]
+#CHECK: lghi  %r14, foo               # encoding: [0xa7,0xe9,A,A]
 
   lghi  %r0, -32768
   lghi  %r0, -1
   lghi  %r0, 0
   lghi  %r0, 1
   lghi  %r0, 32767
   lghi  %r15, 0
+  lghi  %r14, foo
 
 #CHECK: lghr  %r0, %r15               # encoding: [0xb9,0x07,0x00,0x0f]
 #CHECK: lghr  %r7, %r8                # encoding: [0xb9,0x07,0x00,0x78]
 #CHECK: lghr  %r15, %r0               # encoding: [0xb9,0x07,0x00,0xf0]
 
   lghr  %r0, %r15
   lghr  %r7, %r8
   lghr  %r15, %r0
#CHECK: lh  %r15, 0                 # encoding: [0x48,0xf0,0x00,0x00]
   lh  %r15, 0
 
 #CHECK: lhi %r0, -32768             # encoding: [0xa7,0x08,0x80,0x00]
 #CHECK: lhi %r0, -1                 # encoding: [0xa7,0x08,0xff,0xff]
 #CHECK: lhi %r0, 0                  # encoding: [0xa7,0x08,0x00,0x00]
 #CHECK: lhi %r0, 1                  # encoding: [0xa7,0x08,0x00,0x01]
 #CHECK: lhi %r0, 32767              # encoding: [0xa7,0x08,0x7f,0xff]
 #CHECK: lhi %r15, 0                 # encoding: [0xa7,0xf8,0x00,0x00]
+#CHECK: lhi %r0, foo                # encoding: [0xa7,0x08,A,A]
 
   lhi %r0, -32768
   lhi %r0, -1
   lhi %r0, 0
   lhi %r0, 1
   lhi %r0, 32767
   lhi %r15, 0
+  lhi %r0, foo
 
 #CHECK: lhr %r0, %r15               # encoding: [0xb9,0x27,0x00,0x0f]
 #CHECK: lhr %r7, %r8                # encoding: [0xb9,0x27,0x00,0x78]
 #CHECK: lhr %r15, %r0               # encoding: [0xb9,0x27,0x00,0xf0]
 
   lhr %r0, %r15
   lhr %r7, %r8
   lhr %r15, %r0
#CHECK: mfy %r14, 0                 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x5c]
   mfy %r14, 0
 
 #CHECK: mghi  %r0, -32768             # encoding: [0xa7,0x0d,0x80,0x00]
 #CHECK: mghi  %r0, -1                 # encoding: [0xa7,0x0d,0xff,0xff]
 #CHECK: mghi  %r0, 0                  # encoding: [0xa7,0x0d,0x00,0x00]
 #CHECK: mghi  %r0, 1                  # encoding: [0xa7,0x0d,0x00,0x01]
 #CHECK: mghi  %r0, 32767              # encoding: [0xa7,0x0d,0x7f,0xff]
 #CHECK: mghi  %r15, 0                 # encoding: [0xa7,0xfd,0x00,0x00]
+#CHECK: mghi  %r0, foo                # encoding: [0xa7,0x0d,A,A]
 
   mghi  %r0, -32768
   mghi  %r0, -1
   mghi  %r0, 0
   mghi  %r0, 1
   mghi  %r0, 32767
   mghi  %r15, 0
+  mghi  %r0, foo
 
 #CHECK: mh  %r0, 0                  # encoding: [0x4c,0x00,0x00,0x00]
 #CHECK: mh  %r0, 4095               # encoding: [0x4c,0x00,0x0f,0xff]
 #CHECK: mh  %r0, 0(%r1)             # encoding: [0x4c,0x00,0x10,0x00]
 #CHECK: mh  %r0, 0(%r15)            # encoding: [0x4c,0x00,0xf0,0x00]
 #CHECK: mh  %r0, 4095(%r1,%r15)     # encoding: [0x4c,0x01,0xff,0xff]
 #CHECK: mh  %r0, 4095(%r15,%r1)     # encoding: [0x4c,0x0f,0x1f,0xff]
 #CHECK: mh  %r15, 0                 # encoding: [0x4c,0xf0,0x00,0x00]
 
   mh  %r0, 0
   mh  %r0, 4095
   mh  %r0, 0(%r1)
   mh  %r0, 0(%r15)
   mh  %r0, 4095(%r1,%r15)
   mh  %r0, 4095(%r15,%r1)
   mh  %r15, 0
 
 #CHECK: mhi %r0, -32768             # encoding: [0xa7,0x0c,0x80,0x00]
 #CHECK: mhi %r0, -1                 # encoding: [0xa7,0x0c,0xff,0xff]
 #CHECK: mhi %r0, 0                  # encoding: [0xa7,0x0c,0x00,0x00]
 #CHECK: mhi %r0, 1                  # encoding: [0xa7,0x0c,0x00,0x01]
 #CHECK: mhi %r0, 32767              # encoding: [0xa7,0x0c,0x7f,0xff]
 #CHECK: mhi %r15, 0                 # encoding: [0xa7,0xfc,0x00,0x00]
+#CHECK: mhi %r0, foo                # encoding: [0xa7,0x0c,A,A]
 
   mhi %r0, -32768
   mhi %r0, -1
   mhi %r0, 0
   mhi %r0, 1
   mhi %r0, 32767
   mhi %r15, 0
+  mhi %r0, foo
 
 #CHECK: mhy %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x7c]
 #CHECK: mhy %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x7c]
 #CHECK: mhy %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x7c]
 #CHECK: mhy %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x7c]
 #CHECK: mhy %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x7c]
 #CHECK: mhy %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x7c]
 #CHECK: mhy %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x7c]

llvm/utils/TableGen/CodeEmitterGen.cpp

 
 public:
   CodeEmitterGen(RecordKeeper &R) : Records(R) {}
 
   void run(raw_ostream &o);
 
 private:
   int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
-  std::string getInstructionCase(Record *R, CodeGenTarget &Target);
-  std::string getInstructionCaseForEncoding(Record *R, Record *EncodingDef,
-                                            CodeGenTarget &Target);
+  std::pair<std::string, std::string>
+  getInstructionCases(Record *R, CodeGenTarget &Target);
+  void addInstructionCasesForEncoding(Record *R, Record *EncodingDef,
+                                      CodeGenTarget &Target, std::string &Case,
+                                      std::string &BitOffsetCase);
   bool addCodeToMergeInOperand(Record *R, BitsInit *BI,
-                               const std::string &VarName,
-                               std::string &Case, CodeGenTarget &Target);
+                               const std::string &VarName, std::string &Case,
+                               std::string &BitOffsetCase,
+                               CodeGenTarget &Target);
 
   void emitInstructionBaseValues(
       raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
       CodeGenTarget &Target, int HwMode = -1);
+  void
+  emitCaseMap(raw_ostream &o,
+              const std::map<std::string, std::vector<std::string>> &CaseMap);
   unsigned BitWidth = 0u;
   bool UseAPInt = false;
 };
 
 // If the VarBitInit at position 'bit' matches the specified variable then
 // return the variable bit position.  Otherwise return -1.
 int CodeEmitterGen::getVariableBit(const std::string &VarName,
                                    BitsInit *BI, int bit) {
   if (VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
     if (VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
       if (VI->getName() == VarName)
         return VBI->getBitNum();
   } else if (VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
     if (VI->getName() == VarName)
       return 0;
   }
 
   return -1;
 }
 
 // Returns true if it succeeds, false if an error.
 bool CodeEmitterGen::addCodeToMergeInOperand(Record *R, BitsInit *BI,
                                              const std::string &VarName,
                                              std::string &Case,
+                                             std::string &BitOffsetCase,
                                              CodeGenTarget &Target) {
   CodeGenInstruction &CGI = Target.getInstruction(R);
 
   // Determine if VarName actually contributes to the Inst encoding.
   int bit = BI->getNumBits()-1;
 
   // Scan for a bit that this contributed to.
   for (; bit >= 0; ) {
for (--tmpBit; tmpBit >= 0;) {
       if (varBit == -1 || varBit != (beginVarBit - N))
         break;
       ++N;
       --tmpBit;
     }
     ++numOperandLits;
   }
 
+  bool BitOffsetCaseEmitted = false;
   for (; bit >= 0; ) {
     int varBit = getVariableBit(VarName, BI, bit);
     
     // If this bit isn't from a variable, skip it.
     if (varBit == -1) {
       --bit;
       continue;
     }
-    
     // Figure out the consecutive range of bits covered by this operand, in
     // order to generate better encoding code.
     int beginInstBit = bit;
     int beginVarBit = varBit;
     int N = 1;
     for (--bit; bit >= 0;) {
       varBit = getVariableBit(VarName, BI, bit);
       if (varBit == -1 || varBit != (beginVarBit - N)) break;
       ++N;
       --bit;
     }
 
     std::string maskStr;
     int opShift;
 
     unsigned loBit = beginVarBit - N + 1;
     unsigned hiBit = loBit + N;
     unsigned loInstBit = beginInstBit - N + 1;
+    if (!BitOffsetCaseEmitted) {
+      BitOffsetCase += "      case " + utostr(OpIdx) + ":\n";
+      BitOffsetCase += "        return " +
+                       utostr(BI->getNumBits() - beginInstBit - 1) + ";\n";
+      BitOffsetCaseEmitted = true;
+    }
     if (UseAPInt) {
       std::string extractStr;
       if (N >= 64) {
         extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " +
                      itostr(loBit) + ")";
         Case += "      Value.insertBits(" + extractStr + ", " +
                 itostr(loInstBit) + ");\n";
       } else {
if (UseAPInt) {
           Case += "      Value |= (op & " + maskStr + ");\n";
         }
       }
     }
   }
   return true;
 }
 
-std::string CodeEmitterGen::getInstructionCase(Record *R,
-                                               CodeGenTarget &Target) {
-  std::string Case;
+std::pair<std::string, std::string>
+CodeEmitterGen::getInstructionCases(Record *R, CodeGenTarget &Target) {
+  std::string Case, BitOffsetCase;
+
+  auto append = [&](const char *S) {
+    Case += S;
+    BitOffsetCase += S;
+  };
+
   if (const RecordVal *RV = R->getValue("EncodingInfos")) {
     if (auto *DI = dyn_cast_or_null<DefInit>(RV->getValue())) {
       const CodeGenHwModes &HWM = Target.getHwModes();
       EncodingInfoByHwMode EBM(DI->getDef(), HWM);
-      Case += "      switch (HwMode) {\n";
-      Case += "      default: llvm_unreachable(\"Unhandled HwMode\");\n";
+      append("      switch (HwMode) {\n");
+      append("      default: llvm_unreachable(\"Unhandled HwMode\");\n");
       for (auto &KV : EBM) {
-        Case += "      case " + itostr(KV.first) + ": {\n";
-        Case += getInstructionCaseForEncoding(R, KV.second, Target);
-        Case += "      break;\n";
-        Case += "      }\n";
+        append(("      case " + itostr(KV.first) + ": {\n").c_str());
+        addInstructionCasesForEncoding(R, KV.second, Target, Case,
+                                       BitOffsetCase);
+        append("      break;\n");
+        append("      }\n");
       }
-      Case += "      }\n";
-      return Case;
+      append("      }\n");
+      return std::make_pair(std::move(Case), std::move(BitOffsetCase));
     }
   }
-  return getInstructionCaseForEncoding(R, R, Target);
+  addInstructionCasesForEncoding(R, R, Target, Case, BitOffsetCase);
+  return std::make_pair(std::move(Case), std::move(BitOffsetCase));
 }
 
-std::string CodeEmitterGen::getInstructionCaseForEncoding(Record *R, Record *EncodingDef,
-                                                          CodeGenTarget &Target) {
-  std::string Case;
+void CodeEmitterGen::addInstructionCasesForEncoding(
+    Record *R, Record *EncodingDef, CodeGenTarget &Target, std::string &Case,
+    std::string &BitOffsetCase) {
   BitsInit *BI = EncodingDef->getValueAsBitsInit("Inst");
 
   // Loop over all of the fields in the instruction, determining which are the
   // operands to the instruction.
   bool Success = true;
+  BitOffsetCase += "      switch (OpNum) {\n";
   for (const RecordVal &RV : EncodingDef->getValues()) {
     // Ignore fixed fields in the record, we're looking for values like:
     //    bits<5> RST = { ?, ?, ?, ?, ? };
     if (RV.isNonconcreteOK() || RV.getValue()->isComplete())
       continue;
 
-    Success &=
-        addCodeToMergeInOperand(R, BI, std::string(RV.getName()),
-                                Case, Target);
+    Success &= addCodeToMergeInOperand(R, BI, std::string(RV.getName()), Case,
+                                       BitOffsetCase, Target);
   }
+  BitOffsetCase += "      }\n";
 
   if (!Success) {
     // Dump the record, so we can see what's going on...
     std::string E;
     raw_string_ostream S(E);
     S << "Dumping record for previous error:\n";
     S << *R;
     PrintNote(E);
   }
 
   StringRef PostEmitter = R->getValueAsString("PostEncoderMethod");
   if (!PostEmitter.empty()) {
     Case += "      Value = ";
     Case += PostEmitter;
     Case += "(MI, Value";
     Case += ", STI";
     Case += ");\n";
   }
-  
-  return Case;
 }
 
 static void emitInstBits(raw_ostream &OS, const APInt &Bits) {
   for (unsigned I = 0; I < Bits.getNumWords(); ++I)
     OS << ((I > 0) ? ", " : "") << "UINT64_C(" << utostr(Bits.getRawData()[I])
        << ")";
 }
 
for (const CodeGenInstruction *CGI : NumberedInstructions) {
     }
     o << "    ";
     emitInstBits(o, Value);
     o << "," << '\t' << "// " << R->getName() << "\n";
   }
   o << "    UINT64_C(0)\n  };\n";
 }
 
+void CodeEmitterGen::emitCaseMap(
+    raw_ostream &o,
+    const std::map<std::string, std::vector<std::string>> &CaseMap) {
+  std::map<std::string, std::vector<std::string>>::const_iterator IE, EE;
+  for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
+    const std::string &Case = IE->first;
+    const std::vector<std::string> &InstList = IE->second;
+
+    for (int i = 0, N = InstList.size(); i < N; i++) {
+      if (i)
+        o << "\n";
+      o << "    case " << InstList[i] << ":";
+    }
+    o << " {\n";
+    o << Case;
+    o << "      break;\n"
+      << "    }\n";
+  }
+}
+
 void CodeEmitterGen::run(raw_ostream &o) {
   emitSourceFileHeader("Machine Code Emitter", o);
 
   CodeGenTarget Target(Records);
   std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
 
   // For little-endian instruction bit encodings, reverse the bit order
   Target.reverseBitsForLittleEndianEncoding();
if (!HwModes.empty()) {
         o << "  case " << I << ": InstBits = InstBits_" << HWM.getMode(I).Name
           << "; break;\n";
       }
       o << "  };\n";
     }
 
     // Map to accumulate all the cases.
     std::map<std::string, std::vector<std::string>> CaseMap;
+    std::map<std::string, std::vector<std::string>> BitOffsetCaseMap;
 
     // Construct all cases statement for each opcode
     for (Record *R : Insts) {
       if (R->getValueAsString("Namespace") == "TargetOpcode" ||
           R->getValueAsBit("isPseudo"))
         continue;
       std::string InstName =
           (R->getValueAsString("Namespace") + "::" + R->getName()).str();
-      std::string Case = getInstructionCase(R, Target);
+      std::string Case, BitOffsetCase;
+      std::tie(Case, BitOffsetCase) = getInstructionCases(R, Target);
 
-      CaseMap[Case].push_back(std::move(InstName));
+      CaseMap[Case].push_back(InstName);
+      BitOffsetCaseMap[BitOffsetCase].push_back(std::move(InstName));
     }
 
     // Emit initial function code
     if (UseAPInt) {
       int NumWords = APInt::getNumWords(BitWidth);
       o << "  const unsigned opcode = MI.getOpcode();\n"
         << "  if (Scratch.getBitWidth() != " << BitWidth << ")\n"
         << "    Scratch = Scratch.zext(" << BitWidth << ");\n"
         << "  Inst = APInt(" << BitWidth << ", ArrayRef(InstBits + opcode * "
         << NumWords << ", " << NumWords << "));\n"
         << "  APInt &Value = Inst;\n"
         << "  APInt &op = Scratch;\n"
         << "  switch (opcode) {\n";
     } else {
       o << "  const unsigned opcode = MI.getOpcode();\n"
         << "  uint64_t Value = InstBits[opcode];\n"
         << "  uint64_t op = 0;\n"
         << "  (void)op;  // suppress warning\n"
         << "  switch (opcode) {\n";
     }
 
     // Emit each case statement
-    std::map<std::string, std::vector<std::string>>::iterator IE, EE;
-    for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
-      const std::string &Case = IE->first;
-      std::vector<std::string> &InstList = IE->second;
-
-      for (int i = 0, N = InstList.size(); i < N; i++) {
-        if (i)
-          o << "\n";
-        o << "    case " << InstList[i] << ":";
-      }
-      o << " {\n";
-      o << Case;
-      o << "      break;\n"
-        << "    }\n";
-    }
+    emitCaseMap(o, CaseMap);
 
     // Default case: unhandled opcode
     o << "  default:\n"
       << "    std::string msg;\n"
       << "    raw_string_ostream Msg(msg);\n"
       << "    Msg << \"Not supported instr: \" << MI;\n"
       << "    report_fatal_error(Msg.str().c_str());\n"
       << "  }\n";
     if (UseAPInt)
       o << "  Inst = Value;\n";
     else
       o << "  return Value;\n";
     o << "}\n\n";
+
+    o << "#ifdef GET_OPERAND_BIT_OFFSET\n"
+      << "#undef GET_OPERAND_BIT_OFFSET\n\n"
+      << "uint32_t " << Target.getName()
+      << "MCCodeEmitter::getOperandBitOffset(const MCInst &MI,\n"
+      << "    unsigned OpNum,\n"
+      << "    const MCSubtargetInfo &STI) const {\n"
+      << "  switch (MI.getOpcode()) {\n";
+    emitCaseMap(o, BitOffsetCaseMap);
+    o << "  }\n"
+      << "  std::string msg;\n"
+      << "  raw_string_ostream Msg(msg);\n"
+      << "  Msg << \"Not supported instr[opcode]: \" << MI << \"[\" << OpNum "
+         "<< \"]\";\n"
+      << "  report_fatal_error(Msg.str().c_str());\n"
+      << "}\n\n"
+      << "#endif // GET_OPERAND_ENCODING_INFO\n\n";
   }
 }
 
 } // end anonymous namespace
 
 static TableGen::Emitter::OptClass<CodeEmitterGen>
     X("gen-emitter", "Generate machine code emitter");