[SystemZ] Allow symbols in immediate asm operands

[iii]

Summary

Currently mentioning any symbols in immediate asm operands is not
supported, for example:

error: invalid operand for instruction
lghi %r4,foo_end-foo

The immediate problem is that is*Imm() and print*Operand() functions do
not accept MCExprs, but simply relaxing these checks is not enough:
after symbol addresses are computed, range checks need to run against
resolved values.

Add a number of SystemZ::FixupKind members for each kind of immediate
value and process them in SystemZMCAsmBackend::applyFixup(). Only
perform the range checks, do not change anything.

In order to create fixups, one needs to know the operand offsets.
Unfortunately the existing LLVM infrastructure does not provide this
information. Implement generating getOperandBitOffset(), which provides
this information. It does not return useful values for multi-lit
operands, such as SystemZ vector registers, but this is not important
for its intended use case.

Finally, adjust the tests: move previously failing cases like the
one shown above out of insn-bad.s.

[iii]

• Remove an unused variable.
• Remove an irrelevant whitespace change.

[uweigand]

Thanks for working on that, Ilya! If we do allow symbols in immediates (and I agree we should), we should then also handle the case where they don't completely resolve, but result in relocations. This should be straightforward to add once we already have fixups. In addition to R_S390_12 (which is already emitted, and should be used for the U12Imm cases as well), we do support 1-, 2-, 4-, and 8-byte relocations. The sub-byte (U1Imm, U2Imm, U3Imm, U4Imm) and .insn opcode (U48Imm) cases don't have corresponding relocations, but I believe for those we should not allow any symbolic expressions anyway.

Also, it would be good to have tests for the PC-relative cases (symbol-.), both where those resolve at assemble time (symbol in the current section), and where a PC-relative reloc is required (symbol in another section).

Finally, for the tablegen changes I'd prefer to have someone more familiar with that code base to review it. Maybe we can split this off into a separate diff (possibly combined with a getDispOpValue change to make use of it for displacements)?

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp

88

I don't think we should have the "imm" markup for expressions.

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

173

I think this should rather go into getDispOpValue ... a displacement is in fact simply an immediate.

The getOperandBitOffset logic should allow us to replace the MemOpsEmitted hack we currently have there, and then generalize it to all immediates.

The getMachineOpValue will then be only used for registers.

[iii]

• Emit relocations.
• Add various tests.
• Remove "imm" markup for expressions.
• Move the isExpr() logic to getDispOpValue().

[iii]

I've added pc-relative tests, but only for PC32. For PC32DBL I tried (src-.)/2, but the common code does not recognize division as a relocatable expression, and does not let the backend to handle it either. GAS does not handle it either though, so it's probably fine:

lgfi %r0,(foo-.)/2
1.s:1: Error: invalid operands (*UND* and .text sections) for `-'

[uweigand]

Thanks for the updates, looking really good now. Just a few cosmetic comments inline.

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

65–66

Can we rename this to something like getImmOpValue - it's no longer just displacements. Also the comment should be updated.

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h

24–37

Can we integrate the handling of displacements into the new scheme and use FK_390_U12Imm and FK_390_S20Imm here (and elsewhere)? In generals, displacements should just be a type of immediates.

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp

46–63

Would be nicer to reformat those cases as well so that all use the same style.

llvm/test/MC/SystemZ/fixups.s

8

Would it make sense to add CHECK-DIS lines to the existing tests as well?

[uweigand]

In D154899#4518775, @iii wrote:

I've added pc-relative tests, but only for PC32. For PC32DBL I tried (src-.)/2, but the common code does not recognize division as a relocatable expression, and does not let the backend to handle it either. GAS does not handle it either though, so it's probably fine:

Agreed, I think this is fine. The DBL relocations really are intended for the LARL-type instructions, where the /2 is implicit.

[iii]

• Rename getDispOpValue() to getImmOpValue().
• Rename FK_390_12 to FK_390_U12Imm and FK_390_20 to FK_390_S20Imm.
• Reformat.

llvm/test/MC/SystemZ/fixups.s

8

For the new tests it's important, because it allows us to check the resolved immediate value. The existing tests depend relocations, so it's going to be only zeroes anyway.

[uweigand]

LGTM, thanks!

llvm/test/MC/SystemZ/fixups.s

8

OK, makes sense.

llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

unsigned getReg() const override {
     return Reg.Num;
   }
 
   // Immediate operands.
   bool isImm() const override {
     return Kind == KindImm;
   }
   bool isImm(int64_t MinValue, int64_t MaxValue) const {
-    return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
+    return Kind == KindImm && inRange(Imm, MinValue, MaxValue, true);
   }
   const MCExpr *getImm() const {
     assert(Kind == KindImm && "Not an immediate");
     return Imm;
   }
 
   // Immediate operands with optional TLS symbol.
   bool isImmTLS() const {

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp

void SystemZInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                    raw_ostream &O) {
   printInstruction(MI, Address, O);
   printAnnotation(O, Annot);
 }
 
 template <unsigned N>
 void SystemZInstPrinter::printUImmOperand(const MCInst *MI, int OpNum,
                                           raw_ostream &O) {
-  int64_t Value = MI->getOperand(OpNum).getImm();
+  const MCOperand &MO = MI->getOperand(OpNum);
+  if (MO.isExpr()) {
+    O << *MO.getExpr();
+    return;
+  }
+  uint64_t Value = static_cast<uint64_t>(MO.getImm());
   assert(isUInt<N>(Value) && "Invalid uimm argument");
   O << markup("<imm:") << Value << markup(">");
 }
 
 template <unsigned N>
 void SystemZInstPrinter::printSImmOperand(const MCInst *MI, int OpNum,
                                           raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNum);
+  if (MO.isExpr()) {
+    O << *MO.getExpr();
+    return;
+  }
   int64_t Value = MI->getOperand(OpNum).getImm();
   assert(isInt<N>(Value) && "Invalid simm argument");
   O << markup("<imm:") << Value << markup(">");
 }
 
 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum,
                                            raw_ostream &O) {
   printUImmOperand<1>(MI, OpNum, O);

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp

static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value,
   auto handlePCRelFixupValue = [&](unsigned W) -> uint64_t {
     if (Value % 2 != 0)
       Ctx.reportError(Fixup.getLoc(), "Non-even PC relative offset.");
     if (!checkFixupInRange(minIntN(W) * 2, maxIntN(W) * 2))
       return 0;
     return (int64_t)Value / 2;
   };
 
+  auto handleImmValue = [&](bool IsSigned, unsigned W) -> uint64_t {
+    if (!(IsSigned ? checkFixupInRange(minIntN(W), maxIntN(W))
+                   : checkFixupInRange(0, maxUIntN(W))))
+      return 0;
+    return Value;
+  };
+
   switch (unsigned(Kind)) {
   case SystemZ::FK_390_PC12DBL:
     return handlePCRelFixupValue(12);
   case SystemZ::FK_390_PC16DBL:
     return handlePCRelFixupValue(16);
   case SystemZ::FK_390_PC24DBL:
     return handlePCRelFixupValue(24);
   case SystemZ::FK_390_PC32DBL:
     return handlePCRelFixupValue(32);
 
-  case SystemZ::FK_390_12:
-    if (!checkFixupInRange(0, maxUIntN(12)))
-      return 0;
-    return Value;
+  case SystemZ::FK_390_TLS_CALL:
 
-  case SystemZ::FK_390_20: {
-    if (!checkFixupInRange(minIntN(20), maxIntN(20)))
-      return 0;
+  case SystemZ::FK_390_S8Imm:
+    return handleImmValue(true, 8);
+  case SystemZ::FK_390_S16Imm:
+    return handleImmValue(true, 16);
+  case SystemZ::FK_390_S20Imm: {
+    Value = handleImmValue(true, 20);
+    // S20Imm is used only for signed 20-bit displacements.
     // The high byte of a 20 bit displacement value comes first.
     uint64_t DLo = Value & 0xfff;
     uint64_t DHi = (Value >> 12) & 0xff;
     return (DLo << 8) | DHi;
   }
-
-  case SystemZ::FK_390_TLS_CALL:
-    return 0;
+  case SystemZ::FK_390_S32Imm:
+    return handleImmValue(true, 32);
+  case SystemZ::FK_390_U1Imm:
+    return handleImmValue(false, 1);
+  case SystemZ::FK_390_U2Imm:
+    return handleImmValue(false, 2);
+  case SystemZ::FK_390_U3Imm:
+    return handleImmValue(false, 3);
+  case SystemZ::FK_390_U4Imm:
+    return handleImmValue(false, 4);
+  case SystemZ::FK_390_U8Imm:
+    return handleImmValue(false, 8);
+  case SystemZ::FK_390_U12Imm:
+    return handleImmValue(false, 12);
+  case SystemZ::FK_390_U16Imm:
+    return handleImmValue(false, 16);
+  case SystemZ::FK_390_U32Imm:
+    return handleImmValue(false, 32);
+  case SystemZ::FK_390_U48Imm:
+    return handleImmValue(false, 48);
   }
 
   llvm_unreachable("Unknown fixup kind!");
 }
 
 namespace {
 class SystemZMCAsmBackend : public MCAsmBackend {
   uint8_t OSABI;
#undef ELF_RELOC
       .Default(-1u);
   if (Type != -1u)
     return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
   return std::nullopt;
 }
 
 const MCFixupKindInfo &
 SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
-  const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = {
-    { "FK_390_PC12DBL",  4, 12, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_390_PC16DBL",  0, 16, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_390_PC24DBL",  0, 24, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_390_PC32DBL",  0, 32, MCFixupKindInfo::FKF_IsPCRel },
-    { "FK_390_TLS_CALL", 0, 0, 0 },
-    { "FK_390_12",       4, 12, 0 },
-    { "FK_390_20",       4, 20, 0 }
-  };
-
   // Fixup kinds from .reloc directive are like R_390_NONE. They
   // do not require any extra processing.
   if (Kind >= FirstLiteralRelocationKind)
     return MCAsmBackend::getFixupKindInfo(FK_NONE);
 
   if (Kind < FirstTargetFixupKind)
     return MCAsmBackend::getFixupKindInfo(Kind);
 
   assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
          "Invalid kind!");
-  return Infos[Kind - FirstTargetFixupKind];
+  return SystemZ::MCFixupKindInfos[Kind - FirstTargetFixupKind];
 }
 
 bool SystemZMCAsmBackend::shouldForceRelocation(const MCAssembler &,
             const MCFixup &Fixup,
             const MCValue &) {
   return Fixup.getKind() >= FirstLiteralRelocationKind;
 }
 

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

private:
   uint32_t getOperandBitOffset(const MCInst &MI, unsigned OpNum,
                                const MCSubtargetInfo &STI) const;
 
   // Called by the TableGen code to get the binary encoding of operand
   // MO in MI.  Fixups is the list of fixups against MI.
   uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
 
-  // Return the displacement value for the OpNum operand. If it is a symbol,
-  // add a fixup for it and return 0.
-  uint64_t getDispOpValue(const MCInst &MI, unsigned OpNum,
-                          SmallVectorImpl<MCFixup> &Fixups,
-                          const MCSubtargetInfo &STI, unsigned OpSize,
-                          SystemZ::FixupKind Kind) const;
-
-  // Called by the TableGen code to get the binary encoding of an address.
-  // The index or length, if any, is encoded first, followed by the base,
-  // followed by the displacement.  In a 20-bit displacement,
-  // the low 12 bits are encoded before the high 8 bits.
-  template <unsigned N>
-  uint64_t getLenEncoding(const MCInst &MI, unsigned OpNum,
-                          SmallVectorImpl<MCFixup> &Fixups,
-                          const MCSubtargetInfo &STI) const;
-  uint64_t getDisp12Encoding(const MCInst &MI, unsigned OpNum,
-                             SmallVectorImpl<MCFixup> &Fixups,
-                             const MCSubtargetInfo &STI) const;
-  uint64_t getDisp20Encoding(const MCInst &MI, unsigned OpNum,
-                             SmallVectorImpl<MCFixup> &Fixups,
-                             const MCSubtargetInfo &STI) const;
+  // Return the encoded immediate value for the OpNum operand. If it is a
+  // symbol, add a fixup for it and return 0.
+  template <SystemZ::FixupKind Kind>
+  uint64_t getImmOpValue(const MCInst &MI, unsigned OpNum,
+
+  // Called by the TableGen code to get the binary encoding of a length value.
+  // Length values are encoded by subtracting 1 from the actual value.
+  template <SystemZ::FixupKind Kind>
+  uint64_t getLenEncoding(const MCInst &MI, unsigned OpNum,
 
   // Operand OpNum of MI needs a PC-relative fixup of kind Kind at
   // Offset bytes from the start of MI.  Add the fixup to Fixups
   // and return the in-place addend, which since we're a RELA target
   // is always 0.  If AllowTLS is true and optional operand OpNum + 1
   // is present, also emit a TLS call fixup for it.
   uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
                             SmallVectorImpl<MCFixup> &Fixups,

 }
 
 uint64_t SystemZMCCodeEmitter::
 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                   SmallVectorImpl<MCFixup> &Fixups,
                   const MCSubtargetInfo &STI) const {
   if (MO.isReg())
     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
+  // SystemZAsmParser::parseAnyRegister() produces KindImm when registers are
+  // specified as integers.
   if (MO.isImm())
     return static_cast<uint64_t>(MO.getImm());
   llvm_unreachable("Unexpected operand type!");
 }
 
-uint64_t SystemZMCCodeEmitter::getDispOpValue(const MCInst &MI, unsigned OpNum,
-                                              SmallVectorImpl<MCFixup> &Fixups,
-                                              const MCSubtargetInfo &STI,
-                                              unsigned OpSize,
-                                              SystemZ::FixupKind Kind) const {
+template <SystemZ::FixupKind Kind>
+uint64_t SystemZMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNum,
+                                             const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNum);
   if (MO.isImm())
     return static_cast<uint64_t>(MO.getImm());
   if (MO.isExpr()) {
     unsigned MIBitSize = MCII.get(MI.getOpcode()).getSize() * 8;
     uint32_t RawBitOffset = getOperandBitOffset(MI, OpNum, STI);
-    uint32_t BitOffset = MIBitSize - RawBitOffset - OpSize;
+    unsigned OpBitSize =
+        SystemZ::MCFixupKindInfos[Kind - FirstTargetFixupKind].TargetSize;
+    uint32_t BitOffset = MIBitSize - RawBitOffset - OpBitSize;
     Fixups.push_back(MCFixup::create(BitOffset >> 3, MO.getExpr(),
                                      (MCFixupKind)Kind, MI.getLoc()));
     assert(Fixups.size() <= 2 && "More than two memory operands in MI?");
     return 0;
   }
   llvm_unreachable("Unexpected operand type!");
 }
 
-template <unsigned N>
+template <SystemZ::FixupKind Kind>
 uint64_t
 SystemZMCCodeEmitter::getLenEncoding(const MCInst &MI, unsigned OpNum,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {
-  return getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI) - 1;
-}
-
-uint64_t
-SystemZMCCodeEmitter::getDisp12Encoding(const MCInst &MI, unsigned OpNum,
-                                        SmallVectorImpl<MCFixup> &Fixups,
-                                        const MCSubtargetInfo &STI) const {
-  return getDispOpValue(MI, OpNum, Fixups, STI, 12,
-                        SystemZ::FixupKind::FK_390_12);
-}
-
-uint64_t
-SystemZMCCodeEmitter::getDisp20Encoding(const MCInst &MI, unsigned OpNum,
-                                        SmallVectorImpl<MCFixup> &Fixups,
-                                        const MCSubtargetInfo &STI) const {
-  return getDispOpValue(MI, OpNum, Fixups, STI, 20,
-                        SystemZ::FixupKind::FK_390_20);
+  return getImmOpValue<Kind>(MI, OpNum, Fixups, STI) - 1;
 }
 
 uint64_t
 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        unsigned Kind, int64_t Offset,
                                        bool AllowTLS) const {
   SMLoc Loc = MI.getLoc();

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h

 //===-- SystemZMCFixups.h - SystemZ-specific fixup entries ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCFIXUPS_H
 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCFIXUPS_H
 
 #include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCFixupKindInfo.h"
 
 namespace llvm {
 namespace SystemZ {
 enum FixupKind {
   // These correspond directly to R_390_* relocations.
   FK_390_PC12DBL = FirstTargetFixupKind,
   FK_390_PC16DBL,
   FK_390_PC24DBL,
   FK_390_PC32DBL,
   FK_390_TLS_CALL,
-  FK_390_12,
-  FK_390_20,
+
+  FK_390_S8Imm,
+  FK_390_S16Imm,
+  FK_390_S20Imm,
+  FK_390_S32Imm,
+  FK_390_U1Imm,
+  FK_390_U2Imm,
+  FK_390_U3Imm,
+  FK_390_U4Imm,
+  FK_390_U8Imm,
+  FK_390_U12Imm,
+  FK_390_U16Imm,
+  FK_390_U32Imm,
+  FK_390_U48Imm,
 
   // Marker
   LastTargetFixupKind,
   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
 };
+
+const static MCFixupKindInfo MCFixupKindInfos[SystemZ::NumTargetFixupKinds] = {
+    {"FK_390_PC12DBL", 4, 12, MCFixupKindInfo::FKF_IsPCRel},
+    {"FK_390_PC16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
+    {"FK_390_PC24DBL", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
+    {"FK_390_PC32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+    {"FK_390_TLS_CALL", 0, 0, 0},
+    {"FK_390_S8Imm", 0, 8, 0},
+    {"FK_390_S16Imm", 0, 16, 0},
+    {"FK_390_S20Imm", 4, 20, 0},
+    {"FK_390_S32Imm", 0, 32, 0},
+    {"FK_390_U1Imm", 0, 1, 0},
+    {"FK_390_U2Imm", 0, 2, 0},
+    {"FK_390_U3Imm", 0, 3, 0},
+    {"FK_390_U4Imm", 0, 4, 0},
+    {"FK_390_U8Imm", 0, 8, 0},
+    {"FK_390_U12Imm", 4, 12, 0},
+    {"FK_390_U16Imm", 0, 16, 0},
+    {"FK_390_U32Imm", 0, 32, 0},
+    {"FK_390_U48Imm", 0, 48, 0},
+};
 } // end namespace SystemZ
 } // end namespace llvm
 
 #endif

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp

 
 SystemZObjectWriter::SystemZObjectWriter(uint8_t OSABI)
   : MCELFObjectTargetWriter(/*Is64Bit_=*/true, OSABI, ELF::EM_S390,
                             /*HasRelocationAddend_=*/ true) {}
 
 // Return the relocation type for an absolute value of MCFixupKind Kind.
 static unsigned getAbsoluteReloc(MCContext &Ctx, SMLoc Loc, unsigned Kind) {
   switch (Kind) {
-  case FK_Data_1: return ELF::R_390_8;
-  case FK_Data_2: return ELF::R_390_16;
-  case FK_Data_4: return ELF::R_390_32;
-  case FK_Data_8: return ELF::R_390_64;
-  case SystemZ::FK_390_12: return ELF::R_390_12;
-  case SystemZ::FK_390_20: return ELF::R_390_20;
+  case FK_Data_1:
+  case SystemZ::FK_390_U8Imm:
+  case SystemZ::FK_390_S8Imm:
+    return ELF::R_390_8;
+  case SystemZ::FK_390_U12Imm:
+    return ELF::R_390_12;
+  case FK_Data_2:
+  case SystemZ::FK_390_U16Imm:
+  case SystemZ::FK_390_S16Imm:
+    return ELF::R_390_16;
+  case SystemZ::FK_390_S20Imm:
+    return ELF::R_390_20;
+  case FK_Data_4:
+  case SystemZ::FK_390_U32Imm:
+  case SystemZ::FK_390_S32Imm:
+    return ELF::R_390_32;
+  case FK_Data_8:
+    return ELF::R_390_64;
   }
   Ctx.reportError(Loc, "Unsupported absolute address");
   return 0;
 }
 
 // Return the relocation type for a PC-relative value of MCFixupKind Kind.
 static unsigned getPCRelReloc(MCContext &Ctx, SMLoc Loc, unsigned Kind) {
   switch (Kind) {
-  case FK_Data_2:                return ELF::R_390_PC16;
-  case FK_Data_4:                return ELF::R_390_PC32;
-  case FK_Data_8:                return ELF::R_390_PC64;
-  case SystemZ::FK_390_PC12DBL:  return ELF::R_390_PC12DBL;
-  case SystemZ::FK_390_PC16DBL:  return ELF::R_390_PC16DBL;
-  case SystemZ::FK_390_PC24DBL:  return ELF::R_390_PC24DBL;
-  case SystemZ::FK_390_PC32DBL:  return ELF::R_390_PC32DBL;
+  case FK_Data_2:
+  case SystemZ::FK_390_U16Imm:
+  case SystemZ::FK_390_S16Imm:
+    return ELF::R_390_PC16;
+  case FK_Data_4:
+  case SystemZ::FK_390_U32Imm:
+  case SystemZ::FK_390_S32Imm:
+    return ELF::R_390_PC32;
+  case FK_Data_8:
+    return ELF::R_390_PC64;
+  case SystemZ::FK_390_PC12DBL:
+    return ELF::R_390_PC12DBL;
+  case SystemZ::FK_390_PC16DBL:
+    return ELF::R_390_PC16DBL;
+  case SystemZ::FK_390_PC24DBL:
+    return ELF::R_390_PC24DBL;
+  case SystemZ::FK_390_PC32DBL:
+    return ELF::R_390_PC32DBL;
   }
   Ctx.reportError(Loc, "Unsupported PC-relative address");
   return 0;
 }
 
 // Return the R_390_TLS_LE* relocation type for MCFixupKind Kind.
 static unsigned getTLSLEReloc(MCContext &Ctx, SMLoc Loc, unsigned Kind) {
   switch (Kind) {

llvm/lib/Target/SystemZ/SystemZOperands.td

 class ImmediateTLSAsmOperand<string name>
   : AsmOperandClass {
   let Name = name;
   let RenderMethod = "addImmTLSOperands";
 }
 
 class ImmediateOp<ValueType vt, string asmop> : Operand<vt> {
   let PrintMethod = "print"#asmop#"Operand";
+  let EncoderMethod = "getImmOpValue<SystemZ::FK_390_"#asmop#">";
   let DecoderMethod = "decode"#asmop#"Operand";
   let ParserMatchClass = !cast<AsmOperandClass>(asmop);
   let OperandType = "OPERAND_IMMEDIATE";
 }
 
 class ImmOpWithPattern<ValueType vt, string asmop, code pred, SDNodeXForm xform,
       SDNode ImmNode = imm> :
   ImmediateOp<vt, asmop>, PatLeaf<(vt ImmNode), pred, xform>;
defm imm64zx48 : Immediate<i64, [{
   return isUInt<64>(N->getZExtValue());
 }], UIMM48, "U48Imm">;
 
 class Imm64 : ImmLeaf<i64, [{}]>, Operand<i64> {
   let OperandType = "OPERAND_IMMEDIATE";
 }
 def imm64 : Imm64;
 def len4imm64 : Imm64 {
-  let EncoderMethod = "getLenEncoding<4>";
+  let EncoderMethod = "getLenEncoding<SystemZ::FK_390_U4Imm>";
   let DecoderMethod = "decodeLenOperand<4>";
 }
 def len8imm64 : Imm64 {
-  let EncoderMethod = "getLenEncoding<8>";
+  let EncoderMethod = "getLenEncoding<SystemZ::FK_390_U8Imm>";
   let DecoderMethod = "decodeLenOperand<8>";
 }
 
 //===----------------------------------------------------------------------===//
 // Floating-point immediates
 //===----------------------------------------------------------------------===//
 
 // Floating-point zero.
def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
   let DecoderMethod = "decodePC32DBLOperand";
 }
 
 //===----------------------------------------------------------------------===//
 // Addressing modes
 //===----------------------------------------------------------------------===//
 
 // 12-bit displacement operands.
-let EncoderMethod = "getDisp12Encoding",
+let EncoderMethod = "getImmOpValue<SystemZ::FK_390_U12Imm>",
     DecoderMethod = "decodeU12ImmOperand" in {
   def disp12imm32 : Operand<i32>;
   def disp12imm64 : Operand<i64>;
 }
 
 // 20-bit displacement operands.
-let EncoderMethod = "getDisp20Encoding",
+let EncoderMethod = "getImmOpValue<SystemZ::FK_390_S20Imm>",
     DecoderMethod = "decodeS20ImmOperand" in {
   def disp20imm32 : Operand<i32>;
   def disp20imm64 : Operand<i64>;
 }
 
 def BDAddr32Disp12      : AddressAsmOperand<"BDAddr",   "32", "12">;
 def BDAddr32Disp20      : AddressAsmOperand<"BDAddr",   "32", "20">;
 def BDAddr64Disp12      : AddressAsmOperand<"BDAddr",   "64", "12">;

llvm/test/MC/SystemZ/fixups-bad-z13.s

+# RUN: not llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s 2>&1 | FileCheck %s
+
+  .text
+
+# CHECK:      error: Unsupported absolute address
+# CHECK-NEXT:        vleg %v0,0,src
+# CHECK-NEXT:        ^
+  vleg %v0,0,src
+
+# CHECK:      error: Unsupported absolute address
+# CHECK-NEXT:        vleih %v0,0,src
+# CHECK-NEXT:        ^
+  vleih %v0,0,src
+
+# CHECK:      error: Unsupported absolute address
+# CHECK-NEXT:        vleif %v0,0,src
+# CHECK-NEXT:        ^
+  vleif %v0,0,src
+
+# CHECK:      error: Unsupported absolute address
+# CHECK-NEXT:        vrepi %v0,0,src
+# CHECK-NEXT:        ^
+  vrepi %v0,0,src

llvm/test/MC/SystemZ/fixups.s

 
 # RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 --show-encoding %s | FileCheck %s
 
 # RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \
 # RUN: llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL
 
+# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \
+# RUN: llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-DIS
+
 # CHECK: larl %r14, target                      # encoding: [0xc0,0xe0,A,A,A,A]
 # CHECK-NEXT:                                   # fixup A - offset: 2, value: target+2, kind: FK_390_PC32DBL
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PC32DBL target 0x2
   .align 16
   larl %r14, target
 
 # CHECK: larl %r14, target@GOT                  # encoding: [0xc0,0xe0,A,A,A,A]
 # CHECK-NEXT:                                   # fixup A - offset: 2, value: target@GOT+2, kind: FK_390_PC32DBL
# CHECK-REL:                                    0x{{[0-9A-F]*0}} R_390_TLS_LDCALL sym 0x0
   .align 16
   bras %r14, target@plt:tls_ldcall:sym
 
 
 # Symbolic displacements
 
 ## BD12
 # CHECK: vl %v0, src                            # encoding: [0xe7,0x00,0b0000AAAA,A,0x00,0x06]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         vl %v0, src
 
 # CHECK: vl %v0, src(%r1)                       # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x06]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         vl %v0, src(%r1)
 
 # CHECK: .insn vrx,253987186016262,%v0,src(%r1),3  # encoding: [0xe7,0x00,0b0001AAAA,A,0x30,0x06]
-# CHECK-NEXT:                                      # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                      # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                       0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         .insn vrx,0xe70000000006,%v0,src(%r1),3     # vl
 
 ## BD20
 # CHECK: lmg %r6, %r15, src                     # encoding: [0xeb,0x6f,0b0000AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_20 src 0x0
   .align 16
         lmg %r6, %r15, src
 
 # CHECK: lmg %r6, %r15, src(%r1)                # encoding: [0xeb,0x6f,0b0001AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_20 src 0x0
   .align 16
         lmg %r6, %r15, src(%r1)
 
 # CHECK: .insn siy,258385232527441,src(%r15),240  # encoding: [0xeb,0xf0,0b1111AAAA,A,A,0x51]
-# CHECK-NEXT:                                     # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT:                                     # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
 # CHECK-REL:                                      0x{{[0-9A-F]*2}} R_390_20 src 0x0
   .align 16
         .insn siy,0xeb0000000051,src(%r15),240    # tmy
 
 ## BDX12
 # CHECK: la %r14, src                           # encoding: [0x41,0xe0,0b0000AAAA,A]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         la %r14, src
 
 # CHECK: la %r14, src(%r1)                      # encoding: [0x41,0xe0,0b0001AAAA,A]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         la %r14, src(%r1)
 
 # CHECK: la %r14, src(%r1,%r2)                  # encoding: [0x41,0xe1,0b0010AAAA,A]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         la %r14, src(%r1, %r2)
 
 # CHECK: .insn vrx,253987186016262,%v2,src(%r2,%r3),3  # encoding: [0xe7,0x22,0b0011AAAA,A,0x30,0x06]
-# CHECK-NEXT:                                        # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                        # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                           0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         .insn vrx,0xe70000000006,%v2,src(%r2, %r3),3   # vl
 
 ##BDX20
 # CHECK: lg %r14, src                           # encoding: [0xe3,0xe0,0b0000AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_20 src 0x0
   .align 16
   lg %r14, src
 
 # CHECK: lg %r14, src(%r1)                      # encoding: [0xe3,0xe0,0b0001AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_20 src 0x0
   .align 16
   lg %r14, src(%r1)
 
 # CHECK: lg %r14, src(%r1,%r2)                  # encoding: [0xe3,0xe1,0b0010AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_20 src 0x0
   .align 16
   lg %r14, src(%r1, %r2)
 
 # CHECK:  .insn rxy,260584255783013,%f1,src(%r2,%r15)  # encoding: [0xed,0x12,0b1111AAAA,A,A,0x65]
-# CHECK-NEXT:                                          # fixup A - offset: 2, value: src, kind: FK_390_20
+# CHECK-NEXT:                                          # fixup A - offset: 2, value: src, kind: FK_390_S20Imm
 # CHECK-REL:                                           0x{{[0-9A-F]*2}} R_390_20 src 0x0
   .align 16
   .insn rxy,0xed0000000065,%f1,src(%r2,%r15)     # ldy
 
 ##BD12L4
 # CHECK: tp src(16)                             # encoding: [0xeb,0xf0,0b0000AAAA,A,0x00,0xc0]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
   .align 16
         tp src(16)
 
 # CHECK: tp src(16,%r1)                         # encoding: [0xeb,0xf0,0b0001AAAA,A,0x00,0xc0]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
   .align 16
         tp src(16, %r1)
 
 ##BD12L8
 #SSa
 # CHECK: mvc dst(1,%r1), src(%r1)               # encoding: [0xd2,0x00,0b0001AAAA,A,0b0001BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 dst 0x0
 # CHECK-REL:                                    0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
         mvc dst(1,%r1), src(%r1)
 
 #SSb
 # CHECK: mvo src(16,%r1), src(1,%r2)            # encoding: [0xf1,0xf0,0b0001AAAA,A,0b0010BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
 # CHECK-REL:                                    0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
         mvo src(16,%r1), src(1,%r2)
 
 #SSc
 # CHECK: srp src(1,%r1), src(%r15), 0           # encoding: [0xf0,0x00,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
 # CHECK-REL:                                    0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
         srp src(1,%r1), src(%r15), 0
 
 ##BDR12
 #SSd
 # CHECK: mvck dst(%r2,%r1), src, %r3            # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 dst 0x0
 # CHECK-REL:                                    0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
   mvck dst(%r2,%r1), src, %r3
 
 # CHECK: .insn ss,238594023227392,dst(%r2,%r1),src,%r3  # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
-# CHECK-NEXT:                                           # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT:                                           # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                           # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT:                                           # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                            0x{{[0-9A-F]*2}} R_390_12 dst 0x0
 # CHECK-REL:                                            0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
         .insn ss,0xd90000000000,dst(%r2,%r1),src,%r3  # mvck
 
 #SSe
 # CHECK: lmd %r2, %r4, src1(%r1), src2(%r1)     # encoding: [0xef,0x24,0b0001AAAA,A,0b0001BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src1, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: src2, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src1, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: src2, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src1 0x0
 # CHECK-REL:                                    0x{{[0-9A-F]*4}} R_390_12 src2 0x0
         .align 16
         lmd %r2, %r4, src1(%r1), src2(%r1)
 
 #SSf
 # CHECK: pka dst(%r15), src(256,%r15)           # encoding: [0xe9,0xff,0b1111AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 dst 0x0
 # CHECK-REL:                                    0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
   pka     dst(%r15), src(256,%r15)
 
 #SSE
 # CHECK: strag dst(%r1), src(%r15)              # encoding: [0xe5,0x02,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 dst 0x0
 # CHECK-REL:                                    0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
         strag dst(%r1), src(%r15)
 
 # CHECK: .insn sse,251796752695296,dst(%r1),src(%r15)  # encoding: [0xe5,0x02,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                          # fixup A - offset: 2, value: dst, kind: FK_390_12
-# CHECK-NEXT:                                          # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                          # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT:                                          # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                           0x{{[0-9A-F]*2}} R_390_12 dst 0x0
 # CHECK-REL:                                           0x{{[0-9A-F]*4}} R_390_12 src 0x0
   .align 16
   .insn sse,0xe50200000000,dst(%r1),src(%r15)    # strag
 
 #SSF
 # CHECK: ectg src, src(%r15), %r2               # encoding: [0xc8,0x21,0b0000AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
 # CHECK-REL:                                    0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
         ectg src, src(%r15), %r2
 
 # CHECK: .insn ssf,219906620522496,src,src(%r15),%r2   # encoding: [0xc8,0x21,0b0000AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                          # fixup A - offset: 2, value: src, kind: FK_390_12
-# CHECK-NEXT:                                          # fixup B - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                          # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-NEXT:                                          # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                           0x{{[0-9A-F]*2}} R_390_12 src 0x0
 # CHECK-REL:                                           0x{{[0-9A-F]*4}} R_390_12 src 0x0
         .align 16
         .insn ssf,0xc80100000000,src,src(%r15),%r2     # ectg
 
 ##BDV12
 # CHECK: vgeg %v0, src(%v0,%r1), 0              # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x12]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
 # CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
         .align 16
         vgeg %v0, src(%v0,%r1), 0
 
 ## Fixup for second operand only
 # CHECK:  mvc     32(8,%r0), src                # encoding: [0xd2,0x07,0x00,0x20,0b0000AAAA,A]
-# CHECK-NEXT:                                   # fixup A - offset: 4, value: src, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 4, value: src, kind: FK_390_U12Imm
         .align 16
         mvc     32(8,%r0),src
 
+##U8
+# CHECK: cli 0(%r1), src                        # encoding: [0x95,A,0x10,0x00]
+# CHECK-NEXT:                                   # fixup A - offset: 1, value: src, kind: FK_390_U8Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_8 src 0x0
+       .align 16
+       cli 0(%r1),src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: cli 0(%r1), local_u8-[[L]]        # encoding: [0x95,A,0x10,0x00]
+# CHECK-NEXT:                                   # fixup A - offset: 1, value: local_u8-[[L]], kind: FK_390_U8Imm
+# CHECK-DIS:                                    95 04 10 00   cli     0(%r1), 4
+       .align 16
+       cli 0(%r1),local_u8-.
+local_u8:
+
+##S8
+# CHECK: asi 0(%r1), src                        # encoding: [0xeb,A,0x10,0x00,0x00,0x6a]
+# CHECK-NEXT:                                   # fixup A - offset: 1, value: src, kind: FK_390_S8Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_8 src 0x0
+       .align 16
+       asi 0(%r1),src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: asi 0(%r1), local_s8-[[L]]        # encoding: [0xeb,A,0x10,0x00,0x00,0x6a]
+# CHECK-NEXT:                                   # fixup A - offset: 1, value: local_s8-[[L]], kind: FK_390_S8Imm
+# CHECK-DIS:                                    eb 06 10 00 00 6a     asi     0(%r1), 6
+       .align 16
+       asi 0(%r1),local_s8-.
+local_s8:
+
+##U16
+# CHECK: oill %r1, src                          # encoding: [0xa5,0x1b,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U16Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_16 src 0x0
+        .align 16
+        oill %r1,src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: oill %r1, local_u16-[[L]]         # encoding: [0xa5,0x1b,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: local_u16-[[L]], kind: FK_390_U16Imm
+# CHECK-DIS:                                    a5 1b 00 04   oill    %r1, 4
+        .align 16
+        oill %r1,local_u16-.
+local_u16:
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: oill %r1, src-[[L]]               # encoding: [0xa5,0x1b,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src-[[L]], kind: FK_390_U16Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_PC16 src 0x2
+        .align 16
+        oill %r1,src-.
+
+##S16
+# CHECK: lghi %r1, src                          # encoding: [0xa7,0x19,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_S16Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_16 src 0x0
+        .align 16
+        lghi %r1,src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: lghi %r1, local_s16-[[L]]         # encoding: [0xa7,0x19,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: local_s16-[[L]], kind: FK_390_S16Imm
+# CHECK-DIS:                                    a7 19 00 04   lghi    %r1, 4
+        .align 16
+        lghi %r1,local_s16-.
+local_s16:
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: lghi %r1, src-[[L]]               # encoding: [0xa7,0x19,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src-[[L]], kind: FK_390_S16Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_PC16 src 0x2
+        .align 16
+        lghi %r1,src-.
+
+##U32
+# CHECK: clfi %r1, src                          # encoding: [0xc2,0x1f,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U32Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_32 src 0x0
+        .align 16
+        clfi %r1,src
+
+# CHECK: [[L:\..+]]:
+# CHECK-NEXT: clfi %r1, local_u32-[[L]]         # encoding: [0xc2,0x1f,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: local_u32-[[L]], kind: FK_390_U32Imm
+# CHECK-DIS:                                    c2 1f 00 00 00 06     clfi    %r1, 6
+        .align 16
+        clfi %r1,local_u32-.
+local_u32:
+
+# CHECK: [[L:\..+]]:
+# CHECK: clfi %r1, src-[[L]]                    # encoding: [0xc2,0x1f,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src-[[L]], kind: FK_390_U32Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_PC32 src 0x2
+        .align 16
+        clfi %r1,src-.
+
+##S32
+# CHECK: lgfi %r1, src                          # encoding: [0xc0,0x11,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_S32Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_32 src 0x0
+        .align 16
+        lgfi %r1,src
+
+# CHECK: [[L:\..+]]:
+# CHECK: lgfi %r1, local_s32-[[L]]              # encoding: [0xc0,0x11,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: local_s32-[[L]], kind: FK_390_S32Imm
+# CHECK-DIS:                                    c0 11 00 00 00 06     lgfi    %r1, 6
+        .align 16
+        lgfi %r1,local_s32-.
+local_s32:
+
+# CHECK: [[L:\..+]]:
+# CHECK: lgfi %r1, src-[[L]]                    # encoding: [0xc0,0x11,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src-[[L]], kind: FK_390_S32Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_PC32 src 0x2
+        .align 16
+        lgfi %r1,src-.
+
 # Data relocs
 # llvm-mc does not show any "encoding" string for data, so we just check the relocs
 
 # CHECK-REL: .rela.data
   .data
 
 # CHECK-REL: 0x{{[0-9A-F]*0}} R_390_TLS_LE64 target 0x0
   .align 16

llvm/test/MC/SystemZ/insn-bad-z196.s

#CHECK: adtra %f0, %f0, %f0, 16
 
   adtra %f0, %f0, %f0, -1
   adtra %f0, %f0, %f0, 16
 
 #CHECK: error: invalid operand
 #CHECK: aghik %r0, %r1, -32769
 #CHECK: error: invalid operand
 #CHECK: aghik %r0, %r1, 32768
-#CHECK: error: invalid operand
-#CHECK: aghik %r0, %r1, foo
 
   aghik %r0, %r1, -32769
   aghik %r0, %r1, 32768
-  aghik %r0, %r1, foo
 
 #CHECK: error: invalid operand
 #CHECK: ahik  %r0, %r1, -32769
 #CHECK: error: invalid operand
 #CHECK: ahik  %r0, %r1, 32768
-#CHECK: error: invalid operand
-#CHECK: ahik  %r0, %r1, foo
 
   ahik  %r0, %r1, -32769
   ahik  %r0, %r1, 32768
-  ahik  %r0, %r1, foo
 
 #CHECK: error: invalid operand
 #CHECK: aih %r0, (-1 << 31) - 1
 #CHECK: error: invalid operand
 #CHECK: aih %r0, (1 << 31)
 
   aih  %r0, (-1 << 31) - 1
   aih %r0, (1 << 31)

llvm/test/MC/SystemZ/insn-bad.s

#CHECK: agfi  %r0, (1 << 31)
 
   agfi  %r0, (-1 << 31) - 1
   agfi  %r0, (1 << 31)
 
 #CHECK: error: invalid operand
 #CHECK: aghi  %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: aghi  %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: aghi  %r0, foo
 
   aghi  %r0, -32769
   aghi  %r0, 32768
-  aghi  %r0, foo
 
 #CHECK: error: instruction requires: distinct-ops
 #CHECK: aghik %r1, %r2, 3
 
   aghik %r1, %r2, 3
 
 #CHECK: error: instruction requires: distinct-ops
 #CHECK: agrk  %r2,%r3,%r4

 #CHECK: ahhlr %r0, %r0, %r0
 
   ahhlr %r0, %r0, %r0
 
 #CHECK: error: invalid operand
 #CHECK: ahi %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: ahi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: ahi %r0, foo
 
   ahi %r0, -32769
   ahi %r0, 32768
-  ahi %r0, foo
 
 #CHECK: error: instruction requires: distinct-ops
 #CHECK: ahik  %r1, %r2, 3
 
   ahik  %r1, %r2, 3
 
 #CHECK: error: invalid operand
 #CHECK: ahy %r0, -524289
#CHECK: jlno    label
   jlm label
   jlnm  label
   jllh  label
   jllnlh  label
   jlo label
   jlno  label
 
 #CHECK: error: invalid operand
-#CHECK: brc foo, bar
-#CHECK: error: invalid operand
 #CHECK: brc -1, bar
 #CHECK: error: invalid operand
 #CHECK: brc 16, bar
 
-  brc foo, bar
   brc -1, bar
   brc 16, bar
 
 #CHECK: error: offset out of range
 #CHECK: brcl  0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: brcl  0, -1
 #CHECK: error: offset out of range
#CHECK: jgnop 0x100000000
   jgnop 0x100000000
 
 
 #CHECK: error: invalid instruction
 #CHECK: jlnop label
   jlnop label
 
 #CHECK: error: invalid operand
-#CHECK: brcl  foo, bar
-#CHECK: error: invalid operand
 #CHECK: brcl  -1, bar
 #CHECK: error: invalid operand
 #CHECK: brcl  16, bar
 
-  brcl  foo, bar
   brcl  -1, bar
   brcl  16, bar
 
 #CHECK: error: offset out of range
 #CHECK: brct  %r0, -0x100002
 #CHECK: error: offset out of range
 #CHECK: brct  %r0, -1
 #CHECK: error: offset out of range
#CHECK: cgh %r0, 524288
 
   cgh %r0, -524289
   cgh %r0, 524288
 
 #CHECK: error: invalid operand
 #CHECK: cghi  %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: cghi  %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: cghi  %r0, foo
 
   cghi  %r0, -32769
   cghi  %r0, 32768
-  cghi  %r0, foo
 
 #CHECK: error: offset out of range
 #CHECK: cghrl %r0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: cghrl %r0, -1
 #CHECK: error: offset out of range
 #CHECK: cghrl %r0, 1
 #CHECK: error: offset out of range
#CHECK: chhsi 0, 32768
   chhsi 0(%r1,%r2), 0
   chhsi 0, -32769
   chhsi 0, 32768
 
 #CHECK: error: invalid operand
 #CHECK: chi %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: chi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: chi %r0, foo
 
   chi %r0, -32769
   chi %r0, 32768
-  chi %r0, foo
 
 #CHECK: error: instruction requires: high-word
 #CHECK: chlr  %r0, %r0
 
   chlr  %r0, %r0
 
 #CHECK: error: offset out of range
 #CHECK: chrl  %r0, -0x1000000002
#CHECK: lgh %r0, 524288
 
   lgh %r0, -524289
   lgh %r0, 524288
 
 #CHECK: error: invalid operand
 #CHECK: lghi  %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: lghi  %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: lghi  %r0, foo
 
   lghi  %r0, -32769
   lghi  %r0, 32768
-  lghi  %r0, foo
 
 #CHECK: error: offset out of range
 #CHECK: lghrl %r0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: lghrl %r0, -1
 #CHECK: error: offset out of range
 #CHECK: lghrl %r0, 1
 #CHECK: error: offset out of range

 #CHECK: lhh %r0, 0
 
   lhh %r0, 0
 
 #CHECK: error: invalid operand
 #CHECK: lhi %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: lhi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: lhi %r0, foo
 
   lhi %r0, -32769
   lhi %r0, 32768
-  lhi %r0, foo
 
 #CHECK: error: offset out of range
 #CHECK: lhrl  %r0, -0x1000000002
 #CHECK: error: offset out of range
 #CHECK: lhrl  %r0, -1
 #CHECK: error: offset out of range
 #CHECK: lhrl  %r0, 1
 #CHECK: error: offset out of range
#CHECK: mfy %r1, 0
   mfy %r0, -524289
   mfy %r0, 524288
   mfy %r1, 0
 
 #CHECK: error: invalid operand
 #CHECK: mghi  %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: mghi  %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: mghi  %r0, foo
 
   mghi  %r0, -32769
   mghi  %r0, 32768
-  mghi  %r0, foo
 
 #CHECK: error: invalid operand
 #CHECK: mh  %r0, -1
 #CHECK: error: invalid operand
 #CHECK: mh  %r0, 4096
 
   mh  %r0, -1
   mh  %r0, 4096
 
 #CHECK: error: invalid operand
 #CHECK: mhi %r0, -32769
 #CHECK: error: invalid operand
 #CHECK: mhi %r0, 32768
-#CHECK: error: invalid operand
-#CHECK: mhi %r0, foo
 
   mhi %r0, -32769
   mhi %r0, 32768
-  mhi %r0, foo
 
 #CHECK: error: invalid operand
 #CHECK: mhy %r0, -524289
 #CHECK: error: invalid operand
 #CHECK: mhy %r0, 524288
 
   mhy %r0, -524289
   mhy %r0, 524288

llvm/test/MC/SystemZ/insn-good-z196.s

 #CHECK: aghik %r0, %r0, -32768        # encoding: [0xec,0x00,0x80,0x00,0x00,0xd9]
 #CHECK: aghik %r0, %r0, -1            # encoding: [0xec,0x00,0xff,0xff,0x00,0xd9]
 #CHECK: aghik %r0, %r0, 0             # encoding: [0xec,0x00,0x00,0x00,0x00,0xd9]
 #CHECK: aghik %r0, %r0, 1             # encoding: [0xec,0x00,0x00,0x01,0x00,0xd9]
 #CHECK: aghik %r0, %r0, 32767         # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd9]
 #CHECK: aghik %r0, %r15, 0            # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd9]
 #CHECK: aghik %r15, %r0, 0            # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd9]
 #CHECK: aghik %r7, %r8, -16           # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd9]
+#CHECK: aghik %r0, %r1, foo           # encoding: [0xec,0x01,A,A,0x00,0xd9]
 
   aghik %r0, %r0, -32768
   aghik %r0, %r0, -1
   aghik %r0, %r0, 0
   aghik %r0, %r0, 1
   aghik %r0, %r0, 32767
   aghik %r0, %r15, 0
   aghik %r15, %r0, 0
   aghik %r7, %r8, -16
+  aghik %r0, %r1, foo
 
 #CHECK: agrk  %r0, %r0, %r0           # encoding: [0xb9,0xe8,0x00,0x00]
 #CHECK: agrk  %r0, %r0, %r15          # encoding: [0xb9,0xe8,0xf0,0x00]
 #CHECK: agrk  %r0, %r15, %r0          # encoding: [0xb9,0xe8,0x00,0x0f]
 #CHECK: agrk  %r15, %r0, %r0          # encoding: [0xb9,0xe8,0x00,0xf0]
 #CHECK: agrk  %r7, %r8, %r9           # encoding: [0xb9,0xe8,0x90,0x78]
 
   agrk  %r0,%r0,%r0

 #CHECK: ahik  %r0, %r0, -32768        # encoding: [0xec,0x00,0x80,0x00,0x00,0xd8]
 #CHECK: ahik  %r0, %r0, -1            # encoding: [0xec,0x00,0xff,0xff,0x00,0xd8]
 #CHECK: ahik  %r0, %r0, 0             # encoding: [0xec,0x00,0x00,0x00,0x00,0xd8]
 #CHECK: ahik  %r0, %r0, 1             # encoding: [0xec,0x00,0x00,0x01,0x00,0xd8]
 #CHECK: ahik  %r0, %r0, 32767         # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd8]
 #CHECK: ahik  %r0, %r15, 0            # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd8]
 #CHECK: ahik  %r15, %r0, 0            # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd8]
 #CHECK: ahik  %r7, %r8, -16           # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd8]
+#CHECK: ahik  %r0, %r1, foo           # encoding: [0xec,0x01,A,A,0x00,0xd8]
 
   ahik  %r0, %r0, -32768
   ahik  %r0, %r0, -1
   ahik  %r0, %r0, 0
   ahik  %r0, %r0, 1
   ahik  %r0, %r0, 32767
   ahik  %r0, %r15, 0
   ahik  %r15, %r0, 0
   ahik  %r7, %r8, -16
+  ahik  %r0, %r1, foo
 
 #CHECK: aih %r0, -2147483648        # encoding: [0xcc,0x08,0x80,0x00,0x00,0x00]
 #CHECK: aih %r0, -1                 # encoding: [0xcc,0x08,0xff,0xff,0xff,0xff]
 #CHECK: aih %r0, 0                  # encoding: [0xcc,0x08,0x00,0x00,0x00,0x00]
 #CHECK: aih %r0, 1                  # encoding: [0xcc,0x08,0x00,0x00,0x00,0x01]
 #CHECK: aih %r0, 2147483647         # encoding: [0xcc,0x08,0x7f,0xff,0xff,0xff]
 #CHECK: aih %r15, 0                 # encoding: [0xcc,0xf8,0x00,0x00,0x00,0x00]
 

llvm/test/MC/SystemZ/insn-good.s

#CHECK: agfr  %r7, %r8                # encoding: [0xb9,0x18,0x00,0x78]
   agfr  %r7,%r8
 
 #CHECK: aghi  %r0, -32768             # encoding: [0xa7,0x0b,0x80,0x00]
 #CHECK: aghi  %r0, -1                 # encoding: [0xa7,0x0b,0xff,0xff]
 #CHECK: aghi  %r0, 0                  # encoding: [0xa7,0x0b,0x00,0x00]
 #CHECK: aghi  %r0, 1                  # encoding: [0xa7,0x0b,0x00,0x01]
 #CHECK: aghi  %r0, 32767              # encoding: [0xa7,0x0b,0x7f,0xff]
 #CHECK: aghi  %r15, 0                 # encoding: [0xa7,0xfb,0x00,0x00]
+#CHECK: aghi  %r0, foo                # encoding: [0xa7,0x0b,A,A]
 
   aghi  %r0, -32768
   aghi  %r0, -1
   aghi  %r0, 0
   aghi  %r0, 1
   aghi  %r0, 32767
   aghi  %r15, 0
+  aghi  %r0, foo
 
 #CHECK: agr %r0, %r0                # encoding: [0xb9,0x08,0x00,0x00]
 #CHECK: agr %r0, %r15               # encoding: [0xb9,0x08,0x00,0x0f]
 #CHECK: agr %r15, %r0               # encoding: [0xb9,0x08,0x00,0xf0]
 #CHECK: agr %r7, %r8                # encoding: [0xb9,0x08,0x00,0x78]
 
   agr %r0,%r0
   agr %r0,%r15
#CHECK: ah  %r15, 0                 # encoding: [0x4a,0xf0,0x00,0x00]
   ah  %r15, 0
 
 #CHECK: ahi %r0, -32768             # encoding: [0xa7,0x0a,0x80,0x00]
 #CHECK: ahi %r0, -1                 # encoding: [0xa7,0x0a,0xff,0xff]
 #CHECK: ahi %r0, 0                  # encoding: [0xa7,0x0a,0x00,0x00]
 #CHECK: ahi %r0, 1                  # encoding: [0xa7,0x0a,0x00,0x01]
 #CHECK: ahi %r0, 32767              # encoding: [0xa7,0x0a,0x7f,0xff]
 #CHECK: ahi %r15, 0                 # encoding: [0xa7,0xfa,0x00,0x00]
+#CHECK: ahi %r0, foo                # encoding: [0xa7,0x0a,A,A]
 
   ahi %r0, -32768
   ahi %r0, -1
   ahi %r0, 0
   ahi %r0, 1
   ahi %r0, 32767
   ahi %r15, 0
+  ahi %r0, foo
 
 #CHECK: ahy %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x7a]
 #CHECK: ahy %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x7a]
 #CHECK: ahy %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x7a]
 #CHECK: ahy %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x7a]
 #CHECK: ahy %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x7a]
 #CHECK: ahy %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x7a]
 #CHECK: ahy %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x7a]
#CHECK: cgh %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x34]
   cgh %r15, 0
 
 #CHECK: cghi  %r0, -32768             # encoding: [0xa7,0x0f,0x80,0x00]
 #CHECK: cghi  %r0, -1                 # encoding: [0xa7,0x0f,0xff,0xff]
 #CHECK: cghi  %r0, 0                  # encoding: [0xa7,0x0f,0x00,0x00]
 #CHECK: cghi  %r0, 1                  # encoding: [0xa7,0x0f,0x00,0x01]
 #CHECK: cghi  %r0, 32767              # encoding: [0xa7,0x0f,0x7f,0xff]
 #CHECK: cghi  %r15, 0                 # encoding: [0xa7,0xff,0x00,0x00]
+#CHECK: cghi  %r0, foo                # encoding: [0xa7,0x0f,A,A]
 
   cghi  %r0, -32768
   cghi  %r0, -1
   cghi  %r0, 0
   cghi  %r0, 1
   cghi  %r0, 32767
   cghi  %r15, 0
+  cghi  %r0, foo
 
 #CHECK: cghrl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x04,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
   cghrl %r0, -0x100000000
 #CHECK: cghrl %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x04,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL
   cghrl %r0, -2
 #CHECK: cghrl %r0, .[[LAB:L.*]] # encoding: [0xc6,0x04,A,A,A,A]
#CHECK: chhsi 4095(%r15), 42          # encoding: [0xe5,0x54,0xff,0xff,0x00,0x2a]
   chhsi 4095(%r15), 42
 
 #CHECK: chi %r0, -32768             # encoding: [0xa7,0x0e,0x80,0x00]
 #CHECK: chi %r0, -1                 # encoding: [0xa7,0x0e,0xff,0xff]
 #CHECK: chi %r0, 0                  # encoding: [0xa7,0x0e,0x00,0x00]
 #CHECK: chi %r0, 1                  # encoding: [0xa7,0x0e,0x00,0x01]
 #CHECK: chi %r0, 32767              # encoding: [0xa7,0x0e,0x7f,0xff]
 #CHECK: chi %r15, 0                 # encoding: [0xa7,0xfe,0x00,0x00]
+#CHECK: chi %r0, foo                # encoding: [0xa7,0x0e,A,A]
 
   chi %r0, -32768
   chi %r0, -1
   chi %r0, 0
   chi %r0, 1
   chi %r0, 32767
   chi %r15, 0
+  chi %r0, foo
 
 #CHECK: chrl  %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc6,0x05,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
   chrl  %r0, -0x100000000
 #CHECK: chrl  %r0, .[[LAB:L.*]]-2 # encoding: [0xc6,0x05,A,A,A,A]
 #CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL
   chrl  %r0, -2
 #CHECK: chrl  %r0, .[[LAB:L.*]] # encoding: [0xc6,0x05,A,A,A,A]

 
 
 #CHECK: lghi  %r0, -32768             # encoding: [0xa7,0x09,0x80,0x00]
 #CHECK: lghi  %r0, -1                 # encoding: [0xa7,0x09,0xff,0xff]
 #CHECK: lghi  %r0, 0                  # encoding: [0xa7,0x09,0x00,0x00]
 #CHECK: lghi  %r0, 1                  # encoding: [0xa7,0x09,0x00,0x01]
 #CHECK: lghi  %r0, 32767              # encoding: [0xa7,0x09,0x7f,0xff]
 #CHECK: lghi  %r15, 0                 # encoding: [0xa7,0xf9,0x00,0x00]
+#CHECK: lghi  %r14, foo               # encoding: [0xa7,0xe9,A,A]
 
   lghi  %r0, -32768
   lghi  %r0, -1
   lghi  %r0, 0
   lghi  %r0, 1
   lghi  %r0, 32767
   lghi  %r15, 0
+  lghi  %r14, foo
 
 #CHECK: lghr  %r0, %r15               # encoding: [0xb9,0x07,0x00,0x0f]
 #CHECK: lghr  %r7, %r8                # encoding: [0xb9,0x07,0x00,0x78]
 #CHECK: lghr  %r15, %r0               # encoding: [0xb9,0x07,0x00,0xf0]
 
   lghr  %r0, %r15
   lghr  %r7, %r8
   lghr  %r15, %r0
#CHECK: lh  %r15, 0                 # encoding: [0x48,0xf0,0x00,0x00]
   lh  %r15, 0
 
 #CHECK: lhi %r0, -32768             # encoding: [0xa7,0x08,0x80,0x00]
 #CHECK: lhi %r0, -1                 # encoding: [0xa7,0x08,0xff,0xff]
 #CHECK: lhi %r0, 0                  # encoding: [0xa7,0x08,0x00,0x00]
 #CHECK: lhi %r0, 1                  # encoding: [0xa7,0x08,0x00,0x01]
 #CHECK: lhi %r0, 32767              # encoding: [0xa7,0x08,0x7f,0xff]
 #CHECK: lhi %r15, 0                 # encoding: [0xa7,0xf8,0x00,0x00]
+#CHECK: lhi %r0, foo                # encoding: [0xa7,0x08,A,A]
 
   lhi %r0, -32768
   lhi %r0, -1
   lhi %r0, 0
   lhi %r0, 1
   lhi %r0, 32767
   lhi %r15, 0
+  lhi %r0, foo
 
 #CHECK: lhr %r0, %r15               # encoding: [0xb9,0x27,0x00,0x0f]
 #CHECK: lhr %r7, %r8                # encoding: [0xb9,0x27,0x00,0x78]
 #CHECK: lhr %r15, %r0               # encoding: [0xb9,0x27,0x00,0xf0]
 
   lhr %r0, %r15
   lhr %r7, %r8
   lhr %r15, %r0
#CHECK: mfy %r14, 0                 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x5c]
   mfy %r14, 0
 
 #CHECK: mghi  %r0, -32768             # encoding: [0xa7,0x0d,0x80,0x00]
 #CHECK: mghi  %r0, -1                 # encoding: [0xa7,0x0d,0xff,0xff]
 #CHECK: mghi  %r0, 0                  # encoding: [0xa7,0x0d,0x00,0x00]
 #CHECK: mghi  %r0, 1                  # encoding: [0xa7,0x0d,0x00,0x01]
 #CHECK: mghi  %r0, 32767              # encoding: [0xa7,0x0d,0x7f,0xff]
 #CHECK: mghi  %r15, 0                 # encoding: [0xa7,0xfd,0x00,0x00]
+#CHECK: mghi  %r0, foo                # encoding: [0xa7,0x0d,A,A]
 
   mghi  %r0, -32768
   mghi  %r0, -1
   mghi  %r0, 0
   mghi  %r0, 1
   mghi  %r0, 32767
   mghi  %r15, 0
+  mghi  %r0, foo
 
 #CHECK: mh  %r0, 0                  # encoding: [0x4c,0x00,0x00,0x00]
 #CHECK: mh  %r0, 4095               # encoding: [0x4c,0x00,0x0f,0xff]
 #CHECK: mh  %r0, 0(%r1)             # encoding: [0x4c,0x00,0x10,0x00]
 #CHECK: mh  %r0, 0(%r15)            # encoding: [0x4c,0x00,0xf0,0x00]
 #CHECK: mh  %r0, 4095(%r1,%r15)     # encoding: [0x4c,0x01,0xff,0xff]
 #CHECK: mh  %r0, 4095(%r15,%r1)     # encoding: [0x4c,0x0f,0x1f,0xff]
 #CHECK: mh  %r15, 0                 # encoding: [0x4c,0xf0,0x00,0x00]
 
   mh  %r0, 0
   mh  %r0, 4095
   mh  %r0, 0(%r1)
   mh  %r0, 0(%r15)
   mh  %r0, 4095(%r1,%r15)
   mh  %r0, 4095(%r15,%r1)
   mh  %r15, 0
 
 #CHECK: mhi %r0, -32768             # encoding: [0xa7,0x0c,0x80,0x00]
 #CHECK: mhi %r0, -1                 # encoding: [0xa7,0x0c,0xff,0xff]
 #CHECK: mhi %r0, 0                  # encoding: [0xa7,0x0c,0x00,0x00]
 #CHECK: mhi %r0, 1                  # encoding: [0xa7,0x0c,0x00,0x01]
 #CHECK: mhi %r0, 32767              # encoding: [0xa7,0x0c,0x7f,0xff]
 #CHECK: mhi %r15, 0                 # encoding: [0xa7,0xfc,0x00,0x00]
+#CHECK: mhi %r0, foo                # encoding: [0xa7,0x0c,A,A]
 
   mhi %r0, -32768
   mhi %r0, -1
   mhi %r0, 0
   mhi %r0, 1
   mhi %r0, 32767
   mhi %r15, 0
+  mhi %r0, foo
 
 #CHECK: mhy %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x7c]
 #CHECK: mhy %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x7c]
 #CHECK: mhy %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x7c]
 #CHECK: mhy %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x7c]
 #CHECK: mhy %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x7c]
 #CHECK: mhy %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x7c]
 #CHECK: mhy %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x7c]

llvm/test/MC/SystemZ/reloc-absolute.s

 # RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 --show-encoding %s | FileCheck %s
 
 # RUN: llvm-mc -triple s390x-unknown-unknown -filetype=obj -mcpu=z13 %s | \
 # RUN: llvm-objdump -d - --mcpu=z13 | FileCheck %s -check-prefix=CHECK-REL
 
 # Test relocations that can be lowered by the integrated assembler.
 
   .text
 
 ## BD12
 # CHECK: vl %v0, b-a                            # encoding: [0xe7,0x00,0b0000AAAA,A,0x00,0x06]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    e7 00 00 04 00 06     vl  %v0, 4
         .align 16
         vl %v0, b-a
 
 # CHECK: vl %v0, b-a(%r1)                       # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x06]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    e7 00 10 04 00 06     vl  %v0, 4(%r1)
         .align 16
         vl %v0, b-a(%r1)
 
 # CHECK: .insn vrx,253987186016262,%v0,b-a(%r1),3  # encoding: [0xe7,0x00,0b0001AAAA,A,0x30,0x06]
-# CHECK-NEXT:                                      # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                      # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                       e7 00 10 04 30 06    vl  %v0, 4(%r1), 3
         .align 16
         .insn vrx,0xe70000000006,%v0,b-a(%r1),3     # vl
 
 ## BD20
 # CHECK: lmg %r6, %r15, b-a                     # encoding: [0xeb,0x6f,0b0000AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
 # CHECK-REL:                                    eb 6f 00 04 00 04     lmg %r6, %r15, 4
   .align 16
         lmg %r6, %r15, b-a
 
 # CHECK: lmg %r6, %r15, b-a(%r1)                # encoding: [0xeb,0x6f,0b0001AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
 # CHECK-REL:                                    eb 6f 10 04 00 04     lmg %r6, %r15, 4(%r1)
   .align 16
         lmg %r6, %r15, b-a(%r1)
 
 # CHECK: .insn siy,258385232527441,b-a(%r15),240  # encoding: [0xeb,0xf0,0b1111AAAA,A,A,0x51]
-# CHECK-NEXT:                                     # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT:                                     # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
 # CHECK-REL:                                      eb f0 f0 04 00 51     tmy 4(%r15), 240
   .align 16
         .insn siy,0xeb0000000051,b-a(%r15),240    # tmy
 
 ## BDX12
 # CHECK: la %r14, b-a                           # encoding: [0x41,0xe0,0b0000AAAA,A]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    41 e0 00 04   la  %r14, 4
         .align 16
         la %r14, b-a
 
 # CHECK: la %r14, b-a(%r1)                      # encoding: [0x41,0xe0,0b0001AAAA,A]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    41 e0 10 04   la  %r14, 4(%r1)
         .align 16
         la %r14, b-a(%r1)
 
 # CHECK: la %r14, b-a(%r1,%r2)                  # encoding: [0x41,0xe1,0b0010AAAA,A]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    41 e1 20 04   la  %r14, 4(%r1,%r2)
         .align 16
         la %r14, b-a(%r1, %r2)
 
 # CHECK: .insn vrx,253987186016262,%v2,b-a(%r2,%r3),3  # encoding: [0xe7,0x22,0b0011AAAA,A,0x30,0x06]
-# CHECK-NEXT:                                        # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                        # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                           e7 22 30 04 30 06      vl  %v2, 4(%r2,%r3), 3
         .align 16
         .insn vrx,0xe70000000006,%v2,b-a(%r2, %r3),3   # vl
 
 ##BDX20
 # CHECK: lg %r14, b-a                           # encoding: [0xe3,0xe0,0b0000AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
 # CHECK-REL:                                    e3 e0 00 04 00 04     lg  %r14, 4
   .align 16
   lg %r14, b-a
 
 # CHECK: lg %r14, b-a(%r1)                      # encoding: [0xe3,0xe0,0b0001AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
 # CHECK-REL:                                    e3 e0 10 04 00 04     lg  %r14, 4(%r1)
   .align 16
   lg %r14, b-a(%r1)
 
 # CHECK: lg %r14, b-a(%r1,%r2)                  # encoding: [0xe3,0xe1,0b0010AAAA,A,A,0x04]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
 # CHECK-REL:                                    e3 e1 20 04 00 04     lg  %r14, 4(%r1,%r2)
   .align 16
   lg %r14, b-a(%r1, %r2)
 
 # CHECK:  .insn rxy,260584255783013,%f1,b-a(%r2,%r15)  # encoding: [0xed,0x12,0b1111AAAA,A,A,0x65]
-# CHECK-NEXT:                                          # fixup A - offset: 2, value: b-a, kind: FK_390_20
+# CHECK-NEXT:                                          # fixup A - offset: 2, value: b-a, kind: FK_390_S20Imm
 # CHECK-REL:                                           ed 12 f0 04 00 65    ldy %f1, 4(%r2,%r15)
   .align 16
   .insn rxy,0xed0000000065,%f1,b-a(%r2,%r15)     # ldy
 
 ##BD12L4
 # CHECK: tp b-a(16)                             # encoding: [0xeb,0xf0,0b0000AAAA,A,0x00,0xc0]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    eb f0 00 04 00 c0     tp  4(16)
   .align 16
         tp b-a(16)
 
 # CHECK: tp b-a(16,%r1)                         # encoding: [0xeb,0xf0,0b0001AAAA,A,0x00,0xc0]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    eb f0 10 04 00 c0     tp  4(16,%r1)
   .align 16
         tp b-a(16, %r1)
 
 ##BD12L8
 #SSa
 # CHECK: mvc c-b(1,%r1), b-a(%r1)               # encoding: [0xd2,0x00,0b0001AAAA,A,0b0001BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    d2 00 10 08 10 04     mvc 8(1,%r1), 4(%r1)
         .align 16
         mvc c-b(1,%r1), b-a(%r1)
 
 #SSb
 # CHECK: mvo c-b(16,%r1), b-a(1,%r2)            # encoding: [0xf1,0xf0,0b0001AAAA,A,0b0010BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    f1 f0 10 08 20 04     mvo 8(16,%r1), 4(1,%r2)
         .align 16
         mvo c-b(16,%r1), b-a(1,%r2)
 
 #SSc
 # CHECK: srp b-a(1,%r1), b-a(%r15), 0           # encoding: [0xf0,0x00,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    f0 00 10 04 f0 04     srp 4(1,%r1), 4(%r15), 0
         .align 16
         srp b-a(1,%r1), b-a(%r15), 0
 
 ##BDR12
 #SSd
 # CHECK: mvck c-b(%r2,%r1), b-a, %r3            # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    d9 23 10 08 00 04     mvck  8(%r2,%r1), 4, %r3
         .align 16
   mvck c-b(%r2,%r1), b-a, %r3
 
 # CHECK: .insn ss,238594023227392,c-b(%r2,%r1),b-a,%r3  # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
-# CHECK-NEXT:                                           # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT:                                           # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                           # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT:                                           # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                            d9 23 10 08 00 04     mvck  8(%r2,%r1), 4, %r3
         .align 16
         .insn ss,0xd90000000000,c-b(%r2,%r1),b-a,%r3  # mvck
 
 #SSe
 # CHECK: lmd %r2, %r4, b-a(%r1), c-b(%r1)       # encoding: [0xef,0x24,0b0001AAAA,A,0b0001BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: c-b, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: c-b, kind: FK_390_U12Imm
 # CHECK-REL:                                    ef 24 10 04 10 08     lmd %r2, %r4, 4(%r1), 8(%r1)
         .align 16
         lmd %r2, %r4, b-a(%r1), c-b(%r1)
 
 #SSf
 # CHECK: pka c-b(%r15), b-a(256,%r15)           # encoding: [0xe9,0xff,0b1111AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    e9 ff f0 08 f0 04     pka 8(%r15), 4(256,%r15)
         .align 16
   pka     c-b(%r15), b-a(256,%r15)
 
 #SSE
 # CHECK: strag c-b(%r1), b-a(%r15)              # encoding: [0xe5,0x02,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    e5 02 10 08 f0 04     strag 8(%r1), 4(%r15)
         .align 16
         strag c-b(%r1), b-a(%r15)
 
 # CHECK: .insn sse,251796752695296,c-b(%r1),b-a(%r15)  # encoding: [0xe5,0x02,0b0001AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                          # fixup A - offset: 2, value: c-b, kind: FK_390_12
-# CHECK-NEXT:                                          # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                          # fixup A - offset: 2, value: c-b, kind: FK_390_U12Imm
+# CHECK-NEXT:                                          # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                           e5 02 10 08 f0 04      strag 8(%r1), 4(%r15)
   .align 16
   .insn sse,0xe50200000000,c-b(%r1),b-a(%r15)    # strag
 
 #SSF
 # CHECK: ectg b-a, b-a(%r15), %r2               # encoding: [0xc8,0x21,0b0000AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
-# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
+# CHECK-NEXT:                                   # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    c8 21 00 04 f0 04     ectg  4, 4(%r15), %r2
         .align 16
         ectg b-a, b-a(%r15), %r2
 
 # CHECK: .insn ssf,219906620522496,b-a,b-a(%r15),%r2   # encoding: [0xc8,0x21,0b0000AAAA,A,0b1111BBBB,B]
-# CHECK-NEXT:                                          # fixup A - offset: 2, value: b-a, kind: FK_390_12
-# CHECK-NEXT:                                          # fixup B - offset: 4, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                          # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
+# CHECK-NEXT:                                          # fixup B - offset: 4, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                           c8 21 00 04 f0 04      ectg  4, 4(%r15), %r2
         .align 16
         .insn ssf,0xc80100000000,b-a,b-a(%r15),%r2     # ectg
 
 ##BDV12
 # CHECK: vgeg %v0, b-a(%v0,%r1), 0              # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x12]
-# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_12
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: b-a, kind: FK_390_U12Imm
 # CHECK-REL:                                    e7 00 10 04 00 12     vgeg  %v0, 4(%v0,%r1), 0
         .align 16
         vgeg %v0, b-a(%v0,%r1), 0
 
   .type a,@object
   .local  a
   .comm a,4,4
   .type b,@object
   .local  b
   .comm b,8,4
   .type c,@object
   .local  c
   .comm c,4,4