[CSKY] Optimize conditional branch and value select with BTSTI

[benshi001]

llvm/test/CodeGen/CSKY/select.ll

8277

This test is not optimized with BTSTI due to the immediate 256 can be directly encoded into ANDI.

[benshi001]

Not sure why it reports patch application failed, but this patch did pass all tests on my localhost.

[zixuan-wu]

llvm/lib/Target/CSKY/CSKYInstrInfo.td

1249

can this opt also applied here?

[benshi001]

llvm/lib/Target/CSKY/CSKYInstrInfo.td

1249

Thanks. I have added that, and along with a test in llvm/test/CodeGen/CSKY/cmp-i.ll.

[benshi001]

llvm/lib/Target/CSKY/CSKYInstrInfo.td

156–157

This is a typo in my previous commit. The max immediate can be directly encoded into ANDI32 is 0xfff, not 0xffff.

This is a typo, need not another patch.

llvm/lib/Target/CSKY/CSKYInstrInfo.td

 
 def LowestSetBit : SDNodeXForm<imm, [{
   uint32_t I = N->getZExtValue();
   return CurDAG->getTargetConstant(llvm::countr_zero<uint32_t>(I), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 def HighestSetBit : SDNodeXForm<imm, [{
   uint32_t I = N->getZExtValue();
   return CurDAG->getTargetConstant(31 - llvm::countl_zero<uint32_t>(I),
                                    SDLoc(N), N->getValueType(0));
 }]>;
 def LowestZeroBit : SDNodeXForm<imm, [{
   uint32_t I = ~N->getZExtValue();
   return CurDAG->getTargetConstant(llvm::countr_zero<uint32_t>(I), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 def HighestZeroBit : SDNodeXForm<imm, [{
   uint32_t I = ~N->getZExtValue();
def : Pat<(brcond (i32 (setuge GPR:$rs1, oimm16:$rs2)), bb:$imm16),
           (BT32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
   def : Pat<(brcond (i32 (setult GPR:$rs1, oimm16:$rs2)), bb:$imm16),
           (BF32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
   def : Pat<(brcond (i32 (setlt GPR:$rs1, oimm16:$rs2)), bb:$imm16),
           (BT32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
   def : Pat<(brcond (i32 (setge GPR:$rs1, oimm16:$rs2)), bb:$imm16),
           (BF32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
 
+  def : Pat<(brcond (i32 (setne (and GPR:$rs, imm32_1_pop_bit:$im), 0)),
+                    bb:$imm16),
+            (BT32 (BTSTI32 GPR:$rs, (LowestSetBit imm32_1_pop_bit:$im)),
+                  bb:$imm16)>;
+  def : Pat<(brcond (i32 (seteq (and GPR:$rs, imm32_1_pop_bit:$im), 0)),
+                    bb:$imm16),
+            (BF32 (BTSTI32 GPR:$rs, (LowestSetBit imm32_1_pop_bit:$im)),
+                  bb:$imm16)>;
 }
 
 let Predicates = [iHas2E3] in {
 
 def : Pat<(brcond (i32 (setne GPR:$rs1, GPR:$rs2)), bb:$imm16),
           (BT32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
 def : Pat<(brcond (i32 (seteq GPR:$rs1, GPR:$rs2)), bb:$imm16),
           (BF32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;

 def : Pat<(brcond (i32 (setgt GPR:$rs1, (i32 0))), bb:$imm16),
           (BHZ32 GPR:$rs1, bb:$imm16)>;
 def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 0))), bb:$imm16),
           (BLSZ32 GPR:$rs1, bb:$imm16)>;
 }
 
 // Compare Patterns.
 let Predicates = [iHas2E3] in {
   def : Pat<(setne GPR:$rs1, GPR:$rs2),
             (CMPNE32 GPR:$rs1, GPR:$rs2)>;
   def : Pat<(i32 (seteq GPR:$rs1, GPR:$rs2)),
             (MVCV32 (CMPNE32 GPR:$rs1, GPR:$rs2))>;
   def : Pat<(setuge GPR:$rs1, GPR:$rs2),
             (CMPHS32 GPR:$rs1, GPR:$rs2)>;
   def : Pat<(setule GPR:$rs1, GPR:$rs2),
             (CMPHS32 GPR:$rs2, GPR:$rs1)>;
   def : Pat<(i32 (setult GPR:$rs1, GPR:$rs2)),

 def : Pat<(select (i32 (setult GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
           (MOVF32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
 
 def : Pat<(select (i32 (setlt GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
           (MOVT32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
 def : Pat<(select (i32 (setge GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
           (MOVF32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
 
+def : Pat<(select (i32 (setne (and GPR:$rs, imm32_1_pop_bit:$im), 0)),
+                  GPR:$true, GPR:$false),
+          (MOVT32 (BTSTI32 GPR:$rs, (LowestSetBit imm32_1_pop_bit:$im)),
+                  GPR:$true, GPR:$false)>;
+def : Pat<(select (i32 (seteq (and GPR:$rs, imm32_1_pop_bit:$im), 0)),
+                  GPR:$true, GPR:$false),
+          (MOVF32 (BTSTI32 GPR:$rs, (LowestSetBit imm32_1_pop_bit:$im)),
+                  GPR:$true, GPR:$false)>;
+
 def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
           (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
 def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
           (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
 }
 
 
 let Predicates = [iHas2E3] in {

llvm/test/CodeGen/CSKY/br.ll

label1:
   ret i1 1
 label2:
   ret i1 0
 }
 
 define i32 @br_bit_test_eq_0(i32 %c) {
 ; CHECK-LABEL: br_bit_test_eq_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    bnez32 a0, .LBB145_2
+; CHECK-NEXT:    btsti16 a0, 17
+; CHECK-NEXT:    bt32 .LBB145_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB145_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: br_bit_test_eq_0:
label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @br_bit_test_ne_0(i32 %c) {
 ; CHECK-LABEL: br_bit_test_ne_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    bez32 a0, .LBB146_2
+; CHECK-NEXT:    btsti16 a0, 17
+; CHECK-NEXT:    bf32 .LBB146_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB146_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: br_bit_test_ne_0:
label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @br_bit_test_eq_mask(i32 %c) {
 ; CHECK-LABEL: br_bit_test_eq_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    bez32 a0, .LBB147_2
+; CHECK-NEXT:    btsti16 a0, 17
+; CHECK-NEXT:    bf32 .LBB147_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB147_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: br_bit_test_eq_mask:
label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @br_bit_test_ne_mask(i32 %c) {
 ; CHECK-LABEL: br_bit_test_ne_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    bnez32 a0, .LBB148_2
+; CHECK-NEXT:    btsti16 a0, 17
+; CHECK-NEXT:    bt32 .LBB148_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB148_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: br_bit_test_ne_mask:

llvm/test/CodeGen/CSKY/select.ll

 entry:
   %ret = select i1 %c, i1 %m, i1 %n
   ret i1 %ret
 }
 
 define i32 @select_bit_test_eq_0(i32 %0) {
 ; CHECK-LABEL: select_bit_test_eq_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    cmpnei16 a0, 0
+; CHECK-NEXT:    btsti16 a0, 17
 ; CHECK-NEXT:    movi16 a0, 23
 ; CHECK-NEXT:    movi16 a1, 1
 ; CHECK-NEXT:    movf32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_bit_test_eq_0:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
; GENERIC-NEXT:    rts16
   %3 = icmp eq i32 %2, 0
   %4 = select i1 %3, i32 1, i32 23
   ret i32 %4
 }
 
 define i32 @select_bit_test_ne_0(i32 %0) {
 ; CHECK-LABEL: select_bit_test_ne_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    cmpnei16 a0, 0
+; CHECK-NEXT:    btsti16 a0, 17
 ; CHECK-NEXT:    movi16 a0, 34
 ; CHECK-NEXT:    movi16 a1, 5
 ; CHECK-NEXT:    movt32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_bit_test_ne_0:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
; GENERIC-NEXT:    rts16
   %3 = icmp ne i32 %2, 0
   %4 = select i1 %3, i32 5, i32 34
   ret i32 %4
 }
 
 define i32 @select_bit_test_eq_mask(i32 %0) {
 ; CHECK-LABEL: select_bit_test_eq_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    cmpnei16 a0, 0
+; CHECK-NEXT:    btsti16 a0, 17
 ; CHECK-NEXT:    movi16 a0, 5
 ; CHECK-NEXT:    movi16 a1, 34
 ; CHECK-NEXT:    movt32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_bit_test_eq_mask:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
; GENERIC-NEXT:    rts16
   %3 = icmp eq i32 %2, 131072
   %4 = select i1 %3, i32 34, i32 5
   ret i32 %4
 }
 
 define i32 @select_bit_test_ne_mask(i32 %0) {
 ; CHECK-LABEL: select_bit_test_ne_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    cmpnei16 a0, 0
+; CHECK-NEXT:    btsti16 a0, 17
 ; CHECK-NEXT:    movi16 a0, 34
 ; CHECK-NEXT:    movi16 a1, 5
 ; CHECK-NEXT:    movt32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_bit_test_ne_mask:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
; GENERIC-NEXT:    rts16
   %3 = icmp eq i32 %2, 131072
   %4 = select i1 %3, i32 5, i32 34
   ret i32 %4
 }
 
 define i32 @select_lowbit_test_ne_0(i32 %0) {
 ; CHECK-LABEL: select_lowbit_test_ne_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi32 a0, a0, 256
 ; CHECK-NEXT:    cmpnei16 a0, 0
 ; CHECK-NEXT:    movi16 a0, 34
 ; CHECK-NEXT:    movi16 a1, 5
 ; CHECK-NEXT:    movt32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_lowbit_test_ne_0:
 ; GENERIC:       # %bb.0: