[CSKY] Optimize conditional branch and value select with BTSTI

[benshi001]

llvm/test/CodeGen/CSKY/select.ll

8328

This test is not optimized with BTSTI due to the immediate 256 can be directly encoded into ANDI.

[benshi001]

Not sure why it reports patch application failed, but this patch did pass all tests on my localhost.

[zixuan-wu]

llvm/lib/Target/CSKY/CSKYInstrInfo.td

1251

can this opt also applied here?

[benshi001]

llvm/lib/Target/CSKY/CSKYInstrInfo.td

1251

Thanks. I have added that, and along with a test in llvm/test/CodeGen/CSKY/cmp-i.ll.

[benshi001]

llvm/lib/Target/CSKY/CSKYInstrInfo.td

170

This is a typo in my previous commit. The max immediate can be directly encoded into ANDI32 is 0xfff, not 0xffff.

This is a typo, need not another patch.

llvm/lib/Target/CSKY/CSKYInstrInfo.td

 // case can be opimized to (ORI32/ORI16 x, imm).
 def imm32_1_pop_bit_XFORM : SDNodeXForm<imm, [{
   uint32_t I = N->getZExtValue();
   return CurDAG->getTargetConstant(llvm::Log2_32(I), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 def imm32_1_pop_bit : PatLeaf<(imm), [{
   uint32_t I = N->getZExtValue();
-  return llvm::popcount(I) == 1 && I > 0xffff;
+  return llvm::popcount(I) == 1 && I > 0xfff;
 }]>;
 
 // Optimize (and x, imm) to (BCLRI x, log2(~imm)). We should exclude the
 // case can be opimized to (ANDNI x, ~imm).
 def imm32_1_zero_bit_XFORM : SDNodeXForm<imm, [{
   uint32_t I = ~N->getZExtValue();
   return CurDAG->getTargetConstant(llvm::Log2_32(I), SDLoc(N),
                                    N->getValueType(0));
def : Pat<(brcond (i32 (cond0 GPR:$rs1, uimm16:$rs2)), bb:$imm16),
           (BT32 (inst GPR:$rs1, imm_ty:$rs2), bb:$imm16)>;
   def : Pat<(brcond (i32 (cond1 GPR:$rs1, uimm16:$rs2)), bb:$imm16),
           (BF32 (inst GPR:$rs1, imm_ty:$rs2), bb:$imm16)>;
 }
 
 defm : BTF32Pat0<setne, seteq, uimm16, CMPNEI32>;
 defm : BTF32Pat0<setuge, setult, oimm16, CMPHSI32>;
 defm : BTF32Pat0<setlt, setge, oimm16, CMPLTI32>;
+
+def : Pat<(brcond (i32 (setne (and GPR:$rs, imm32_1_pop_bit:$im), 0)), bb:$imm16),
+          (BT32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),
+                bb:$imm16)>;
+def : Pat<(brcond (i32 (seteq (and GPR:$rs, imm32_1_pop_bit:$im), 0)), bb:$imm16),
+          (BF32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),
+                bb:$imm16)>;
 }
 
 let Predicates = [iHas2E3] in {
 
 def : Pat<(brcond (i32 (setne GPR:$rs1, GPR:$rs2)), bb:$imm16),
           (BT32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
 def : Pat<(brcond (i32 (seteq GPR:$rs1, GPR:$rs2)), bb:$imm16),
           (BF32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;

 def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 0))), bb:$imm16),
           (BLSZ32 GPR:$rs1, bb:$imm16)>;
 def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 -1))), bb:$imm16),
           (BLZ32 GPR:$rs1, bb:$imm16)>;
 }
 
 // Compare Patterns.
 let Predicates = [iHas2E3] in {
   def : Pat<(setne GPR:$rs1, GPR:$rs2),
             (CMPNE32 GPR:$rs1, GPR:$rs2)>;
+  def : Pat<(setne (and GPR:$rs, imm32_1_pop_bit:$im), 0),
+            (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im))>;
   def : Pat<(i32 (seteq GPR:$rs1, GPR:$rs2)),
             (MVCV32 (CMPNE32 GPR:$rs1, GPR:$rs2))>;
   def : Pat<(setuge GPR:$rs1, GPR:$rs2),
             (CMPHS32 GPR:$rs1, GPR:$rs2)>;
   def : Pat<(setule GPR:$rs1, GPR:$rs2),
             (CMPHS32 GPR:$rs2, GPR:$rs1)>;
   def : Pat<(i32 (setult GPR:$rs1, GPR:$rs2)),
             (MVCV32 (CMPHS32 GPR:$rs1, GPR:$rs2))>;

 defm : MOVTF32Pat0<setne, seteq, uimm16, CMPNEI32>;
 defm : MOVTF32Pat0<setuge, setult, oimm16, CMPHSI32>;
 defm : MOVTF32Pat0<setlt, setge, oimm16, CMPLTI32>;
 
 def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
           (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
 def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
           (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
-}
 
+def : Pat<(select (i32 (setne (and GPR:$rs, imm32_1_pop_bit:$im), 0)),
+                  GPR:$true, GPR:$false),
+          (MOVT32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),
+                  GPR:$true, GPR:$false)>;
+def : Pat<(select (i32 (seteq (and GPR:$rs, imm32_1_pop_bit:$im), 0)),
+                  GPR:$true, GPR:$false),
+          (MOVF32 (BTSTI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$im)),
+                  GPR:$true, GPR:$false)>;
+}
 
 let Predicates = [iHas2E3] in {
 def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
           (INCT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
 def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5:$imm), GPR:$false),
           (INCF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx, uimm5:$imm)>;
 def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), (add GPR:$rx, uimm5_neg:$imm), GPR:$false),
           (DECT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$false, GPR:$rx,

llvm/test/CodeGen/CSKY/br.ll

label1:
   ret i1 1
 label2:
   ret i1 0
 }
 
 define i32 @br_bit_test_eq_0(i32 %c) {
 ; CHECK-LABEL: br_bit_test_eq_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    bnez32 a0, .LBB145_2
+; CHECK-NEXT:    btsti16 a0, 17
+; CHECK-NEXT:    bt32 .LBB145_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB145_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: br_bit_test_eq_0:
label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @br_bit_test_ne_0(i32 %c) {
 ; CHECK-LABEL: br_bit_test_ne_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    bez32 a0, .LBB146_2
+; CHECK-NEXT:    btsti16 a0, 17
+; CHECK-NEXT:    bf32 .LBB146_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB146_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: br_bit_test_ne_0:
label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @br_bit_test_eq_mask(i32 %c) {
 ; CHECK-LABEL: br_bit_test_eq_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    bez32 a0, .LBB147_2
+; CHECK-NEXT:    btsti16 a0, 17
+; CHECK-NEXT:    bf32 .LBB147_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB147_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: br_bit_test_eq_mask:
label1:
   ret i32 1
 label2:
   ret i32 0
 }
 
 define i32 @br_bit_test_ne_mask(i32 %c) {
 ; CHECK-LABEL: br_bit_test_ne_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    bnez32 a0, .LBB148_2
+; CHECK-NEXT:    btsti16 a0, 17
+; CHECK-NEXT:    bt32 .LBB148_2
 ; CHECK-NEXT:  # %bb.1: # %label1
 ; CHECK-NEXT:    movi16 a0, 1
 ; CHECK-NEXT:    rts16
 ; CHECK-NEXT:  .LBB148_2: # %label2
 ; CHECK-NEXT:    movi16 a0, 0
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: br_bit_test_ne_mask:

llvm/test/CodeGen/CSKY/cmp-i.ll

 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp eq i32 %x, 4097000
   ret i1 %icmp
 }
 
+define i1 @icmpRI_AND_ne(i32 %x) {
+; CHECK-LABEL: icmpRI_AND_ne:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    btsti16 a0, 15
+; CHECK-NEXT:    mvc32 a0
+; CHECK-NEXT:    rts16
+;
+; GENERIC-LABEL: icmpRI_AND_ne:
+; GENERIC:       # %bb.0: # %entry
+; GENERIC-NEXT:    .cfi_def_cfa_offset 0
+; GENERIC-NEXT:    subi16 sp, sp, 4
+; GENERIC-NEXT:    .cfi_def_cfa_offset 4
+; GENERIC-NEXT:    movi16 a1, 0
+; GENERIC-NEXT:    lsli16 a2, a1, 24
+; GENERIC-NEXT:    lsli16 a3, a1, 16
+; GENERIC-NEXT:    or16 a3, a2
+; GENERIC-NEXT:    movi16 a2, 128
+; GENERIC-NEXT:    lsli16 a2, a2, 8
+; GENERIC-NEXT:    or16 a2, a3
+; GENERIC-NEXT:    or16 a2, a1
+; GENERIC-NEXT:    and16 a2, a0
+; GENERIC-NEXT:    cmpnei16 a2, 0
+; GENERIC-NEXT:    mvcv16 a1
+; GENERIC-NEXT:    movi16 a0, 1
+; GENERIC-NEXT:    subu16 a0, a1
+; GENERIC-NEXT:    addi16 sp, sp, 4
+; GENERIC-NEXT:    rts16
+entry:
+  %and = and i32 %x, 32768
+  %icmp = icmp ne i32 %and, 0
+  ret i1 %icmp
+}
+
 define i1 @ICMP_LONG_eq(i64 %x, i64 %y) {
 ; CHECK-LABEL: ICMP_LONG_eq:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xor16 a1, a3
 ; CHECK-NEXT:    xor16 a0, a2
 ; CHECK-NEXT:    or16 a0, a1
 ; CHECK-NEXT:    cmpnei16 a0, 0
 ; CHECK-NEXT:    mvcv16 a0

 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    cmphs16 a1, a3
 ; GENERIC-NEXT:    mvcv16 l0
 ; GENERIC-NEXT:    cmphs16 a0, a2
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpne16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB25_2
+; GENERIC-NEXT:    bt16 .LBB26_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    mov16 a0, l0
-; GENERIC-NEXT:  .LBB25_2: # %entry
+; GENERIC-NEXT:  .LBB26_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld16.w l0, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp ugt i64 %y, %x
   ret i1 %icmp
 }

 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    cmpnei16 a1, 0
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    movi16 a2, 1
 ; GENERIC-NEXT:    cmphs16 a2, a0
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB26_2
+; GENERIC-NEXT:    bt16 .LBB27_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    subu16 a2, a1
 ; GENERIC-NEXT:    mov16 a0, a2
-; GENERIC-NEXT:  .LBB26_2: # %entry
+; GENERIC-NEXT:  .LBB27_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp ugt i64 %x, 1
   ret i1 %icmp
 }
 
 define i1 @ICMP_SHORT_ugt(i16 %x, i16 %y) {

 ; GENERIC-NEXT:    cmphs16 a3, a1
 ; GENERIC-NEXT:    mvcv16 l1
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    cmphs16 a2, l0
 ; GENERIC-NEXT:    mvcv16 a2
 ; GENERIC-NEXT:    cmpne16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB36_2
+; GENERIC-NEXT:    bt16 .LBB37_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    subu16 a0, l1
-; GENERIC-NEXT:    br32 .LBB36_3
-; GENERIC-NEXT:  .LBB36_2:
+; GENERIC-NEXT:    br32 .LBB37_3
+; GENERIC-NEXT:  .LBB37_2:
 ; GENERIC-NEXT:    subu16 a0, a2
-; GENERIC-NEXT:  .LBB36_3: # %entry
+; GENERIC-NEXT:  .LBB37_3: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld16.w l0, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    ld16.w l1, (sp, 4) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 8
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp uge i64 %y, %x
   ret i1 %icmp

 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    cmphs16 a3, a1
 ; GENERIC-NEXT:    mvcv16 l0
 ; GENERIC-NEXT:    cmphs16 a2, a0
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpne16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB47_2
+; GENERIC-NEXT:    bt16 .LBB48_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    mov16 a0, l0
-; GENERIC-NEXT:  .LBB47_2: # %entry
+; GENERIC-NEXT:  .LBB48_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld16.w l0, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp ult i64 %y, %x
   ret i1 %icmp
 }

 ; GENERIC-NEXT:    cmphs16 a1, a3
 ; GENERIC-NEXT:    mvcv16 l1
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    cmphs16 l0, a2
 ; GENERIC-NEXT:    mvcv16 a2
 ; GENERIC-NEXT:    cmpne16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB58_2
+; GENERIC-NEXT:    bt16 .LBB59_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    subu16 a0, l1
-; GENERIC-NEXT:    br32 .LBB58_3
-; GENERIC-NEXT:  .LBB58_2:
+; GENERIC-NEXT:    br32 .LBB59_3
+; GENERIC-NEXT:  .LBB59_2:
 ; GENERIC-NEXT:    subu16 a0, a2
-; GENERIC-NEXT:  .LBB58_3: # %entry
+; GENERIC-NEXT:  .LBB59_3: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld16.w l0, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    ld16.w l1, (sp, 4) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 8
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp ule i64 %y, %x
   ret i1 %icmp

 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
 ; GENERIC-NEXT:    subi16 sp, sp, 4
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    cmphsi16 a0, 2
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpnei16 a1, 0
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB59_2
+; GENERIC-NEXT:    bt16 .LBB60_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    movi16 a0, 0
-; GENERIC-NEXT:  .LBB59_2: # %entry
+; GENERIC-NEXT:  .LBB60_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp ule i64 %x, 1
   ret i1 %icmp
 }
 
 define i1 @ICMP_SHORT_ule(i16 %x, i16 %y) {

 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    cmplt16 a1, a3
 ; GENERIC-NEXT:    mvcv16 l0
 ; GENERIC-NEXT:    cmphs16 a0, a2
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpne16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB69_2
+; GENERIC-NEXT:    bt16 .LBB70_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    subu16 a0, l0
-; GENERIC-NEXT:  .LBB69_2: # %entry
+; GENERIC-NEXT:  .LBB70_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld16.w l0, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp sgt i64 %y, %x
   ret i1 %icmp
 }

 ; GENERIC-NEXT:    cmplt16 a2, a1
 ; GENERIC-NEXT:    mvcv16 a2
 ; GENERIC-NEXT:    movi16 a3, 1
 ; GENERIC-NEXT:    cmphs16 a3, a0
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpnei16 a1, 0
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB70_2
+; GENERIC-NEXT:    bt16 .LBB71_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    subu16 a3, a2
 ; GENERIC-NEXT:    mov16 a0, a3
-; GENERIC-NEXT:  .LBB70_2: # %entry
+; GENERIC-NEXT:  .LBB71_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp sgt i64 %x, 1
   ret i1 %icmp
 }
 
 define i1 @ICMP_SHORT_sgt(i16 %x, i16 %y) {

 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    cmphs16 a2, a0
 ; GENERIC-NEXT:    mvcv16 a2
 ; GENERIC-NEXT:    cmplt16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpne16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bf16 .LBB80_2
+; GENERIC-NEXT:    bf16 .LBB81_2
 ; GENERIC-NEXT:  # %bb.1:
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    subu16 a0, a2
-; GENERIC-NEXT:  .LBB80_2: # %entry
+; GENERIC-NEXT:  .LBB81_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp sge i64 %y, %x
   ret i1 %icmp
 }
 
 define i1 @ICMP_LONG_I_sge(i64 %x) {

 ; GENERIC-NEXT:    cmplt16 a0, a1
 ; GENERIC-NEXT:    mvcv16 a3
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    cmpnei16 a2, 0
 ; GENERIC-NEXT:    mvcv16 a2
 ; GENERIC-NEXT:    cmpnei16 a1, 0
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB81_2
+; GENERIC-NEXT:    bt16 .LBB82_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    subu16 a0, a3
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
-; GENERIC-NEXT:  .LBB81_2:
+; GENERIC-NEXT:  .LBB82_2:
 ; GENERIC-NEXT:    subu16 a0, a2
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp sge i64 %x, 1
   ret i1 %icmp
 }
 

 ; GENERIC-NEXT:    .cfi_def_cfa_offset 8
 ; GENERIC-NEXT:    cmplt16 a3, a1
 ; GENERIC-NEXT:    mvcv16 l0
 ; GENERIC-NEXT:    cmphs16 a2, a0
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpne16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB91_2
+; GENERIC-NEXT:    bt16 .LBB92_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    subu16 a0, l0
-; GENERIC-NEXT:  .LBB91_2: # %entry
+; GENERIC-NEXT:  .LBB92_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    ld16.w l0, (sp, 0) # 4-byte Folded Reload
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp slt i64 %y, %x
   ret i1 %icmp
 }

 ; GENERIC-NEXT:    movi16 a2, 0
 ; GENERIC-NEXT:    cmplt16 a1, a2
 ; GENERIC-NEXT:    mvcv16 a2
 ; GENERIC-NEXT:    cmpnei16 a0, 0
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpnei16 a1, 0
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB92_2
+; GENERIC-NEXT:    bt16 .LBB93_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    subu16 a0, a2
-; GENERIC-NEXT:  .LBB92_2: # %entry
+; GENERIC-NEXT:  .LBB93_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp slt i64 %x, 1
   ret i1 %icmp
 }
 
 define i1 @ICMP_SHORT_slt(i16 %x, i16 %y) {

 ; GENERIC-NEXT:    .cfi_def_cfa_offset 4
 ; GENERIC-NEXT:    cmphs16 a0, a2
 ; GENERIC-NEXT:    mvcv16 a2
 ; GENERIC-NEXT:    cmplt16 a1, a3
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpne16 a3, a1
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bf16 .LBB102_2
+; GENERIC-NEXT:    bf16 .LBB103_2
 ; GENERIC-NEXT:  # %bb.1:
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    subu16 a0, a2
-; GENERIC-NEXT:  .LBB102_2: # %entry
+; GENERIC-NEXT:  .LBB103_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp sle i64 %y, %x
   ret i1 %icmp
 }
 
 define i1 @ICMP_LONG_I_sle(i64 %x) {

 ; GENERIC-NEXT:    movi16 a2, 0
 ; GENERIC-NEXT:    cmplt16 a1, a2
 ; GENERIC-NEXT:    mvcv16 a2
 ; GENERIC-NEXT:    cmphsi16 a0, 2
 ; GENERIC-NEXT:    mvcv16 a0
 ; GENERIC-NEXT:    cmpnei16 a1, 0
 ; GENERIC-NEXT:    mvcv16 a1
 ; GENERIC-NEXT:    btsti16 a1, 0
-; GENERIC-NEXT:    bt16 .LBB103_2
+; GENERIC-NEXT:    bt16 .LBB104_2
 ; GENERIC-NEXT:  # %bb.1: # %entry
 ; GENERIC-NEXT:    movi16 a0, 1
 ; GENERIC-NEXT:    subu16 a0, a2
-; GENERIC-NEXT:  .LBB103_2: # %entry
+; GENERIC-NEXT:  .LBB104_2: # %entry
 ; GENERIC-NEXT:    addi16 sp, sp, 4
 ; GENERIC-NEXT:    rts16
 entry:
   %icmp = icmp sle i64 %x, 1
   ret i1 %icmp
 }
 
 define i1 @ICMP_SHORT_sle(i16 %x, i16 %y) {

llvm/test/CodeGen/CSKY/select.ll

 entry:
   %ret = select i1 %c, i1 %m, i1 %n
   ret i1 %ret
 }
 
 define i32 @select_bit_test_eq_0(i32 %0) {
 ; CHECK-LABEL: select_bit_test_eq_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    cmpnei16 a0, 0
+; CHECK-NEXT:    btsti16 a0, 17
 ; CHECK-NEXT:    movi16 a0, 23
 ; CHECK-NEXT:    movi16 a1, 1
 ; CHECK-NEXT:    movf32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_bit_test_eq_0:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
; GENERIC-NEXT:    rts16
   %3 = icmp eq i32 %2, 0
   %4 = select i1 %3, i32 1, i32 23
   ret i32 %4
 }
 
 define i32 @select_bit_test_ne_0(i32 %0) {
 ; CHECK-LABEL: select_bit_test_ne_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    cmpnei16 a0, 0
+; CHECK-NEXT:    btsti16 a0, 17
 ; CHECK-NEXT:    movi16 a0, 34
 ; CHECK-NEXT:    movi16 a1, 5
 ; CHECK-NEXT:    movt32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_bit_test_ne_0:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
; GENERIC-NEXT:    rts16
   %3 = icmp ne i32 %2, 0
   %4 = select i1 %3, i32 5, i32 34
   ret i32 %4
 }
 
 define i32 @select_bit_test_eq_mask(i32 %0) {
 ; CHECK-LABEL: select_bit_test_eq_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    cmpnei16 a0, 0
+; CHECK-NEXT:    btsti16 a0, 17
 ; CHECK-NEXT:    movi16 a0, 5
 ; CHECK-NEXT:    movi16 a1, 34
 ; CHECK-NEXT:    movt32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_bit_test_eq_mask:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
; GENERIC-NEXT:    rts16
   %3 = icmp eq i32 %2, 131072
   %4 = select i1 %3, i32 34, i32 5
   ret i32 %4
 }
 
 define i32 @select_bit_test_ne_mask(i32 %0) {
 ; CHECK-LABEL: select_bit_test_ne_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    and16 a0, a1
-; CHECK-NEXT:    cmpnei16 a0, 0
+; CHECK-NEXT:    btsti16 a0, 17
 ; CHECK-NEXT:    movi16 a0, 34
 ; CHECK-NEXT:    movi16 a1, 5
 ; CHECK-NEXT:    movt32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_bit_test_ne_mask:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    .cfi_def_cfa_offset 0
; GENERIC-NEXT:    rts16
   %3 = icmp eq i32 %2, 131072
   %4 = select i1 %3, i32 5, i32 34
   ret i32 %4
 }
 
 define i32 @select_lowbit_test_ne_0(i32 %0) {
 ; CHECK-LABEL: select_lowbit_test_ne_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi32 a0, a0, 256
 ; CHECK-NEXT:    cmpnei16 a0, 0
 ; CHECK-NEXT:    movi16 a0, 34
 ; CHECK-NEXT:    movi16 a1, 5
 ; CHECK-NEXT:    movt32 a0, a1
 ; CHECK-NEXT:    rts16
 ;
 ; GENERIC-LABEL: select_lowbit_test_ne_0:
 ; GENERIC:       # %bb.0: