[CSKY] Optimize ANDI/ORI to BSETI/BCLRI for specific immediates

[benshi001]

llvm/test/CodeGen/CSKY/bseti_bclri.ll

25

This is not optimized to two BSETI due to the immediate can be encoded to ORI32.

34

This is not optimized to two BSETI due to the immediate can be encoded to ORI32.

43

This is not optimized to two BSETIs due to the immediate can be composed via a single MOVIH32.

68

This is not optimized to two BSETIs due to the immediate is used twice.

96

This is not optimized to two BCLRI due to the immediate can be encoded into ANDNI.

103

This is not optimized to two BCLRI due to the immediate can be encoded into ANDNI.

134

This is not optimized to two BCLRI32 due to the immediate is used twice.

llvm/lib/Target/CSKY/CSKYInstrInfo.td

 }
 
 def uimm_shift : Operand<i32>, ImmLeaf<i32, "return isUInt<2>(Imm);"> {
   let EncoderMethod = "getImmShiftOpValue";
   let ParserMatchClass = UImmAsmOperand<2>;
   let DecoderMethod = "decodeImmShiftOpValue";
 }
 
-// Optimize (or x, imm) to (BSETI x, log2(imm)). We should exclude the
-// case can be opimized to (ORI32/ORI16 x, imm).
-def uimm_bseti_1_XFORM : SDNodeXForm<imm, [{
+def LowestSetBit : SDNodeXForm<imm, [{
   uint32_t I = N->getZExtValue();
-  return CurDAG->getTargetConstant(llvm::Log2_32(I), SDLoc(N),
+  return CurDAG->getTargetConstant(llvm::countr_zero<uint32_t>(I), SDLoc(N),
                                    N->getValueType(0));
 }]>;
-def uimm_bseti_1 : PatLeaf<(imm), [{
+def HighestSetBit : SDNodeXForm<imm, [{
   uint32_t I = N->getZExtValue();
-  return llvm::popcount(I) == 1 && I > 0xffff;
+  return CurDAG->getTargetConstant(31 - llvm::countl_zero<uint32_t>(I),
+                                   SDLoc(N), N->getValueType(0));
 }]>;
-
-// Optimize (and x, imm) to (BCLRI x, log2(~imm)). We should exclude the
-// case can be opimized to (ANDNI x, ~imm).
-def uimm_bclri_1_XFORM : SDNodeXForm<imm, [{
+def LowestZeroBit : SDNodeXForm<imm, [{
   uint32_t I = ~N->getZExtValue();
-  return CurDAG->getTargetConstant(llvm::Log2_32(I), SDLoc(N),
+  return CurDAG->getTargetConstant(llvm::countr_zero<uint32_t>(I), SDLoc(N),
                                    N->getValueType(0));
 }]>;
-def uimm_bclri_1 : PatLeaf<(imm), [{
+def HighestZeroBit : SDNodeXForm<imm, [{
+  uint32_t I = ~N->getZExtValue();
+  return CurDAG->getTargetConstant(31 - llvm::countl_zero<uint32_t>(I),
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
+// Optimize (or x, imm) to (BSETI x, log2(imm)). We should exclude the
+// case can be opimized to (ORI32/ORI16 x, imm).
+def imm32_1_pop_bit : PatLeaf<(imm), [{
+  uint32_t I = N->getZExtValue();
+  return llvm::popcount(I) == 1 && !isUInt<16>(I);
+}]>;
+// Optimize (or x, imm) to (BSETI (BSETI x, i0), i1), in which
+// imm = (1 << i0) | (1 << i1), and imm has to be composed via
+// a MOVIH32+ORI32 pair.
+def imm32_2_pop_bits : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  uint32_t I = N->getZExtValue();
+  // Reject immediates can be composed via a single MOVIH32 or directly
+  // encoded into the IMM16 field of ORI32.
+  if (isUInt<16>(I) || isShiftedUInt<16, 16>(I))
+    return false;
+  return llvm::popcount(I) == 2;
+}]>;
+// Optimize (and x, imm) to (BCLRI (BCLRI x, i0), i1), in which
+// imm = ~((1 << i0) | (1 << i1)).
+def imm32_30_pop_bits : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  uint32_t I = ~N->getZExtValue();
+  // Reject immediates can be directly encoded into the IMM12 field of ANDNI32.
+  if (isUInt<12>(I))
+    return false;
+  return llvm::popcount(I) == 2;
+}]>;
+// Optimize (and x, imm) to (BCLRI x, log2(~imm)). We should exclude the
+// case can be opimized to (ANDNI x, ~imm).
+def imm32_31_pop_bits : PatLeaf<(imm), [{
   uint32_t I = ~N->getZExtValue();
-  return llvm::popcount(I) == 1 && I > 0xfff;
+  return llvm::popcount(I) == 1 && !isUInt<12>(I);
 }]>;
 
 def CSKYSymbol : AsmOperandClass {
   let Name = "CSKYSymbol";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = "InvalidCSKYSymbol";
   let ParserMethod = "parseCSKYSymbol";
 }

 
 // Constant materialize patterns.
 let Predicates = [iHasE2] in
   def : Pat<(i32 imm:$imm),
             (ORI32 (MOVIH32 (uimm32_hi16 imm:$imm)), (uimm32_lo16 imm:$imm))>;
 
 // Bit operations.
 let Predicates = [iHasE2] in {
-  def : Pat<(or GPR:$rs, uimm_bseti_1:$imm),
-            (BSETI32 GPR:$rs, (uimm_bseti_1_XFORM uimm_bseti_1:$imm))>;
-  def : Pat<(and GPR:$rs, uimm_bclri_1:$imm),
-            (BCLRI32 GPR:$rs, (uimm_bclri_1_XFORM uimm_bclri_1:$imm))>;
+  def : Pat<(or GPR:$rs, imm32_1_pop_bit:$imm),
+            (BSETI32 GPR:$rs, (LowestSetBit imm32_1_pop_bit:$imm))>;
+  def : Pat<(or GPR:$rs, imm32_2_pop_bits:$imm),
+            (BSETI32 (BSETI32 GPR:$rs, (LowestSetBit imm32_2_pop_bits:$imm)),
+                     (HighestSetBit imm32_2_pop_bits:$imm))>;
+  def : Pat<(and GPR:$rs, imm32_30_pop_bits:$imm),
+            (BCLRI32 (BCLRI32 GPR:$rs, (LowestZeroBit imm32_30_pop_bits:$imm)),
+                     (HighestZeroBit imm32_30_pop_bits:$imm))>;
+  def : Pat<(and GPR:$rs, imm32_31_pop_bits:$imm),
+            (BCLRI32 GPR:$rs, (LowestZeroBit imm32_31_pop_bits:$imm))>;
 }
 
 // Other operations.
 let Predicates = [iHasE2] in {
   def : Pat<(rotl GPR:$rs1, GPR:$rs2),
             (ROTL32 GPR:$rs1, (ANDI32 GPR:$rs2, 0x1f))>;
   let Predicates = [iHas2E3] in {
     def : Pat<(bitreverse GPR:$rx), (BREV32 GPR:$rx)>;

llvm/test/CodeGen/CSKY/bseti_bclri.ll

 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 131072
  ret i32 %2
 }
 
 define i32 @test_or_192(i32 noundef %0) {
 ; CHECK-LABEL: test_or_192:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori32 a0, a0, 192
 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 192
  ret i32 %2
 }
 
 define i32 @test_or_3072(i32 noundef %0) {
 ; CHECK-LABEL: test_or_3072:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori32 a0, a0, 3072
 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 3072
  ret i32 %2
 }
 
 define i32 @test_or_196608(i32 noundef %0) {
 ; CHECK-LABEL: test_or_196608:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movih32 a1, 3
 ; CHECK-NEXT:    or16 a0, a1
 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 196608
  ret i32 %2
 }
 
 define i32 @test_or_65540(i32 noundef %0) {
 ; CHECK-LABEL: test_or_65540:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 1
-; CHECK-NEXT:    ori32 a1, a1, 4
-; CHECK-NEXT:    or16 a0, a1
+; CHECK-NEXT:    bseti16 a0, 2
+; CHECK-NEXT:    bseti16 a0, 16
 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 65540
  ret i32 %2
 }
 
+define i32 @test_or_65540_twice(i32 noundef %0, i32 noundef %1) {
+; CHECK-LABEL: test_or_65540_twice:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movih32 a2, 1
+; CHECK-NEXT:    ori32 a2, a2, 4
+; CHECK-NEXT:    or16 a0, a2
+; CHECK-NEXT:    or16 a1, a2
+; CHECK-NEXT:    addu16 a0, a1
+; CHECK-NEXT:    rts16
+ %3 = or i32 %0, 65540
+ %4 = or i32 %1, 65540
+ %5 = add i32 %3, %4
+ ret i32 %5
+}
+
 define i32 @test_andnot_128(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andni32 a0, a0, 128
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -129
  ret i32 %2
 }
 
 define i32 @test_andnot_131072(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_131072:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bclri16 a0, 17
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -131073
  ret i32 %2
 }
 
 define i32 @test_andnot_192(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_192:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andni32 a0, a0, 192
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -193
  ret i32 %2
 }
 
 define i32 @test_andnot_3072(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_3072:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andni32 a0, a0, 3072
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -3073
  ret i32 %2
 }
 
 define i32 @test_andnot_1966608(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_1966608:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movih32 a1, 65505
 ; CHECK-NEXT:    ori32 a1, a1, 65007
 ; CHECK-NEXT:    and16 a0, a1
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -1966609
  ret i32 %2
 }
 
 define i32 @test_andnot_65540(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_65540:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 65534
-; CHECK-NEXT:    ori32 a1, a1, 65531
-; CHECK-NEXT:    and16 a0, a1
+; CHECK-NEXT:    bclri16 a0, 2
+; CHECK-NEXT:    bclri16 a0, 16
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -65541
  ret i32 %2
 }
+
+define i32 @test_andnot_65540_twice(i32 noundef %0, i32 noundef %1) {
+; CHECK-LABEL: test_andnot_65540_twice:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movih32 a2, 65534
+; CHECK-NEXT:    ori32 a2, a2, 65531
+; CHECK-NEXT:    and16 a0, a2
+; CHECK-NEXT:    and16 a1, a2
+; CHECK-NEXT:    subu16 a0, a1
+; CHECK-NEXT:    rts16
+ %3 = and i32 %0, -65541
+ %4 = and i32 %1, -65541
+ %5 = sub i32 %3, %4
+ ret i32 %5
+}