[LoongArch] Explicitly specify instruction properties

[hev]

Summary

This revision explicitly specifies the machine instruction properties instead of relying on guesswork. This is because guessing instruction properties has proven to be inaccurate, such as the machine LICM not working:

void func(char *a, char *b)
{
    int i;

    for (i = 0; i != 72526; i++)
        a[i] = b[i];
}

Guessing instruction properties:

func:                                   # @func
# %bb.0:
        move    $a2, $zero
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
        ldx.b   $a3, $a1, $a2
        stx.b   $a3, $a0, $a2
        addi.d  $a2, $a2, 1
        lu12i.w $a3, 17
        ori     $a3, $a3, 2894
        bne     $a2, $a3, .LBB0_1
# %bb.2:
        ret
.Lfunc_end0:

Explicitly specify instruction properties:

func:                                   # @func
# %bb.0:
        lu12i.w $a2, 17
        ori     $a2, $a2, 2894
        move    $a3, $zero
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
        ldx.b   $a4, $a1, $a3
        stx.b   $a4, $a0, $a3
        addi.d  $a3, $a3, 1
        bne     $a3, $a2, .LBB0_1
# %bb.2:
        ret
.Lfunc_end0:

[xen0n]

The diff is missing context lines, I guess you created the patch with plain git diff and posted the diff with the web interface... Checkout the recommendations or set up Arcanist and use arc diff. (In case of Arcanist you may have to apply some PHP 8 fixes but it should be straight-forward otherwise.)

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

779

I checked PPC and RISCV and it seems prefetch instructions should have mayLoad = 1, mayStore = 1. Otherwise I expect them to get incorrectly optimized away...

1915

These instructions should probably be hasSideEffects = 1 because they instruct the hardware to perform certain actions. Otherwise they will probably get deleted too given they don't return anything...

[hev]

Thanks for your comments.

[xen0n]

LGTM; you may want to coordinate with the author of D154183 and D154195 so no instruction will miss any marker.

[SixWeining]

LGTM. Thanks!

llvm/lib/Target/LoongArch/LoongArch.td

def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,
                                              FeatureExtLVZ,
                                              FeatureExtLBT]>;
 
 //===----------------------------------------------------------------------===//
 // Define the LoongArch target.
 //===----------------------------------------------------------------------===//
 
 def LoongArchInstrInfo : InstrInfo {
-  // guess mayLoad, mayStore, and hasSideEffects
-  // This option is a temporary migration help. It will go away.
-  let guessInstructionProperties = 1;
+  let guessInstructionProperties = 0;
 }
 
 def LoongArchAsmParser : AsmParser {
   let ShouldEmitMatchRegisterAltName = 1;
   let AllowDuplicateRegisterNames = 1;
 }
 
 def LoongArchAsmParserVariant : AsmParserVariant {

llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td

def FTINTRNE_W_S : FP_CONV<0b0000000100011010110001, "ftintrne.w.s", FPR32,
                            FPR32>;
 def FRINT_S      : FP_CONV<0b0000000100011110010001, "frint.s", FPR32, FPR32>;
 
 // Move Instructions
 def FSEL_S : FP_SEL<0b00001101000000, "fsel", FPR32>;
 def FMOV_S     : FP_MOV<0b0000000100010100100101, "fmov.s", FPR32, FPR32>;
 def MOVGR2FR_W : FP_MOV<0b0000000100010100101001, "movgr2fr.w", FPR32, GPR>;
 def MOVFR2GR_S : FP_MOV<0b0000000100010100101101, "movfr2gr.s", GPR, FPR32>;
+let hasSideEffects = 1 in {
 def MOVGR2FCSR : FP_MOV<0b0000000100010100110000, "movgr2fcsr", FCSR, GPR>;
 def MOVFCSR2GR : FP_MOV<0b0000000100010100110010, "movfcsr2gr", GPR, FCSR>;
+} // hasSideEffects = 1
 def MOVFR2CF_S : FP_MOV<0b0000000100010100110100, "movfr2cf", CFR, FPR32>;
 def MOVCF2FR_S : FP_MOV<0b0000000100010100110101, "movcf2fr", FPR32, CFR>;
 def MOVGR2CF   : FP_MOV<0b0000000100010100110110, "movgr2cf", CFR, GPR>;
 def MOVCF2GR   : FP_MOV<0b0000000100010100110111, "movcf2gr", GPR, CFR>;
 
 // Branch Instructions
 def BCEQZ : FP_BRANCH<0b01001000, "bceqz">;
 def BCNEZ : FP_BRANCH<0b01001001, "bcnez">;

llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td

 
 // Move Instructions
 def FMOV_D        : FP_MOV<0b0000000100010100100110, "fmov.d", FPR64, FPR64>;
 def MOVFRH2GR_S   : FP_MOV<0b0000000100010100101111, "movfrh2gr.s", GPR, FPR64>;
 let isCodeGenOnly = 1 in {
 def MOVFR2GR_S_64 : FP_MOV<0b0000000100010100101101, "movfr2gr.s", GPR, FPR64>;
 def FSEL_D : FP_SEL<0b00001101000000, "fsel", FPR64>;
 } // isCodeGenOnly = 1
-let Constraints = "$dst = $out" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out" in {
 def MOVGR2FRH_W : FPFmtMOV<0b0000000100010100101011, (outs FPR64:$out),
                            (ins FPR64:$dst, GPR:$src), "movgr2frh.w",
                            "$dst, $src">;
-} // Constraints = "$dst = $out"
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out"
 
 // Common Memory Access Instructions
 def FLD_D : FP_LOAD_2RI12<0b0010101110, "fld.d", FPR64>;
 def FST_D : FP_STORE_2RI12<0b0010101111, "fst.d", FPR64>;
 def FLDX_D : FP_LOAD_3R<0b00111000001101000, "fldx.d", FPR64>;
 def FSTX_D : FP_STORE_3R<0b00111000001111000, "fstx.d", FPR64>;
 
 // Bound Check Memory Access Instructions

llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td

class FPFmtMEM<bits<17> op, dag outs, dag ins, string opcstr, string opnstr,
   let Inst{9-5} = rj;
   let Inst{4-0} = fd;
 }
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class FP_ALU_2R<bits<22> op, string opstr, RegisterClass rc>
     : FPFmt2R<op, (outs rc:$fd), (ins rc:$fj), opstr, "$fd, $fj">;
 
 class FP_ALU_3R<bits<17> op, string opstr, RegisterClass rc>
     : FPFmt3R<op, (outs rc:$fd), (ins rc:$fj, rc:$fk), opstr, "$fd, $fj, $fk">;
 
 class FP_ALU_4R<bits<12> op, string opstr, RegisterClass rc>
     : FPFmt4R<op, (outs rc:$fd), (ins rc:$fj, rc:$fk, rc:$fa), opstr,
               "$fd, $fj, $fk, $fa">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 class FPCMPOpc<bits<12> value> {
   bits<12> val = value;
 }
 
 class FPCMPCond<bits<5> value> {
   bits<5> val = value;
 }
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class FP_CMP<FPCMPOpc op, FPCMPCond cond, string opstr, RegisterClass rc>
     : FPFmtFCMP<op.val, cond.val, (outs CFR:$cd), (ins rc:$fj, rc:$fk), opstr,
                 "$cd, $fj, $fk">;
 
 class FP_CONV<bits<22> op, string opstr, RegisterClass rcd, RegisterClass rcs>
     : FPFmt2R<op, (outs rcd:$fd), (ins rcs:$fj), opstr, "$fd, $fj">;
 
 class FP_MOV<bits<22> op, string opstr, RegisterClass rcd, RegisterClass rcs>
     : FPFmtMOV<op, (outs rcd:$dst), (ins rcs:$src), opstr, "$dst, $src">;
 
 class FP_SEL<bits<14> op, string opstr, RegisterClass rc>
     : FPFmtFSEL<op, (outs rc:$fd), (ins rc:$fj, rc:$fk, CFR:$ca), opstr,
                 "$fd, $fj, $fk, $ca">;
 
 class FP_BRANCH<bits<8> opcode, string opstr>
     : FPFmtBR<opcode, (outs), (ins CFR:$cj, simm21_lsl2:$imm21), opstr,
               "$cj, $imm21"> {
   let isBranch = 1;
   let isTerminator = 1;
 }
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
-let mayLoad = 1 in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 class FP_LOAD_3R<bits<17> op, string opstr, RegisterClass rc>
     : FPFmtMEM<op, (outs rc:$fd), (ins GPR:$rj, GPR:$rk), opstr,
                "$fd, $rj, $rk">;
 class FP_LOAD_2RI12<bits<10> op, string opstr, RegisterClass rc>
     : FPFmt2RI12<op, (outs rc:$fd), (ins GPR:$rj, simm12:$imm12), opstr,
                  "$fd, $rj, $imm12">;
-} // mayLoad = 1
+} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
 
-let mayStore = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 class FP_STORE_3R<bits<17> op, string opstr, RegisterClass rc>
     : FPFmtMEM<op, (outs), (ins rc:$fd, GPR:$rj, GPR:$rk), opstr,
                "$fd, $rj, $rk">;
 class FP_STORE_2RI12<bits<10> op, string opstr, RegisterClass rc>
     : FPFmt2RI12<op, (outs), (ins rc:$fd, GPR:$rj, simm12:$imm12), opstr,
                  "$fd, $rj, $imm12">;
-} // mayStore = 1
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
 
 def FPCMP_OPC_S : FPCMPOpc<0b000011000001>;
 def FPCMP_OPC_D : FPCMPOpc<0b000011000010>;
 
 def FPCMP_COND_CAF  : FPCMPCond<0x0>;
 def FPCMP_COND_CUN  : FPCMPCond<0x8>;
 def FPCMP_COND_CEQ  : FPCMPCond<0x4>;
 def FPCMP_COND_CUEQ : FPCMPCond<0xC>;

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 include "LoongArchFloatInstrFormats.td"
 include "LoongArchLSXInstrFormats.td"
 include "LoongArchLASXInstrFormats.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class ALU_3R<bits<17> op, string opstr>
     : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
 class ALU_2R<bits<22> op, string opstr>
     : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), opstr, "$rd, $rj">;
 
 class ALU_3RI2<bits<15> op, string opstr, Operand ImmOpnd>
     : Fmt3RI2<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm2), opstr,
               "$rd, $rj, $rk, $imm2">;

 class ALU_2RI12<bits<10> op, string opstr, Operand ImmOpnd>
     : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm12), opstr,
                "$rd, $rj, $imm12">;
 class ALU_2RI16<bits<6> op, string opstr, Operand ImmOpnd>
     : Fmt2RI16<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm16), opstr,
                "$rd, $rj, $imm16">;
 class ALU_1RI20<bits<7> op, string opstr, Operand ImmOpnd>
     : Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20), opstr, "$rd, $imm20">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 class MISC_I15<bits<17> op, string opstr>
     : FmtI15<op, (outs), (ins uimm15:$imm15), opstr, "$imm15">;
 
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 class RDTIME_2R<bits<22> op, string opstr>
     : Fmt2R<op, (outs GPR:$rd, GPR:$rj), (ins), opstr, "$rd, $rj">;
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class BrCC_2RI16<bits<6> op, string opstr>
     : Fmt2RI16<op, (outs), (ins GPR:$rj, GPR:$rd, simm16_lsl2_br:$imm16), opstr,
                "$rj, $rd, $imm16"> {
   let isBranch = 1;
   let isTerminator = 1;
 }
 class BrCCZ_1RI21<bits<6> op, string opstr>
     : Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2:$imm21), opstr,
                "$rj, $imm21"> {
   let isBranch = 1;
   let isTerminator = 1;
 }
 class Br_I26<bits<6> op, string opstr>
     : FmtI26<op, (outs), (ins simm26_b:$imm26), opstr, "$imm26"> {
   let isBranch = 1;
   let isTerminator = 1;
 }
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
-let mayLoad = 1 in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 class LOAD_3R<bits<17> op, string opstr>
     : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
 class LOAD_2RI12<bits<10> op, string opstr>
     : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, simm12_addlike:$imm12), opstr,
                "$rd, $rj, $imm12">;
 class LOAD_2RI14<bits<8> op, string opstr>
     : Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14), opstr,
                "$rd, $rj, $imm14">;
-} // mayLoad = 1
+} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
 
-let mayStore = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 class STORE_3R<bits<17> op, string opstr>
     : Fmt3R<op, (outs), (ins GPR:$rd, GPR:$rj, GPR:$rk), opstr,
             "$rd, $rj, $rk">;
 class STORE_2RI12<bits<10> op, string opstr>
     : Fmt2RI12<op, (outs), (ins GPR:$rd, GPR:$rj, simm12_addlike:$imm12), opstr,
                "$rd, $rj, $imm12">;
 class STORE_2RI14<bits<8> op, string opstr>
     : Fmt2RI14<op, (outs), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14), opstr,
                "$rd, $rj, $imm14">;
-} // mayStore = 1
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
 
-let mayLoad = 1, mayStore = 1, Constraints = "@earlyclobber $rd" in
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1, Constraints = "@earlyclobber $rd" in
 class AM_3R<bits<17> op, string opstr>
     : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rk, GPRMemAtomic:$rj), opstr,
             "$rd, $rk, $rj">;
 
-let mayLoad = 1 in
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 class LLBase<bits<8> op, string opstr>
     : Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14), opstr,
                "$rd, $rj, $imm14">;
 
-let mayStore = 1, Constraints = "$rd = $dst" in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $dst" in
 class SCBase<bits<8> op, string opstr>
     : Fmt2RI14<op, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14),
                opstr, "$rd, $rj, $imm14">;
 
+let hasSideEffects = 1 in
 class IOCSRRD<bits<22> op, string opstr>
     : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), opstr, "$rd, $rj">;
 
+let hasSideEffects = 1 in
 class IOCSRWR<bits<22> op, string opstr>
     : Fmt2R<op, (outs), (ins GPR:$rd, GPR:$rj), opstr, "$rd, $rj">;
 
 //===----------------------------------------------------------------------===//
 // Basic Integer Instructions
 //===----------------------------------------------------------------------===//
 
 // Arithmetic Operation Instructions

 def BLT  : BrCC_2RI16<0b011000, "blt">;
 def BGE  : BrCC_2RI16<0b011001, "bge">;
 def BLTU : BrCC_2RI16<0b011010, "bltu">;
 def BGEU : BrCC_2RI16<0b011011, "bgeu">;
 def BEQZ : BrCCZ_1RI21<0b010000, "beqz">;
 def BNEZ : BrCCZ_1RI21<0b010001, "bnez">;
 def B : Br_I26<0b010100, "b">;
 
-let isCall = 1, Defs=[R1] in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1, Defs=[R1] in
 def BL : FmtI26<0b010101, (outs), (ins simm26_symbol:$imm26), "bl", "$imm26">;
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def JIRL : Fmt2RI16<0b010011, (outs GPR:$rd),
                     (ins GPR:$rj, simm16_lsl2:$imm16), "jirl",
                     "$rd, $rj, $imm16">;
 
 // Common Memory Access Instructions
 def LD_B  : LOAD_2RI12<0b0010100000, "ld.b">;
 def LD_H  : LOAD_2RI12<0b0010100001, "ld.h">;
 def LD_W  : LOAD_2RI12<0b0010100010, "ld.w">;
 def LD_BU : LOAD_2RI12<0b0010101000, "ld.bu">;
 def LD_HU : LOAD_2RI12<0b0010101001, "ld.hu">;
 def ST_B : STORE_2RI12<0b0010100100, "st.b">;
 def ST_H : STORE_2RI12<0b0010100101, "st.h">;
 def ST_W : STORE_2RI12<0b0010100110, "st.w">;
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
 def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12), "preld",
                      "$imm5, $rj, $imm12">;
 
 // Atomic Memory Access Instructions
 def LL_W : LLBase<0b00100000, "ll.w">;
 def SC_W : SCBase<0b00100001, "sc.w">;
 
 // Barrier Instructions

 // Arithmetic Operation Instructions for 64-bits
 def ADD_D : ALU_3R<0b00000000000100001, "add.d">;
 def SUB_D : ALU_3R<0b00000000000100011, "sub.d">;
 def ADDI_D : ALU_2RI12<0b0000001011, "addi.d", simm12_addlike>;
 def ADDU16I_D : ALU_2RI16<0b000100, "addu16i.d", simm16>;
 def ALSL_WU : ALU_3RI2<0b000000000000011, "alsl.wu", uimm2_plus1>;
 def ALSL_D  : ALU_3RI2<0b000000000010110, "alsl.d", uimm2_plus1>;
 let Constraints = "$rd = $dst" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def LU32I_D : Fmt1RI20<0b0001011, (outs GPR:$dst),
                        (ins GPR:$rd, simm20_lu32id:$imm20), "lu32i.d",
                        "$rd, $imm20">;
 }
 def LU52I_D : ALU_2RI12<0b0000001100, "lu52i.d", simm12_lu52id>;
 def PCADDU18I : ALU_1RI20<0b0001111, "pcaddu18i", simm20>;
 def MUL_D     : ALU_3R<0b00000000000111011, "mul.d">;
 def MULH_D    : ALU_3R<0b00000000000111100, "mulh.d">;
 def MULH_DU   : ALU_3R<0b00000000000111101, "mulh.du">;
 def MULW_D_W  : ALU_3R<0b00000000000111110, "mulw.d.w">;
 def MULW_D_WU : ALU_3R<0b00000000000111111, "mulw.d.wu">;
 let usesCustomInserter = true in {
 def DIV_D     : ALU_3R<0b00000000001000100, "div.d">;
 def MOD_D     : ALU_3R<0b00000000001000101, "mod.d">;
 def DIV_DU    : ALU_3R<0b00000000001000110, "div.du">;
 def MOD_DU    : ALU_3R<0b00000000001000111, "mod.du">;
 } // usesCustomInserter = true
 
 // Bit-shift Instructions for 64-bits

 def STX_B : STORE_3R<0b00111000000100000, "stx.b">;
 def STX_H : STORE_3R<0b00111000000101000, "stx.h">;
 def STX_W : STORE_3R<0b00111000000110000, "stx.w">;
 def STX_D : STORE_3R<0b00111000000111000, "stx.d">;
 def LDPTR_W : LOAD_2RI14<0b00100100, "ldptr.w">;
 def LDPTR_D : LOAD_2RI14<0b00100110, "ldptr.d">;
 def STPTR_W : STORE_2RI14<0b00100101, "stptr.w">;
 def STPTR_D : STORE_2RI14<0b00100111, "stptr.d">;
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
 def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk), "preldx",
                        "$imm5, $rj, $rk">;
 
 // Bound Check Memory Access Instructions
 def LDGT_B : LOAD_3R<0b00111000011110000, "ldgt.b">;
 def LDGT_H : LOAD_3R<0b00111000011110001, "ldgt.h">;
 def LDGT_W : LOAD_3R<0b00111000011110010, "ldgt.w">;
 def LDGT_D : LOAD_3R<0b00111000011110011, "ldgt.d">;

 def : Pat<(loongarch_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>;
 def : Pat<(loongarch_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
 let isCall = 1, Defs = [R1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rj),
                                 [(loongarch_call GPR:$rj)]>,
                          PseudoInstExpansion<(JIRL R1, GPR:$rj, 0)>;
 
-let isCall = 1, Defs = [R1] in
+let isCall = 1, hasSideEffects = 0, mayStore = 0, mayLoad = 0, Defs = [R1] in
 def PseudoJIRL_CALL : Pseudo<(outs), (ins GPR:$rj, simm16_lsl2:$imm16)>,
                       PseudoInstExpansion<(JIRL R1, GPR:$rj,
                                            simm16_lsl2:$imm16)>;
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in
 def PseudoRET : Pseudo<(outs), (ins), [(loongarch_ret)]>,
                 PseudoInstExpansion<(JIRL R0, R1, 0)>;
 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [R3] in
 def PseudoTAIL : Pseudo<(outs), (ins simm26_symbol:$dst)>;
 
 def : Pat<(loongarch_tail (iPTR tglobaladdr:$dst)),
           (PseudoTAIL tglobaladdr:$dst)>;
 def : Pat<(loongarch_tail (iPTR texternalsym:$dst)),
           (PseudoTAIL texternalsym:$dst)>;
 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [R3] in
 def PseudoTAILIndirect : Pseudo<(outs), (ins GPRT:$rj),
                                 [(loongarch_tail GPRT:$rj)]>,
                          PseudoInstExpansion<(JIRL R0, GPR:$rj, 0)>;
 
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [R3] in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
+    hasSideEffects = 0, mayStore = 0, mayLoad = 0, Uses = [R3] in
 def PseudoB_TAIL : Pseudo<(outs), (ins simm26_b:$imm26)>,
                    PseudoInstExpansion<(B simm26_b:$imm26)>;
 
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [R3] in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
+    hasSideEffects = 0, mayStore = 0, mayLoad = 0, Uses = [R3] in
 def PseudoJIRL_TAIL : Pseudo<(outs), (ins GPR:$rj, simm16_lsl2:$imm16)>,
                       PseudoInstExpansion<(JIRL R0, GPR:$rj,
                                            simm16_lsl2:$imm16)>;
 
 /// Load address (la*) macro instructions.
 
 // Define isCodeGenOnly = 0 to expose them to tablegened assembly parser.
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
def : InstAlias<"bgt $rj, $rd, $imm16",
                 (BLT GPR:$rd, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
 def : InstAlias<"bgtu $rj, $rd, $imm16",
                 (BLTU GPR:$rd, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
 def : InstAlias<"ble $rj, $rd, $imm16",
                 (BGE GPR:$rd, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
 def : InstAlias<"bleu $rj, $rd, $imm16",
                 (BGEU GPR:$rd, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
 def : InstAlias<"bltz $rd, $imm16",
                 (BLT GPR:$rd, R0, simm16_lsl2_br:$imm16), 0>;
 def : InstAlias<"bgtz $rj, $imm16",
                 (BLT R0, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
 def : InstAlias<"blez $rj, $imm16",
                 (BGE R0, GPR:$rj, simm16_lsl2_br:$imm16), 0>;
 def : InstAlias<"bgez $rd, $imm16",
                 (BGE GPR:$rd, R0, simm16_lsl2_br:$imm16), 0>;
 
 // Load immediate.
def RDFCSR : Pseudo<(outs GPR:$rd), (ins uimm2:$fcsr),
                [(set GPR:$rd, (loongarch_movfcsr2gr uimm2:$fcsr))]>;
 }
 
 //===----------------------------------------------------------------------===//
 // Privilege Instructions
 //===----------------------------------------------------------------------===//
 
 // CSR Access Instructions
+let hasSideEffects = 1 in
 def CSRRD : FmtCSR<0b0000010000000, (outs GPR:$rd), (ins uimm14:$csr_num),
                    "csrrd", "$rd, $csr_num">;
-let Constraints = "$rd = $dst" in {
+let hasSideEffects = 1, Constraints = "$rd = $dst" in {
 def CSRWR : FmtCSR<0b0000010000001, (outs GPR:$dst),
                    (ins GPR:$rd, uimm14:$csr_num), "csrwr", "$rd, $csr_num">;
 def CSRXCHG : FmtCSRXCHG<0b00000100, (outs GPR:$dst),
                          (ins GPR:$rd, GPR:$rj, uimm14:$csr_num),
                          "csrxchg", "$rd, $rj, $csr_num">;
-} // Constraints = "$rd = $dst"
+} // hasSideEffects = 1, Constraints = "$rd = $dst"
 
 // IOCSR Access Instructions
 def IOCSRRD_B : IOCSRRD<0b0000011001001000000000, "iocsrrd.b">;
 def IOCSRRD_H : IOCSRRD<0b0000011001001000000001, "iocsrrd.h">;
 def IOCSRRD_W : IOCSRRD<0b0000011001001000000010, "iocsrrd.w">;
 def IOCSRWR_B : IOCSRWR<0b0000011001001000000100, "iocsrwr.b">;
 def IOCSRWR_H : IOCSRWR<0b0000011001001000000101, "iocsrwr.h">;
 def IOCSRWR_W : IOCSRWR<0b0000011001001000000110, "iocsrwr.w">;
 let Predicates = [IsLA64] in {
 def IOCSRRD_D : IOCSRRD<0b0000011001001000000011, "iocsrrd.d">;
 def IOCSRWR_D : IOCSRWR<0b0000011001001000000111, "iocsrwr.d">;
 } // Predicates = [IsLA64]
 
 // TLB Maintenance Instructions
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
 def TLBSRCH  : FmtI32<0b00000110010010000010100000000000, "tlbsrch">;
 def TLBRD    : FmtI32<0b00000110010010000010110000000000, "tlbrd">;
 def TLBWR    : FmtI32<0b00000110010010000011000000000000, "tlbwr">;
 def TLBFILL  : FmtI32<0b00000110010010000011010000000000, "tlbfill">;
 def TLBCLR   : FmtI32<0b00000110010010000010000000000000, "tlbclr">;
 def TLBFLUSH : FmtI32<0b00000110010010000010010000000000, "tlbflush">;
 def INVTLB : FmtINVTLB<(outs), (ins GPR:$rk, GPR:$rj, uimm5:$op), "invtlb",
                        "$op, $rj, $rk">;
+} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 
 // Software Page Walking Instructions
 def LDDIR : Fmt2RI8<0b00000110010000, (outs GPR:$rd),
                     (ins GPR:$rj, uimm8:$imm8), "lddir", "$rd, $rj, $imm8">;
 def LDPTE : FmtLDPTE<(outs), (ins GPR:$rj, uimm8:$seq), "ldpte", "$rj, $seq">;
 
 
 // Other Miscellaneous Instructions
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 def ERTN : FmtI32<0b00000110010010000011100000000000, "ertn">;
 def DBCL : MISC_I15<0b00000000001010101, "dbcl">;
 def IDLE : MISC_I15<0b00000110010010001, "idle">;
 
 //===----------------------------------------------------------------------===//
 // Privilege Intrinsics
 //===----------------------------------------------------------------------===//
 

llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 --mattr=+f,-d < %s | FileCheck %s --check-prefix=LA64F
 ; RUN: llc --mtriple=loongarch64 --mattr=+d < %s | FileCheck %s --check-prefix=LA64D
 
 ;; Add more test cases after supporting different AtomicOrdering.
 
 define float @float_fadd_acquire(ptr %p) nounwind {
 ; LA64F-LABEL: float_fadd_acquire:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    fld.s $fa0, $a0, 0
 ; LA64F-NEXT:    addi.w $a1, $zero, 1
 ; LA64F-NEXT:    movgr2fr.w $fa1, $a1
+; LA64F-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64F-NEXT:  .LBB0_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Loop Header: Depth=1
 ; LA64F-NEXT:    # Child Loop BB0_3 Depth 2
-; LA64F-NEXT:    ffint.s.w $fa2, $fa1
-; LA64F-NEXT:    fadd.s $fa2, $fa0, $fa2
+; LA64F-NEXT:    fadd.s $fa2, $fa0, $fa1
 ; LA64F-NEXT:    movfr2gr.s $a1, $fa2
 ; LA64F-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64F-NEXT:  .LBB0_3: # %atomicrmw.start
 ; LA64F-NEXT:    # Parent Loop BB0_1 Depth=1
 ; LA64F-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64F-NEXT:    ll.w $a3, $a0, 0
 ; LA64F-NEXT:    bne $a3, $a2, .LBB0_5
 ; LA64F-NEXT:  # %bb.4: # %atomicrmw.start

 ; LA64F-NEXT:  # %bb.2: # %atomicrmw.end
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: float_fadd_acquire:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    fld.s $fa0, $a0, 0
 ; LA64D-NEXT:    addi.w $a1, $zero, 1
 ; LA64D-NEXT:    movgr2fr.w $fa1, $a1
+; LA64D-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64D-NEXT:  .LBB0_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Loop Header: Depth=1
 ; LA64D-NEXT:    # Child Loop BB0_3 Depth 2
-; LA64D-NEXT:    ffint.s.w $fa2, $fa1
-; LA64D-NEXT:    fadd.s $fa2, $fa0, $fa2
+; LA64D-NEXT:    fadd.s $fa2, $fa0, $fa1
 ; LA64D-NEXT:    movfr2gr.s $a1, $fa2
 ; LA64D-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64D-NEXT:  .LBB0_3: # %atomicrmw.start
 ; LA64D-NEXT:    # Parent Loop BB0_1 Depth=1
 ; LA64D-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64D-NEXT:    ll.w $a3, $a0, 0
 ; LA64D-NEXT:    bne $a3, $a2, .LBB0_5
 ; LA64D-NEXT:  # %bb.4: # %atomicrmw.start

 }
 
 define float @float_fmin_acquire(ptr %p) nounwind {
 ; LA64F-LABEL: float_fmin_acquire:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    fld.s $fa0, $a0, 0
 ; LA64F-NEXT:    addi.w $a1, $zero, 1
 ; LA64F-NEXT:    movgr2fr.w $fa1, $a1
+; LA64F-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64F-NEXT:  .LBB2_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Loop Header: Depth=1
 ; LA64F-NEXT:    # Child Loop BB2_3 Depth 2
-; LA64F-NEXT:    ffint.s.w $fa2, $fa1
-; LA64F-NEXT:    fmax.s $fa3, $fa0, $fa0
-; LA64F-NEXT:    fmin.s $fa2, $fa3, $fa2
+; LA64F-NEXT:    fmax.s $fa2, $fa0, $fa0
+; LA64F-NEXT:    fmin.s $fa2, $fa2, $fa1
 ; LA64F-NEXT:    movfr2gr.s $a1, $fa2
 ; LA64F-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64F-NEXT:  .LBB2_3: # %atomicrmw.start
 ; LA64F-NEXT:    # Parent Loop BB2_1 Depth=1
 ; LA64F-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64F-NEXT:    ll.w $a3, $a0, 0
 ; LA64F-NEXT:    bne $a3, $a2, .LBB2_5
 ; LA64F-NEXT:  # %bb.4: # %atomicrmw.start

 ; LA64F-NEXT:  # %bb.2: # %atomicrmw.end
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: float_fmin_acquire:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    fld.s $fa0, $a0, 0
 ; LA64D-NEXT:    addi.w $a1, $zero, 1
 ; LA64D-NEXT:    movgr2fr.w $fa1, $a1
+; LA64D-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64D-NEXT:  .LBB2_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Loop Header: Depth=1
 ; LA64D-NEXT:    # Child Loop BB2_3 Depth 2
-; LA64D-NEXT:    ffint.s.w $fa2, $fa1
-; LA64D-NEXT:    fmax.s $fa3, $fa0, $fa0
-; LA64D-NEXT:    fmin.s $fa2, $fa3, $fa2
+; LA64D-NEXT:    fmax.s $fa2, $fa0, $fa0
+; LA64D-NEXT:    fmin.s $fa2, $fa2, $fa1
 ; LA64D-NEXT:    movfr2gr.s $a1, $fa2
 ; LA64D-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64D-NEXT:  .LBB2_3: # %atomicrmw.start
 ; LA64D-NEXT:    # Parent Loop BB2_1 Depth=1
 ; LA64D-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64D-NEXT:    ll.w $a3, $a0, 0
 ; LA64D-NEXT:    bne $a3, $a2, .LBB2_5
 ; LA64D-NEXT:  # %bb.4: # %atomicrmw.start

 }
 
 define float @float_fmax_acquire(ptr %p) nounwind {
 ; LA64F-LABEL: float_fmax_acquire:
 ; LA64F:       # %bb.0:
 ; LA64F-NEXT:    fld.s $fa0, $a0, 0
 ; LA64F-NEXT:    addi.w $a1, $zero, 1
 ; LA64F-NEXT:    movgr2fr.w $fa1, $a1
+; LA64F-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64F-NEXT:  .LBB3_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Loop Header: Depth=1
 ; LA64F-NEXT:    # Child Loop BB3_3 Depth 2
-; LA64F-NEXT:    ffint.s.w $fa2, $fa1
-; LA64F-NEXT:    fmax.s $fa3, $fa0, $fa0
-; LA64F-NEXT:    fmax.s $fa2, $fa3, $fa2
+; LA64F-NEXT:    fmax.s $fa2, $fa0, $fa0
+; LA64F-NEXT:    fmax.s $fa2, $fa2, $fa1
 ; LA64F-NEXT:    movfr2gr.s $a1, $fa2
 ; LA64F-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64F-NEXT:  .LBB3_3: # %atomicrmw.start
 ; LA64F-NEXT:    # Parent Loop BB3_1 Depth=1
 ; LA64F-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64F-NEXT:    ll.w $a3, $a0, 0
 ; LA64F-NEXT:    bne $a3, $a2, .LBB3_5
 ; LA64F-NEXT:  # %bb.4: # %atomicrmw.start

 ; LA64F-NEXT:  # %bb.2: # %atomicrmw.end
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: float_fmax_acquire:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    fld.s $fa0, $a0, 0
 ; LA64D-NEXT:    addi.w $a1, $zero, 1
 ; LA64D-NEXT:    movgr2fr.w $fa1, $a1
+; LA64D-NEXT:    ffint.s.w $fa1, $fa1
 ; LA64D-NEXT:  .LBB3_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Loop Header: Depth=1
 ; LA64D-NEXT:    # Child Loop BB3_3 Depth 2
-; LA64D-NEXT:    ffint.s.w $fa2, $fa1
-; LA64D-NEXT:    fmax.s $fa3, $fa0, $fa0
-; LA64D-NEXT:    fmax.s $fa2, $fa3, $fa2
+; LA64D-NEXT:    fmax.s $fa2, $fa0, $fa0
+; LA64D-NEXT:    fmax.s $fa2, $fa2, $fa1
 ; LA64D-NEXT:    movfr2gr.s $a1, $fa2
 ; LA64D-NEXT:    movfr2gr.s $a2, $fa0
 ; LA64D-NEXT:  .LBB3_3: # %atomicrmw.start
 ; LA64D-NEXT:    # Parent Loop BB3_1 Depth=1
 ; LA64D-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64D-NEXT:    ll.w $a3, $a0, 0
 ; LA64D-NEXT:    bne $a3, $a2, .LBB3_5
 ; LA64D-NEXT:  # %bb.4: # %atomicrmw.start

 ; LA64D-NEXT:    ret
   %v = atomicrmw fmax ptr %p, float 1.0 acquire, align 4
   ret float %v
 }
 
 define double @double_fadd_acquire(ptr %p) nounwind {
 ; LA64F-LABEL: double_fadd_acquire:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    addi.d $sp, $sp, -64
-; LA64F-NEXT:    st.d $ra, $sp, 56 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $fp, $sp, 48 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s0, $sp, 40 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s1, $sp, 32 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s2, $sp, 24 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s3, $sp, 16 # 8-byte Folded Spill
+; LA64F-NEXT:    addi.d $sp, $sp, -80
+; LA64F-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s4, $sp, 24 # 8-byte Folded Spill
 ; LA64F-NEXT:    move $fp, $a0
 ; LA64F-NEXT:    ld.d $a0, $a0, 0
-; LA64F-NEXT:    ori $s0, $zero, 8
-; LA64F-NEXT:    addi.d $s1, $sp, 8
-; LA64F-NEXT:    addi.d $s2, $sp, 0
-; LA64F-NEXT:    ori $s3, $zero, 2
+; LA64F-NEXT:    lu52i.d $s0, $zero, 1023
+; LA64F-NEXT:    ori $s1, $zero, 8
+; LA64F-NEXT:    addi.d $s2, $sp, 16
+; LA64F-NEXT:    addi.d $s3, $sp, 8
+; LA64F-NEXT:    ori $s4, $zero, 2
 ; LA64F-NEXT:  .LBB4_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Inner Loop Header: Depth=1
-; LA64F-NEXT:    st.d $a0, $sp, 8
-; LA64F-NEXT:    lu52i.d $a1, $zero, 1023
+; LA64F-NEXT:    st.d $a0, $sp, 16
+; LA64F-NEXT:    move $a1, $s0
 ; LA64F-NEXT:    bl %plt(__adddf3)
-; LA64F-NEXT:    st.d $a0, $sp, 0
-; LA64F-NEXT:    move $a0, $s0
+; LA64F-NEXT:    st.d $a0, $sp, 8
+; LA64F-NEXT:    move $a0, $s1
 ; LA64F-NEXT:    move $a1, $fp
-; LA64F-NEXT:    move $a2, $s1
-; LA64F-NEXT:    move $a3, $s2
-; LA64F-NEXT:    move $a4, $s3
-; LA64F-NEXT:    move $a5, $s3
+; LA64F-NEXT:    move $a2, $s2
+; LA64F-NEXT:    move $a3, $s3
+; LA64F-NEXT:    move $a4, $s4
+; LA64F-NEXT:    move $a5, $s4
 ; LA64F-NEXT:    bl %plt(__atomic_compare_exchange)
 ; LA64F-NEXT:    move $a1, $a0
-; LA64F-NEXT:    ld.d $a0, $sp, 8
+; LA64F-NEXT:    ld.d $a0, $sp, 16
 ; LA64F-NEXT:    beqz $a1, .LBB4_1
 ; LA64F-NEXT:  # %bb.2: # %atomicrmw.end
-; LA64F-NEXT:    ld.d $s3, $sp, 16 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s2, $sp, 24 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s1, $sp, 32 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s0, $sp, 40 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $fp, $sp, 48 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $ra, $sp, 56 # 8-byte Folded Reload
-; LA64F-NEXT:    addi.d $sp, $sp, 64
+; LA64F-NEXT:    ld.d $s4, $sp, 24 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s3, $sp, 32 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s2, $sp, 40 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s1, $sp, 48 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s0, $sp, 56 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $fp, $sp, 64 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $ra, $sp, 72 # 8-byte Folded Reload
+; LA64F-NEXT:    addi.d $sp, $sp, 80
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: double_fadd_acquire:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    addi.d $sp, $sp, -80
 ; LA64D-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
 ; LA64D-NEXT:    fst.d $fs0, $sp, 24 # 8-byte Folded Spill
 ; LA64D-NEXT:    move $fp, $a0
 ; LA64D-NEXT:    fld.d $fa0, $a0, 0
 ; LA64D-NEXT:    addi.d $a0, $zero, 1
-; LA64D-NEXT:    movgr2fr.d $fs0, $a0
+; LA64D-NEXT:    movgr2fr.d $fa1, $a0
+; LA64D-NEXT:    ffint.d.l $fs0, $fa1
 ; LA64D-NEXT:    ori $s0, $zero, 8
 ; LA64D-NEXT:    addi.d $s1, $sp, 16
 ; LA64D-NEXT:    addi.d $s2, $sp, 8
 ; LA64D-NEXT:    ori $s3, $zero, 2
 ; LA64D-NEXT:  .LBB4_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Inner Loop Header: Depth=1
 ; LA64D-NEXT:    fst.d $fa0, $sp, 16
-; LA64D-NEXT:    ffint.d.l $fa1, $fs0
-; LA64D-NEXT:    fadd.d $fa0, $fa0, $fa1
+; LA64D-NEXT:    fadd.d $fa0, $fa0, $fs0
 ; LA64D-NEXT:    fst.d $fa0, $sp, 8
 ; LA64D-NEXT:    move $a0, $s0
 ; LA64D-NEXT:    move $a1, $fp
 ; LA64D-NEXT:    move $a2, $s1
 ; LA64D-NEXT:    move $a3, $s2
 ; LA64D-NEXT:    move $a4, $s3
 ; LA64D-NEXT:    move $a5, $s3
 ; LA64D-NEXT:    bl %plt(__atomic_compare_exchange)

 ; LA64D-NEXT:    ret
   %v = atomicrmw fadd ptr %p, double 1.0 acquire, align 4
   ret double %v
 }
 
 define double @double_fsub_acquire(ptr %p) nounwind {
 ; LA64F-LABEL: double_fsub_acquire:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    addi.d $sp, $sp, -64
-; LA64F-NEXT:    st.d $ra, $sp, 56 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $fp, $sp, 48 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s0, $sp, 40 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s1, $sp, 32 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s2, $sp, 24 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s3, $sp, 16 # 8-byte Folded Spill
+; LA64F-NEXT:    addi.d $sp, $sp, -80
+; LA64F-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s4, $sp, 24 # 8-byte Folded Spill
 ; LA64F-NEXT:    move $fp, $a0
 ; LA64F-NEXT:    ld.d $a0, $a0, 0
-; LA64F-NEXT:    ori $s0, $zero, 8
-; LA64F-NEXT:    addi.d $s1, $sp, 8
-; LA64F-NEXT:    addi.d $s2, $sp, 0
-; LA64F-NEXT:    ori $s3, $zero, 2
+; LA64F-NEXT:    lu52i.d $s0, $zero, -1025
+; LA64F-NEXT:    ori $s1, $zero, 8
+; LA64F-NEXT:    addi.d $s2, $sp, 16
+; LA64F-NEXT:    addi.d $s3, $sp, 8
+; LA64F-NEXT:    ori $s4, $zero, 2
 ; LA64F-NEXT:  .LBB5_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Inner Loop Header: Depth=1
-; LA64F-NEXT:    st.d $a0, $sp, 8
-; LA64F-NEXT:    lu52i.d $a1, $zero, -1025
+; LA64F-NEXT:    st.d $a0, $sp, 16
+; LA64F-NEXT:    move $a1, $s0
 ; LA64F-NEXT:    bl %plt(__adddf3)
-; LA64F-NEXT:    st.d $a0, $sp, 0
-; LA64F-NEXT:    move $a0, $s0
+; LA64F-NEXT:    st.d $a0, $sp, 8
+; LA64F-NEXT:    move $a0, $s1
 ; LA64F-NEXT:    move $a1, $fp
-; LA64F-NEXT:    move $a2, $s1
-; LA64F-NEXT:    move $a3, $s2
-; LA64F-NEXT:    move $a4, $s3
-; LA64F-NEXT:    move $a5, $s3
+; LA64F-NEXT:    move $a2, $s2
+; LA64F-NEXT:    move $a3, $s3
+; LA64F-NEXT:    move $a4, $s4
+; LA64F-NEXT:    move $a5, $s4
 ; LA64F-NEXT:    bl %plt(__atomic_compare_exchange)
 ; LA64F-NEXT:    move $a1, $a0
-; LA64F-NEXT:    ld.d $a0, $sp, 8
+; LA64F-NEXT:    ld.d $a0, $sp, 16
 ; LA64F-NEXT:    beqz $a1, .LBB5_1
 ; LA64F-NEXT:  # %bb.2: # %atomicrmw.end
-; LA64F-NEXT:    ld.d $s3, $sp, 16 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s2, $sp, 24 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s1, $sp, 32 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s0, $sp, 40 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $fp, $sp, 48 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $ra, $sp, 56 # 8-byte Folded Reload
-; LA64F-NEXT:    addi.d $sp, $sp, 64
+; LA64F-NEXT:    ld.d $s4, $sp, 24 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s3, $sp, 32 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s2, $sp, 40 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s1, $sp, 48 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s0, $sp, 56 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $fp, $sp, 64 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $ra, $sp, 72 # 8-byte Folded Reload
+; LA64F-NEXT:    addi.d $sp, $sp, 80
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: double_fsub_acquire:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    addi.d $sp, $sp, -80
 ; LA64D-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill

 ; LA64D-NEXT:    ret
   %v = atomicrmw fsub ptr %p, double 1.0 acquire, align 4
   ret double %v
 }
 
 define double @double_fmin_acquire(ptr %p) nounwind {
 ; LA64F-LABEL: double_fmin_acquire:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    addi.d $sp, $sp, -64
-; LA64F-NEXT:    st.d $ra, $sp, 56 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $fp, $sp, 48 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s0, $sp, 40 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s1, $sp, 32 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s2, $sp, 24 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s3, $sp, 16 # 8-byte Folded Spill
+; LA64F-NEXT:    addi.d $sp, $sp, -80
+; LA64F-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s4, $sp, 24 # 8-byte Folded Spill
 ; LA64F-NEXT:    move $fp, $a0
 ; LA64F-NEXT:    ld.d $a0, $a0, 0
-; LA64F-NEXT:    ori $s0, $zero, 8
-; LA64F-NEXT:    addi.d $s1, $sp, 8
-; LA64F-NEXT:    addi.d $s2, $sp, 0
-; LA64F-NEXT:    ori $s3, $zero, 2
+; LA64F-NEXT:    lu52i.d $s0, $zero, 1023
+; LA64F-NEXT:    ori $s1, $zero, 8
+; LA64F-NEXT:    addi.d $s2, $sp, 16
+; LA64F-NEXT:    addi.d $s3, $sp, 8
+; LA64F-NEXT:    ori $s4, $zero, 2
 ; LA64F-NEXT:  .LBB6_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Inner Loop Header: Depth=1
-; LA64F-NEXT:    st.d $a0, $sp, 8
-; LA64F-NEXT:    lu52i.d $a1, $zero, 1023
+; LA64F-NEXT:    st.d $a0, $sp, 16
+; LA64F-NEXT:    move $a1, $s0
 ; LA64F-NEXT:    bl %plt(fmin)
-; LA64F-NEXT:    st.d $a0, $sp, 0
-; LA64F-NEXT:    move $a0, $s0
+; LA64F-NEXT:    st.d $a0, $sp, 8
+; LA64F-NEXT:    move $a0, $s1
 ; LA64F-NEXT:    move $a1, $fp
-; LA64F-NEXT:    move $a2, $s1
-; LA64F-NEXT:    move $a3, $s2
-; LA64F-NEXT:    move $a4, $s3
-; LA64F-NEXT:    move $a5, $s3
+; LA64F-NEXT:    move $a2, $s2
+; LA64F-NEXT:    move $a3, $s3
+; LA64F-NEXT:    move $a4, $s4
+; LA64F-NEXT:    move $a5, $s4
 ; LA64F-NEXT:    bl %plt(__atomic_compare_exchange)
 ; LA64F-NEXT:    move $a1, $a0
-; LA64F-NEXT:    ld.d $a0, $sp, 8
+; LA64F-NEXT:    ld.d $a0, $sp, 16
 ; LA64F-NEXT:    beqz $a1, .LBB6_1
 ; LA64F-NEXT:  # %bb.2: # %atomicrmw.end
-; LA64F-NEXT:    ld.d $s3, $sp, 16 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s2, $sp, 24 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s1, $sp, 32 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s0, $sp, 40 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $fp, $sp, 48 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $ra, $sp, 56 # 8-byte Folded Reload
-; LA64F-NEXT:    addi.d $sp, $sp, 64
+; LA64F-NEXT:    ld.d $s4, $sp, 24 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s3, $sp, 32 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s2, $sp, 40 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s1, $sp, 48 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s0, $sp, 56 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $fp, $sp, 64 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $ra, $sp, 72 # 8-byte Folded Reload
+; LA64F-NEXT:    addi.d $sp, $sp, 80
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: double_fmin_acquire:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    addi.d $sp, $sp, -80
 ; LA64D-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
 ; LA64D-NEXT:    fst.d $fs0, $sp, 24 # 8-byte Folded Spill
 ; LA64D-NEXT:    move $fp, $a0
 ; LA64D-NEXT:    fld.d $fa0, $a0, 0
 ; LA64D-NEXT:    addi.d $a0, $zero, 1
-; LA64D-NEXT:    movgr2fr.d $fs0, $a0
+; LA64D-NEXT:    movgr2fr.d $fa1, $a0
+; LA64D-NEXT:    ffint.d.l $fs0, $fa1
 ; LA64D-NEXT:    ori $s0, $zero, 8
 ; LA64D-NEXT:    addi.d $s1, $sp, 16
 ; LA64D-NEXT:    addi.d $s2, $sp, 8
 ; LA64D-NEXT:    ori $s3, $zero, 2
 ; LA64D-NEXT:  .LBB6_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Inner Loop Header: Depth=1
 ; LA64D-NEXT:    fst.d $fa0, $sp, 16
 ; LA64D-NEXT:    fmax.d $fa0, $fa0, $fa0
-; LA64D-NEXT:    ffint.d.l $fa1, $fs0
-; LA64D-NEXT:    fmin.d $fa0, $fa0, $fa1
+; LA64D-NEXT:    fmin.d $fa0, $fa0, $fs0
 ; LA64D-NEXT:    fst.d $fa0, $sp, 8
 ; LA64D-NEXT:    move $a0, $s0
 ; LA64D-NEXT:    move $a1, $fp
 ; LA64D-NEXT:    move $a2, $s1
 ; LA64D-NEXT:    move $a3, $s2
 ; LA64D-NEXT:    move $a4, $s3
 ; LA64D-NEXT:    move $a5, $s3
 ; LA64D-NEXT:    bl %plt(__atomic_compare_exchange)

 ; LA64D-NEXT:    ret
   %v = atomicrmw fmin ptr %p, double 1.0 acquire, align 4
   ret double %v
 }
 
 define double @double_fmax_acquire(ptr %p) nounwind {
 ; LA64F-LABEL: double_fmax_acquire:
 ; LA64F:       # %bb.0:
-; LA64F-NEXT:    addi.d $sp, $sp, -64
-; LA64F-NEXT:    st.d $ra, $sp, 56 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $fp, $sp, 48 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s0, $sp, 40 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s1, $sp, 32 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s2, $sp, 24 # 8-byte Folded Spill
-; LA64F-NEXT:    st.d $s3, $sp, 16 # 8-byte Folded Spill
+; LA64F-NEXT:    addi.d $sp, $sp, -80
+; LA64F-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
+; LA64F-NEXT:    st.d $s4, $sp, 24 # 8-byte Folded Spill
 ; LA64F-NEXT:    move $fp, $a0
 ; LA64F-NEXT:    ld.d $a0, $a0, 0
-; LA64F-NEXT:    ori $s0, $zero, 8
-; LA64F-NEXT:    addi.d $s1, $sp, 8
-; LA64F-NEXT:    addi.d $s2, $sp, 0
-; LA64F-NEXT:    ori $s3, $zero, 2
+; LA64F-NEXT:    lu52i.d $s0, $zero, 1023
+; LA64F-NEXT:    ori $s1, $zero, 8
+; LA64F-NEXT:    addi.d $s2, $sp, 16
+; LA64F-NEXT:    addi.d $s3, $sp, 8
+; LA64F-NEXT:    ori $s4, $zero, 2
 ; LA64F-NEXT:  .LBB7_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Inner Loop Header: Depth=1
-; LA64F-NEXT:    st.d $a0, $sp, 8
-; LA64F-NEXT:    lu52i.d $a1, $zero, 1023
+; LA64F-NEXT:    st.d $a0, $sp, 16
+; LA64F-NEXT:    move $a1, $s0
 ; LA64F-NEXT:    bl %plt(fmax)
-; LA64F-NEXT:    st.d $a0, $sp, 0
-; LA64F-NEXT:    move $a0, $s0
+; LA64F-NEXT:    st.d $a0, $sp, 8
+; LA64F-NEXT:    move $a0, $s1
 ; LA64F-NEXT:    move $a1, $fp
-; LA64F-NEXT:    move $a2, $s1
-; LA64F-NEXT:    move $a3, $s2
-; LA64F-NEXT:    move $a4, $s3
-; LA64F-NEXT:    move $a5, $s3
+; LA64F-NEXT:    move $a2, $s2
+; LA64F-NEXT:    move $a3, $s3
+; LA64F-NEXT:    move $a4, $s4
+; LA64F-NEXT:    move $a5, $s4
 ; LA64F-NEXT:    bl %plt(__atomic_compare_exchange)
 ; LA64F-NEXT:    move $a1, $a0
-; LA64F-NEXT:    ld.d $a0, $sp, 8
+; LA64F-NEXT:    ld.d $a0, $sp, 16
 ; LA64F-NEXT:    beqz $a1, .LBB7_1
 ; LA64F-NEXT:  # %bb.2: # %atomicrmw.end
-; LA64F-NEXT:    ld.d $s3, $sp, 16 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s2, $sp, 24 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s1, $sp, 32 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $s0, $sp, 40 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $fp, $sp, 48 # 8-byte Folded Reload
-; LA64F-NEXT:    ld.d $ra, $sp, 56 # 8-byte Folded Reload
-; LA64F-NEXT:    addi.d $sp, $sp, 64
+; LA64F-NEXT:    ld.d $s4, $sp, 24 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s3, $sp, 32 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s2, $sp, 40 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s1, $sp, 48 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $s0, $sp, 56 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $fp, $sp, 64 # 8-byte Folded Reload
+; LA64F-NEXT:    ld.d $ra, $sp, 72 # 8-byte Folded Reload
+; LA64F-NEXT:    addi.d $sp, $sp, 80
 ; LA64F-NEXT:    ret
 ;
 ; LA64D-LABEL: double_fmax_acquire:
 ; LA64D:       # %bb.0:
 ; LA64D-NEXT:    addi.d $sp, $sp, -80
 ; LA64D-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
 ; LA64D-NEXT:    fst.d $fs0, $sp, 24 # 8-byte Folded Spill
 ; LA64D-NEXT:    move $fp, $a0
 ; LA64D-NEXT:    fld.d $fa0, $a0, 0
 ; LA64D-NEXT:    addi.d $a0, $zero, 1
-; LA64D-NEXT:    movgr2fr.d $fs0, $a0
+; LA64D-NEXT:    movgr2fr.d $fa1, $a0
+; LA64D-NEXT:    ffint.d.l $fs0, $fa1
 ; LA64D-NEXT:    ori $s0, $zero, 8
 ; LA64D-NEXT:    addi.d $s1, $sp, 16
 ; LA64D-NEXT:    addi.d $s2, $sp, 8
 ; LA64D-NEXT:    ori $s3, $zero, 2
 ; LA64D-NEXT:  .LBB7_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Inner Loop Header: Depth=1
 ; LA64D-NEXT:    fst.d $fa0, $sp, 16
 ; LA64D-NEXT:    fmax.d $fa0, $fa0, $fa0
-; LA64D-NEXT:    ffint.d.l $fa1, $fs0
-; LA64D-NEXT:    fmax.d $fa0, $fa0, $fa1
+; LA64D-NEXT:    fmax.d $fa0, $fa0, $fs0
 ; LA64D-NEXT:    fst.d $fa0, $sp, 8
 ; LA64D-NEXT:    move $a0, $s0
 ; LA64D-NEXT:    move $a1, $fp
 ; LA64D-NEXT:    move $a2, $s1
 ; LA64D-NEXT:    move $a3, $s2
 ; LA64D-NEXT:    move $a4, $s3
 ; LA64D-NEXT:    move $a5, $s3
 ; LA64D-NEXT:    bl %plt(__atomic_compare_exchange)

llvm/test/CodeGen/LoongArch/ir-instruction/fcmp-dbl.ll

 ; LA32-NEXT:    movgr2fr.w $fa1, $zero
 ; LA32-NEXT:    movgr2frh.w $fa1, $zero
 ; LA32-NEXT:    fcmp.cle.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    movcf2gr $a1, $fcc0
 ; LA32-NEXT:    bnez $a1, .LBB16_2
 ; LA32-NEXT:  # %bb.1: # %if.then
 ; LA32-NEXT:    ret
 ; LA32-NEXT:  .LBB16_2: # %if.else
-; LA32-NEXT:    movgr2fr.w $fa1, $zero
-; LA32-NEXT:    movgr2frh.w $fa1, $zero
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_fast_olt:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa1, $zero
 ; LA64-NEXT:    fcmp.cle.d $fcc0, $fa1, $fa0

 ; LA32-NEXT:    movgr2frh.w $fa1, $zero
 ; LA32-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a1, $fcc0
 ; LA32-NEXT:    xori $a1, $a1, 1
 ; LA32-NEXT:    bnez $a1, .LBB17_2
 ; LA32-NEXT:  # %bb.1: # %if.then
 ; LA32-NEXT:    ret
 ; LA32-NEXT:  .LBB17_2: # %if.else
-; LA32-NEXT:    movgr2fr.w $fa1, $zero
-; LA32-NEXT:    movgr2frh.w $fa1, $zero
-; LA32-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_fast_oeq:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa1, $zero
 ; LA64-NEXT:    fcmp.ceq.d $fcc0, $fa0, $fa1
 ; LA64-NEXT:    movcf2gr $a1, $fcc0

 ; LA32:       # %bb.0:
 ; LA32-NEXT:    movgr2fr.w $fa1, $zero
 ; LA32-NEXT:    movgr2frh.w $fa1, $zero
 ; LA32-NEXT:    fcmp.clt.d $fcc0, $fa1, $fa0
 ; LA32-NEXT:    bcnez $fcc0, .LBB18_2
 ; LA32-NEXT:  # %bb.1: # %if.then
 ; LA32-NEXT:    ret
 ; LA32-NEXT:  .LBB18_2: # %if.else
-; LA32-NEXT:    movgr2fr.w $fa1, $zero
-; LA32-NEXT:    movgr2frh.w $fa1, $zero
 ; LA32-NEXT:    fcmp.cle.d $fcc0, $fa0, $fa1
 ; LA32-NEXT:    movcf2gr $a0, $fcc0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: fcmp_fast_ole:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    movgr2fr.d $fa1, $zero
 ; LA64-NEXT:    fcmp.clt.d $fcc0, $fa1, $fa0