[CSKY] Optimize ANDI/ORI to BCLRI/BSETI for specific immediates

[benshi001]

llvm/test/CodeGen/CSKY/bseti_bclri.ll

54

This case will be optimized to (BSETI (BSETI x, 16), 2) in the future.

109

This case will be optimized to (BCLRI (BCLRI x, 16), 2) in the future.

[benshi001]

llvm/test/CodeGen/CSKY/bseti_bclri.ll

7

This case is not optimized to BSETI due to the immediate can be directly encoded in to ORI32.

25

This case is not optimized to BSETI due to the immediate can be directly encoded in to ORI32.

64

This case can not be optimized to BCLRI due to the immediate can be directly encoded into ANDNI.

82

This case can not be optimized to BCLRI due to the immediate can be directly encoded into ANDNI.

99

This case can not be optimized to BCLRI due to the immediate has more the more than one zero-bit.

[benshi001]

ping ...

llvm/lib/Target/CSKY/CSKYInstrInfo.td

 }
 
 def uimm_shift : Operand<i32>, ImmLeaf<i32, "return isUInt<2>(Imm);"> {
   let EncoderMethod = "getImmShiftOpValue";
   let ParserMatchClass = UImmAsmOperand<2>;
   let DecoderMethod = "decodeImmShiftOpValue";
 }
 
+// Optimize (or x, imm) to (BSETI x, log2(imm)). We should exclude the
+// case can be opimized to (ORI32/ORI16 x, imm).
+def imm32_1_pop_bit_XFORM : SDNodeXForm<imm, [{
+  uint32_t I = N->getZExtValue();
+  return CurDAG->getTargetConstant(llvm::Log2_32(I), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+def imm32_1_pop_bit : PatLeaf<(imm), [{
+  uint32_t I = N->getZExtValue();
+  return llvm::popcount(I) == 1 && I > 0xffff;
+}]>;
+
+// Optimize (and x, imm) to (BCLRI x, log2(~imm)). We should exclude the
+// case can be opimized to (ANDNI x, ~imm).
+def imm32_1_zero_bit_XFORM : SDNodeXForm<imm, [{
+  uint32_t I = ~N->getZExtValue();
+  return CurDAG->getTargetConstant(llvm::Log2_32(I), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+def imm32_1_zero_bit : PatLeaf<(imm), [{
+  uint32_t I = ~N->getZExtValue();
+  return llvm::popcount(I) == 1 && I > 0xfff;
+}]>;
+
 def CSKYSymbol : AsmOperandClass {
   let Name = "CSKYSymbol";
   let RenderMethod = "addImmOperands";
   let DiagnosticType = "InvalidCSKYSymbol";
   let ParserMethod = "parseCSKYSymbol";
 }
 
 def br_symbol : Operand<OtherVT> {
def : Pat<(select CARRY:$ca, GPR:$other, (i32 0)),
           (CLRF32 CARRY:$ca, GPR:$other)>;
 }
 
 // Constant materialize patterns.
 let Predicates = [iHasE2] in
   def : Pat<(i32 imm:$imm),
             (ORI32 (MOVIH32 (uimm32_hi16 imm:$imm)), (uimm32_lo16 imm:$imm))>;
 
+// Bit operations.
+let Predicates = [iHasE2] in {
+  def : Pat<(or GPR:$rs, imm32_1_pop_bit:$imm),
+            (BSETI32 GPR:$rs, (imm32_1_pop_bit_XFORM imm32_1_pop_bit:$imm))>;
+  def : Pat<(and GPR:$rs, imm32_1_zero_bit:$imm),
+            (BCLRI32 GPR:$rs, (imm32_1_zero_bit_XFORM imm32_1_zero_bit:$imm))>;
+}
+
 // Other operations.
 let Predicates = [iHasE2] in {
   def : Pat<(rotl GPR:$rs1, GPR:$rs2),
             (ROTL32 GPR:$rs1, (ANDI32 GPR:$rs2, 0x1f))>;
   let Predicates = [iHas2E3] in {
     def : Pat<(bitreverse GPR:$rx), (BREV32 GPR:$rx)>;
     def : Pat<(bswap GPR:$rx), (REVB32 GPR:$rx)>;
   }

llvm/test/CodeGen/CSKY/bseti_bclri.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 < %s -mtriple=csky | FileCheck %s
 
 define i32 @test_or_128(i32 noundef %0) {
 ; CHECK-LABEL: test_or_128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori32 a0, a0, 128
 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 128
  ret i32 %2
 }
 
 define i32 @test_or_131072(i32 noundef %0) {
 ; CHECK-LABEL: test_or_131072:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 2
-; CHECK-NEXT:    or16 a0, a1
+; CHECK-NEXT:    bseti16 a0, 17
 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 131072
  ret i32 %2
 }
 
 define i32 @test_or_192(i32 noundef %0) {
 ; CHECK-LABEL: test_or_192:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori32 a0, a0, 192
 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 192
  ret i32 %2
 }
 
 define i32 @test_or_3072(i32 noundef %0) {
 ; CHECK-LABEL: test_or_3072:
 ; CHECK:       # %bb.0:

  %2 = or i32 %0, 196608
  ret i32 %2
 }
 
 define i32 @test_or_65540(i32 noundef %0) {
 ; CHECK-LABEL: test_or_65540:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movih32 a1, 1
 ; CHECK-NEXT:    ori32 a1, a1, 4
 ; CHECK-NEXT:    or16 a0, a1
 ; CHECK-NEXT:    rts16
  %2 = or i32 %0, 65540
  ret i32 %2
 }
 
 define i32 @test_andnot_128(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andni32 a0, a0, 128
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -129
  ret i32 %2
 }
 
 define i32 @test_andnot_131072(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_131072:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movih32 a1, 65533
-; CHECK-NEXT:    ori32 a1, a1, 65535
-; CHECK-NEXT:    and16 a0, a1
+; CHECK-NEXT:    bclri16 a0, 17
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -131073
  ret i32 %2
 }
 
 define i32 @test_andnot_192(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_192:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andni32 a0, a0, 192
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -193
  ret i32 %2
 }
 
 define i32 @test_andnot_3072(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_3072:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andni32 a0, a0, 3072
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -3073
  ret i32 %2
 }
 
 define i32 @test_andnot_1966608(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_1966608:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movih32 a1, 65505
 ; CHECK-NEXT:    ori32 a1, a1, 65007
 ; CHECK-NEXT:    and16 a0, a1
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -1966609
  ret i32 %2
 }
 
 define i32 @test_andnot_65540(i32 noundef %0) {
 ; CHECK-LABEL: test_andnot_65540:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movih32 a1, 65534
 ; CHECK-NEXT:    ori32 a1, a1, 65531
 ; CHECK-NEXT:    and16 a0, a1
 ; CHECK-NEXT:    rts16
  %2 = and i32 %0, -65541
  ret i32 %2
 }