[AArch64] Remove G_VECREDUCE_FADD from selectReduction

[dmgreen]

Summary

I believe that for fp reductions we can use the imported tablegen patterns for selection, as opposed to going via selectReduction. Integer reductions are more difficult, as the return types in selection DAG will be promoted to i32.

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

 def : GINodeEquiv<G_FMAXNUM_IEEE, fmaxnum_ieee>;
 def : GINodeEquiv<G_FMAXIMUM, fmaximum>;
 def : GINodeEquiv<G_FMINIMUM, fminimum>;
 def : GINodeEquiv<G_READCYCLECOUNTER, readcyclecounter>;
 def : GINodeEquiv<G_ROTR, rotr>;
 def : GINodeEquiv<G_ROTL, rotl>;
 def : GINodeEquiv<G_LROUND, lround>;
 def : GINodeEquiv<G_LLROUND, llround>;
+def : GINodeEquiv<G_VECREDUCE_FADD, vecreduce_fadd>;
 
 def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
 def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;
 def : GINodeEquiv<G_STRICT_FMUL, strict_fmul>;
 def : GINodeEquiv<G_STRICT_FDIV, strict_fdiv>;
 def : GINodeEquiv<G_STRICT_FREM, strict_frem>;
 def : GINodeEquiv<G_STRICT_FMA, strict_fma>;
 def : GINodeEquiv<G_STRICT_FSQRT, strict_fsqrt>;

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

#endif
   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
     return selectExtractElt(I, MRI);
   case TargetOpcode::G_INSERT_VECTOR_ELT:
     return selectInsertElt(I, MRI);
   case TargetOpcode::G_CONCAT_VECTORS:
     return selectConcatVectors(I, MRI);
   case TargetOpcode::G_JUMP_TABLE:
     return selectJumpTable(I, MRI);
-  case TargetOpcode::G_VECREDUCE_FADD:
   case TargetOpcode::G_VECREDUCE_ADD:
     return selectReduction(I, MRI);
   case TargetOpcode::G_MEMCPY:
   case TargetOpcode::G_MEMCPY_INLINE:
   case TargetOpcode::G_MEMMOVE:
   case TargetOpcode::G_MEMSET:
     assert(STI.hasMOPS() && "Shouldn't get here without +mops feature");
     return selectMOPS(I, MRI);
if (I.getOpcode() == TargetOpcode::G_VECREDUCE_ADD) {
     else {
       LLVM_DEBUG(dbgs() << "Unhandled type for add reduction");
       return false;
     }
     I.setDesc(TII.get(Opc));
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
-  if (I.getOpcode() == TargetOpcode::G_VECREDUCE_FADD) {
-    unsigned Opc = 0;
-    if (VecTy == LLT::fixed_vector(2, 32))
-      Opc = AArch64::FADDPv2i32p;
-    else if (VecTy == LLT::fixed_vector(2, 64))
-      Opc = AArch64::FADDPv2i64p;
-    else {
-      LLVM_DEBUG(dbgs() << "Unhandled type for fadd reduction");
-      return false;
-    }
-    I.setDesc(TII.get(Opc));
-    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
-  }
   return false;
 }
 
 bool AArch64InstructionSelector::selectMOPS(MachineInstr &GI,
                                             MachineRegisterInfo &MRI) {
   unsigned Mopcode;
   switch (GI.getOpcode()) {
   case TargetOpcode::G_MEMCPY:

llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-fadd.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
 ---
 name:            fadd_v2s32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $d0
 
     ; CHECK-LABEL: name: fadd_v2s32
     ; CHECK: liveins: $d0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[FADDPv2i32p:%[0-9]+]]:fpr32 = FADDPv2i32p [[COPY]]
-    ; CHECK: $w0 = COPY [[FADDPv2i32p]]
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
+    ; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nofpexcept FADDPv2i32p [[COPY]], implicit $fpcr
+    ; CHECK-NEXT: $w0 = COPY [[FADDPv2i32p]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(s32) = G_VECREDUCE_FADD %0(<2 x s32>)
     $w0 = COPY %1(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            fadd_v2s64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $q0
 
     ; CHECK-LABEL: name: fadd_v2s64
     ; CHECK: liveins: $q0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
-    ; CHECK: [[FADDPv2i64p:%[0-9]+]]:fpr64 = FADDPv2i64p [[COPY]]
-    ; CHECK: $x0 = COPY [[FADDPv2i64p]]
-    ; CHECK: RET_ReallyLR implicit $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+    ; CHECK-NEXT: [[FADDPv2i64p:%[0-9]+]]:fpr64 = nofpexcept FADDPv2i64p [[COPY]], implicit $fpcr
+    ; CHECK-NEXT: $x0 = COPY [[FADDPv2i64p]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
     %0:fpr(<2 x s64>) = COPY $q0
     %2:fpr(s64) = G_VECREDUCE_FADD %0(<2 x s64>)
     $x0 = COPY %2(s64)
     RET_ReallyLR implicit $x0
 
 ...