[m68k] Fix incorrect handling of TLS when matching addressing mode.

[0x59616e]

Summary

TargetGlobalTLSAddress is not considered and handled correctly when matching addressing mode, which leads to an incorrect result of instruction selection.

fixes #63162.

[RKSimon]

llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

747–748

drop this?

[glaubitz]

I can confirm that this patch fixes the issue for me!

[myhsu]

Overall looks good. Though please address the inline comments.

llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

504

please add curly braces around this case

[0x59616e]

address feedbacks

[myhsu]

Cool, LGTM
Thanks!

[0x59616e]

Thanks!

llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp

case ISD::FrameIndex:
     if (AM.isDispAddrType() &&
         AM.BaseType == M68kISelAddressMode::Base::RegBase &&
         AM.BaseReg.getNode() == nullptr && doesDispFitFI(AM)) {
       AM.BaseType = M68kISelAddressMode::Base::FrameIndexBase;
       AM.BaseFrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
       return true;
     }
     break;
+
+  case ISD::TargetGlobalTLSAddress: {
+    GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
+    AM.GV = GA->getGlobal();
+    AM.SymbolFlags = GA->getTargetFlags();
+    return true;
+  }
   }
 
   return matchAddressBase(N, AM);
 }
 
 /// Add the specified node to the specified addressing mode, returning true if
 /// it cannot be done. This just pattern matches for the addressing mode.
 bool M68kDAGToDAGISel::matchAddress(SDValue N, M68kISelAddressMode &AM) {
if (AM.hasIndexReg()) {
     return false;
   }
 
   if (!AM.hasBaseReg()) {
     LLVM_DEBUG(dbgs() << "REJECT: No Base reg\n");
     return false;
   }
 
+  Base = AM.BaseReg;
+
   if (getSymbolicDisplacement(AM, SDLoc(N), Disp)) {
     assert(!AM.Disp && "Should not be any displacement");
     LLVM_DEBUG(dbgs() << "SUCCESS, matched Symbol\n");
     return true;
   }
 
   // Give a chance to AddrType::ARI
   if (AM.Disp == 0) {
     LLVM_DEBUG(dbgs() << "REJECT: No displacement\n");
     return false;
   }
 
-  Base = AM.BaseReg;
   Disp = getI16Imm(AM.Disp, SDLoc(N));
 
   LLVM_DEBUG(dbgs() << "SUCCESS\n");
   return true;
 }
 
 static bool isAddressBase(const SDValue &N) {
   switch (N.getOpcode()) {
   case ISD::ADD:

llvm/test/CodeGen/M68k/TLS/tlsgd.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=m68k --relocation-model=pic -o - %s | FileCheck %s
 
 @myvar = external thread_local global i32, align 4
 
 define ptr @get_addr() nounwind {
 ; CHECK-LABEL: get_addr:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a0
-; CHECK-NEXT:    adda.l myvar@TLSGD, %a0
+; CHECK-NEXT:    lea (myvar@TLSGD,%a0), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
 ; CHECK-NEXT:    jsr (__tls_get_addr@PLT,%pc)
 ; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
   ret ptr %0
 }
 
 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsie.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=m68k -o - %s | FileCheck %s
 
 @myvar = external thread_local global i32, align 4
 
 define dso_local ptr @get_addr() nounwind {
 ; CHECK-LABEL: get_addr:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr __m68k_read_tp@PLT
 ; CHECK-NEXT:    move.l %a0, %d0
 ; CHECK-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a0
-; CHECK-NEXT:    add.l (0,myvar@GOTTPOFF,%a0), %d0
+; CHECK-NEXT:    add.l (myvar@GOTTPOFF,%a0), %d0
 ; CHECK-NEXT:    move.l %d0, %a0
 ; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 
 entry:
   %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
   ret ptr %0
 }
 
 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsld.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=m68k --relocation-model=pic -o - %s | FileCheck %s
 
 @myvar = internal thread_local global i32 2, align 4
 
 define dso_local ptr @get_addr() nounwind {
 ; CHECK-LABEL: get_addr:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    lea (_GLOBAL_OFFSET_TABLE_@GOTPCREL,%pc), %a0
-; CHECK-NEXT:    adda.l myvar@TLSLDM, %a0
+; CHECK-NEXT:    lea (myvar@TLSLDM,%a0), %a0
 ; CHECK-NEXT:    move.l %a0, (%sp)
 ; CHECK-NEXT:    jsr (__tls_get_addr@PLT,%pc)
-; CHECK-NEXT:    adda.l myvar@TLSLD, %a0
+; CHECK-NEXT:    lea (myvar@TLSLD,%a0), %a0
 ; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
   ret ptr %0
 }
 
 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)

llvm/test/CodeGen/M68k/TLS/tlsle.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=m68k -o - %s | FileCheck %s
 
 @myvar = internal thread_local global i32 2, align 4
 
 define dso_local ptr @get_addr() nounwind {
 ; CHECK-LABEL: get_addr:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    suba.l #4, %sp
 ; CHECK-NEXT:    jsr __m68k_read_tp@PLT
-; CHECK-NEXT:    adda.l myvar@TPOFF, %a0
+; CHECK-NEXT:    lea (myvar@TPOFF,%a0), %a0
 ; CHECK-NEXT:    adda.l #4, %sp
 ; CHECK-NEXT:    rts
 entry:
   %0 = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @myvar)
   ret ptr %0
 }
 
 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)