[SPIR-V] Simplify regclasses hierarchy and cleanup regbanks

[zuban32]

Summary

The subset of SPIR-V instructions we have a dag pattern for
allows us to distinguish between integer and float versions
of instructions basing on existing constraints (different
GMIR opcodes for integer/FP versions of instructions + type inference),
so FP regclasses are redundant and can be removed.

And since SPIR-V is a virtual ISA it only needs a single regbank
to support instruction selection.

Depends on D153099 and D153100

[iliya-diyachkov]

In general it looks fine. We also need to check testing results.

llvm/lib/Target/SPIRV/SPIRVInstrInfo.td

99

Should $set be i32imm, not ID? OpExtInstImport's result is still ID.

llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp

void SPIRVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   auto SrcOp = I->getOperand(1);
   assert(DstOp.isReg() && SrcOp.isReg() &&
          "Register operands are expected in COPY");
   auto &MRI = I->getMF()->getRegInfo();
   MRI.replaceRegWith(DstOp.getReg(), SrcOp.getReg());
 }
 
 bool SPIRVInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
-  if (MI.getOpcode() == SPIRV::GET_ID || MI.getOpcode() == SPIRV::GET_fID ||
-      MI.getOpcode() == SPIRV::GET_pID || MI.getOpcode() == SPIRV::GET_vfID ||
-      MI.getOpcode() == SPIRV::GET_vID) {
+  if (MI.getOpcode() == SPIRV::GET_ID || MI.getOpcode() == SPIRV::GET_SID ||
+      MI.getOpcode() == SPIRV::GET_VID) {
     auto &MRI = MI.getMF()->getRegInfo();
     MRI.replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
     MI.eraseFromParent();
     return true;
   }
   return false;
 }

llvm/lib/Target/SPIRV/SPIRVInstrInfo.td

 //
 //===----------------------------------------------------------------------===//
 
 include "SPIRVInstrFormats.td"
 include "SPIRVSymbolicOperands.td"
 
 // Codegen only metadata instructions
 let isCodeGenOnly=1 in {
-  def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
-  def DECL_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
+  def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins unknown:$src_id, TYPE:$src_ty)>;
   def GET_ID: Pseudo<(outs ID:$dst_id), (ins ANYID:$src)>;
-  def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
-  def GET_pID: Pseudo<(outs pID:$dst_id), (ins ANYID:$src)>;
-  def GET_vID: Pseudo<(outs vID:$dst_id), (ins ANYID:$src)>;
-  def GET_vfID: Pseudo<(outs vfID:$dst_id), (ins ANYID:$src)>;
+  def GET_SID: Pseudo<(outs SID:$dst_id), (ins ANYID:$src)>;
+  def GET_VID: Pseudo<(outs VID:$dst_id), (ins ANYID:$src)>;
 }
 
 def SPVTypeBin : SDTypeProfile<1, 2, []>;
 
 def assigntype : SDNode<"SPIRVISD::AssignType", SPVTypeBin>;
 
 def : GINodeEquiv<ASSIGN_TYPE, assigntype>;
 
 class BinOp<string name, bits<16> opCode, list<dag> pattern=[]>
                 : Op<opCode, (outs ANYID:$dst), (ins TYPE:$src_ty, ANYID:$src, ANYID:$src2),
                   "$dst = "#name#" $src_ty $src $src2", pattern>;
 
 class BinOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
                 : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
                   "$dst = "#name#" $src_ty $src $src2", [(set ID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
 
-multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0, bit genV = 0> {
-  if genF then
-    def S: BinOpTyped<name, opCode, fID, node>;
-  else
-    def S: BinOpTyped<name, opCode, ID, node>;
-  if genV then {
-    if genF then
-      def V: BinOpTyped<name, opCode, vfID, node>;
-    else
-      def V: BinOpTyped<name, opCode, vID, node>;
-  }
+multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genV = 0> {
+  def S: BinOpTyped<name, opCode, SID, node>;
+  if genV then
+    def V: BinOpTyped<name, opCode, VID, node>;
 }
 
 class UnOp<string name, bits<16> opCode, list<dag> pattern=[]>
                 : Op<opCode, (outs ANYID:$dst), (ins TYPE:$type, ANYID:$src),
                   "$dst = "#name#" $type $src", pattern>;
 class UnOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
                 : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src),
                   "$dst = "#name#" $src_ty $src", [(set ID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;

 // 3.42.2 Debug Instructions
 
 def OpSourceContinued: Op<2, (outs), (ins StringImm:$str, variable_ops),
                   "OpSourceContinued $str">;
 def OpSource: Op<3, (outs), (ins SourceLanguage:$lang, i32imm:$version, variable_ops),
                   "OpSource $lang $version">;
 def OpSourceExtension: Op<4, (outs), (ins StringImm:$extension, variable_ops),
                   "OpSourceExtension $extension">;
-def OpName: Op<5, (outs), (ins ANY:$tar, StringImm:$name, variable_ops), "OpName $tar $name">;
+def OpName: Op<5, (outs), (ins ANYID:$tar, StringImm:$name, variable_ops), "OpName $tar $name">;
 def OpMemberName: Op<6, (outs), (ins TYPE:$ty, i32imm:$mem, StringImm:$name, variable_ops),
                   "OpMemberName $ty $mem $name">;
 def OpString: Op<7, (outs ID:$r), (ins StringImm:$s, variable_ops), "$r = OpString $s">;
 def OpLine: Op<8, (outs), (ins ID:$file, i32imm:$ln, i32imm:$col), "OpLine $file $ln $col">;
 def OpNoLine: Op<317, (outs), (ins), "OpNoLine">;
 def OpModuleProcessed: Op<330, (outs), (ins StringImm:$process, variable_ops),
                   "OpModuleProcessed $process">;
 
 // 3.42.3 Annotation Instructions
 
-def OpDecorate: Op<71, (outs), (ins ANY:$target, Decoration:$dec, variable_ops),
+def OpDecorate: Op<71, (outs), (ins ANYID:$target, Decoration:$dec, variable_ops),
                   "OpDecorate $target $dec">;
 def OpMemberDecorate: Op<72, (outs), (ins TYPE:$t, i32imm:$m, Decoration:$d, variable_ops),
                   "OpMemberDecorate $t $m $d">;
 
 // TODO Currently some deprecated opcodes are missing: OpDecorationGroup,
 // OpGroupDecorate and OpGroupMemberDecorate
 
-def OpDecorateId: Op<332, (outs), (ins ANY:$target, Decoration:$dec, variable_ops),
+def OpDecorateId: Op<332, (outs), (ins ANYID:$target, Decoration:$dec, variable_ops),
                   "OpDecorateId $target $dec">;
-def OpDecorateString: Op<5632, (outs), (ins ANY:$t, Decoration:$d, StringImm:$s, variable_ops),
+def OpDecorateString: Op<5632, (outs), (ins ANYID:$t, Decoration:$d, StringImm:$s, variable_ops),
                   "OpDecorateString $t $d $s">;
 def OpMemberDecorateString: Op<5633, (outs),
                   (ins TYPE:$ty, i32imm:$mem, Decoration:$dec, StringImm:$str, variable_ops),
                   "OpMemberDecorateString $ty $mem $dec $str">;
 
 // 3.42.4 Extension Instructions
 
 def OpExtension: Op<10, (outs), (ins StringImm:$name, variable_ops), "OpExtension $name">;
 def OpExtInstImport: Op<11, (outs ID:$res), (ins StringImm:$extInstsName, variable_ops),
                   "$res = OpExtInstImport $extInstsName">;
-def OpExtInst: Op<12, (outs ID:$res), (ins TYPE:$ty, ID:$set, Extension:$inst, variable_ops),
+def OpExtInst: Op<12, (outs ID:$res), (ins TYPE:$ty, i32imm:$set, Extension:$inst, variable_ops),
                   "$res = OpExtInst $ty $set $inst">;
 
 // 3.42.5 Mode-Setting Instructions
 
 def OpMemoryModel: Op<14, (outs), (ins AddressingModel:$addr, MemoryModel:$mem),
                   "OpMemoryModel $addr $mem">;
 def OpEntryPoint: Op<15, (outs),
                   (ins ExecutionModel:$model, ID:$entry, StringImm:$name, variable_ops),

 
 // 3.42.7 Constant-Creation Instructions
 
 def imm_to_i32 : SDNodeXForm<imm, [{
 return CurDAG->getTargetConstant(
   N->getValueAP().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
-def fimm_to_i32 : SDNodeXForm<imm, [{
+def fimm_to_i32 : SDNodeXForm<fpimm, [{
 return CurDAG->getTargetConstant(
-  N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
+  N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::f32);
 }]>;
 
 def gi_bitcast_fimm_to_i32 : GICustomOperandRenderer<"renderFImm32">,
   GISDNodeXFormEquiv<fimm_to_i32>;
 
 def gi_bitcast_imm_to_i32 : GICustomOperandRenderer<"renderImm32">,
   GISDNodeXFormEquiv<imm_to_i32>;
 
 def PseudoConstI: IntImmLeaf<i32, [{ return Imm.getBitWidth() <= 32; }], imm_to_i32>;
-def PseudoConstF: FPImmLeaf<f32, [{  return true; }], fimm_to_i32>;
+def PseudoConstF: FPImmLeaf<f32, [{ return true; }], fimm_to_i32>;
+
 def ConstPseudoTrue: IntImmLeaf<i32, [{ return Imm.getBitWidth() == 1 && Imm.getZExtValue() == 1; }]>;
 def ConstPseudoFalse: IntImmLeaf<i32, [{ return Imm.getBitWidth() == 1 && Imm.getZExtValue() == 0; }]>;
 def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;
 
 multiclass IntFPImm<bits<16> opCode, string name> {
   def I: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src, variable_ops),
                   "$dst = "#name#" $type $src", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
-  def F: Op<opCode, (outs ID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
+  def F: Op<opCode, (outs ID:$dst), (ins TYPE:$type, FID:$src, variable_ops),
                   "$dst = "#name#" $type $src", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
 }
 
 def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
                       [(set ID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
 def OpConstantFalse: Op<42, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
                       [(set ID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;
 

 def OpPtrCastToGeneric : UnOp<"OpPtrCastToGeneric", 121>;
 def OpGenericCastToPtr : UnOp<"OpGenericCastToPtr", 122>;
 def OpGenericCastToPtrExplicit : Op<123, (outs ID:$r), (ins TYPE:$t, ID:$p, StorageClass:$s),
                               "$r = OpGenericCastToPtrExplicit $t $p $s">;
 def OpBitcast : UnOp<"OpBitcast", 124>;
 
 // 3.42.12 Composite Instructions
 
-def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
-                  "$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
-
+def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$idx),
+                  "$res = OpVectorExtractDynamic $ty $vec $idx">;
 def OpVectorInsertDynamic: Op<78, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$comp, ID:$idx),
                   "$res = OpVectorInsertDynamic $ty $vec $comp $idx">;
 def OpVectorShuffle: Op<79, (outs ID:$res), (ins TYPE:$ty, ID:$v1, ID:$v2, variable_ops),
                   "$res = OpVectorShuffle $ty $v1 $v2">;
 def OpCompositeConstruct: Op<80, (outs ID:$res), (ins TYPE:$type, variable_ops),
                   "$res = OpCompositeConstruct $type">;
 def OpCompositeExtract: Op<81, (outs ID:$res), (ins TYPE:$type, ID:$base, variable_ops),
                   "$res = OpCompositeExtract $type $base">;
 def OpCompositeInsert: Op<82, (outs ID:$r), (ins TYPE:$ty, ID:$obj, ID:$base, variable_ops),
                   "$r = OpCompositeInsert $ty $obj $base">;
 def OpCopyObject: UnOp<"OpCopyObject", 83>;
 def OpTranspose: UnOp<"OpTranspose", 84>;
 def OpCopyLogical: UnOp<"OpCopyLogical", 400>;
 
 // 3.42.13 Arithmetic Instructions
 
 def OpSNegate: UnOp<"OpSNegate", 126>;
-def OpFNegate: UnOpTyped<"OpFNegate", 127, fID, fneg>;
-def OpFNegateV: UnOpTyped<"OpFNegate", 127, vfID, fneg>;
-defm OpIAdd: BinOpTypedGen<"OpIAdd", 128, add, 0, 1>;
-defm OpFAdd: BinOpTypedGen<"OpFAdd", 129, fadd, 1, 1>;
-
-defm OpISub: BinOpTypedGen<"OpISub", 130, sub, 0, 1>;
-defm OpFSub: BinOpTypedGen<"OpFSub", 131, fsub, 1, 1>;
-
-defm OpIMul: BinOpTypedGen<"OpIMul", 132, mul, 0, 1>;
-defm OpFMul: BinOpTypedGen<"OpFMul", 133, fmul, 1, 1>;
-
-defm OpUDiv: BinOpTypedGen<"OpUDiv", 134, udiv, 0, 1>;
-defm OpSDiv: BinOpTypedGen<"OpSDiv", 135, sdiv, 0, 1>;
-defm OpFDiv: BinOpTypedGen<"OpFDiv", 136, fdiv, 1, 1>;
+def OpFNegate: UnOpTyped<"OpFNegate", 127, SID, fneg>;
+def OpFNegateV: UnOpTyped<"OpFNegate", 127, VID, fneg>;
+defm OpIAdd: BinOpTypedGen<"OpIAdd", 128, add, 1>;
+defm OpFAdd: BinOpTypedGen<"OpFAdd", 129, fadd, 1>;
+
+defm OpISub: BinOpTypedGen<"OpISub", 130, sub, 1>;
+defm OpFSub: BinOpTypedGen<"OpFSub", 131, fsub, 1>;
+
+defm OpIMul: BinOpTypedGen<"OpIMul", 132, mul, 1>;
+defm OpFMul: BinOpTypedGen<"OpFMul", 133, fmul, 1>;
+
+defm OpUDiv: BinOpTypedGen<"OpUDiv", 134, udiv, 1>;
+defm OpSDiv: BinOpTypedGen<"OpSDiv", 135, sdiv, 1>;
+defm OpFDiv: BinOpTypedGen<"OpFDiv", 136, fdiv, 1>;
 
-defm OpUMod: BinOpTypedGen<"OpUMod", 137, urem, 0, 1>;
-defm OpSRem: BinOpTypedGen<"OpSRem", 138, srem, 0, 1>;
+defm OpUMod: BinOpTypedGen<"OpUMod", 137, urem, 1>;
+defm OpSRem: BinOpTypedGen<"OpSRem", 138, srem, 1>;
 
 def OpSMod: BinOp<"OpSMod", 139>;
 
-defm OpFRem: BinOpTypedGen<"OpFRem", 140, frem, 1, 1>;
+defm OpFRem: BinOpTypedGen<"OpFRem", 140, frem, 1>;
 def OpFMod: BinOp<"OpFMod", 141>;
 
 def OpVectorTimesScalar: BinOp<"OpVectorTimesScalar", 142>;
 def OpMatrixTimesScalar: BinOp<"OpMatrixTimesScalar", 143>;
 def OpVectorTimesMatrix: BinOp<"OpVectorTimesMatrix", 144>;
 def OpMatrixTimesVector: BinOp<"OpMatrixTimesVector", 145>;
 def OpMatrixTimesMatrix: BinOp<"OpMatrixTimesMatrix", 146>;
 
 def OpOuterProduct: BinOp<"OpOuterProduct", 147>;
 def OpDot: BinOp<"OpDot", 148>;
 
 def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, ID, addc>;
 def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, ID, subc>;
 def OpUMulExtended: BinOp<"OpUMulExtended", 151>;
 def OpSMulExtended: BinOp<"OpSMulExtended", 152>;
 
 // 3.42.14 Bit Instructions
 
-defm OpShiftRightLogical: BinOpTypedGen<"OpShiftRightLogical", 194, srl, 0, 1>;
-defm OpShiftRightArithmetic: BinOpTypedGen<"OpShiftRightArithmetic", 195, sra, 0, 1>;
-defm OpShiftLeftLogical: BinOpTypedGen<"OpShiftLeftLogical", 196, shl, 0, 1>;
-
-defm OpBitwiseOr: BinOpTypedGen<"OpBitwiseOr", 197, or, 0, 1>;
-defm OpBitwiseXor: BinOpTypedGen<"OpBitwiseXor", 198, xor, 0, 1>;
-defm OpBitwiseAnd: BinOpTypedGen<"OpBitwiseAnd", 199, and, 0, 1>;
+defm OpShiftRightLogical: BinOpTypedGen<"OpShiftRightLogical", 194, srl, 1>;
+defm OpShiftRightArithmetic: BinOpTypedGen<"OpShiftRightArithmetic", 195, sra, 1>;
+defm OpShiftLeftLogical: BinOpTypedGen<"OpShiftLeftLogical", 196, shl, 1>;
+
+defm OpBitwiseOr: BinOpTypedGen<"OpBitwiseOr", 197, or, 1>;
+defm OpBitwiseXor: BinOpTypedGen<"OpBitwiseXor", 198, xor, 1>;
+defm OpBitwiseAnd: BinOpTypedGen<"OpBitwiseAnd", 199, and, 1>;
 def OpNot: UnOp<"OpNot", 200>;
 
 def OpBitFieldInsert: Op<201, (outs ID:$res),
                   (ins TYPE:$ty, ID:$base, ID:$insert, ID:$offset, ID:$count),
                   "$res = OpBitFieldInsert $ty $base $insert $offset $count">;
 def OpBitFieldSExtract: Op<202, (outs ID:$res),
                   (ins TYPE:$ty, ID:$base, ID:$offset, ID:$count),
                   "$res = OpBitFieldSExtract $ty $base $offset $count">;

llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
   for (MachineInstr *MI : ToErase)
     MI->eraseFromParent();
 }
 
 static std::pair<Register, unsigned>
 createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI,
                const SPIRVGlobalRegistry &GR) {
   LLT NewT = LLT::scalar(32);
-  SPIRVType *SpvType = GR.getSPIRVTypeForVReg(ValReg);
-  assert(SpvType && "VReg is expected to have SPIRV type");
-  bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
-  bool IsVectorFloat =
-      SpvType->getOpcode() == SPIRV::OpTypeVector &&
-      GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() ==
-          SPIRV::OpTypeFloat;
-  IsFloat |= IsVectorFloat;
-  auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
-  if (MRI.getType(ValReg).isPointer()) {
-    NewT = LLT::pointer(0, 32);
-    GetIdOp = SPIRV::GET_pID;
-  } else if (MRI.getType(ValReg).isVector()) {
+  auto GetIdOp = SPIRV::GET_SID;
+  if (MRI.getType(ValReg).isVector()) {
     NewT = LLT::fixed_vector(2, NewT);
-    GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
+    GetIdOp = SPIRV::GET_VID;
   }
   Register IdReg = MRI.createGenericVirtualRegister(NewT);
   return {IdReg, GetIdOp};
 }
 
 static void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
                          MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR) {
   unsigned Opc = MI.getOpcode();

llvm/lib/Target/SPIRV/SPIRVRegisterBankInfo.cpp

 
 using namespace llvm;
 
 // This required for .td selection patterns to work or we'd end up with RegClass
 // checks being redundant as all the classes would be mapped to the same bank.
 const RegisterBank &
 SPIRVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
                                               LLT Ty) const {
-  switch (RC.getID()) {
-  case SPIRV::TYPERegClassID:
-    return SPIRV::TYPERegBank;
-  case SPIRV::pIDRegClassID:
-  case SPIRV::IDRegClassID:
-    return SPIRV::IDRegBank;
-  case SPIRV::fIDRegClassID:
-    return SPIRV::fIDRegBank;
-  case SPIRV::vIDRegClassID:
-    return SPIRV::vIDRegBank;
-  case SPIRV::vfIDRegClassID:
-    return SPIRV::vfIDRegBank;
-  case SPIRV::ANYIDRegClassID:
-  case SPIRV::ANYRegClassID:
-    return SPIRV::IDRegBank;
-  }
-  llvm_unreachable("Unknown register class");
 }

llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td

 //===-- SPIRVRegisterBanks.td - Describe SPIR-V RegBanks ---*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-// Although RegisterBankSelection is disabled we need to distinct the banks
-// as InstructionSelector RegClass checking code relies on them
-def IDRegBank : RegisterBank<"IDBank", [ID]>;
-def fIDRegBank : RegisterBank<"fIDBank", [fID]>;
-def vIDRegBank : RegisterBank<"vIDBank", [vID]>;
-def vfIDRegBank : RegisterBank<"vfIDBank", [vfID]>;
-def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
+// Although RegBankSelect is disabled, we need to have
+// at least one regbank to support instruction selector
+def IDRegBank : RegisterBank<"IDBank", [ID]>;

llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td

 //===-- SPIRVRegisterInfo.td - SPIR-V Register defs --------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 //  Declarations that describe the SPIR-V register file.
 //
 //===----------------------------------------------------------------------===//
 
 let Namespace = "SPIRV" in {
   def p0 : PtrValueType <i32, 0>;
-  // All registers are for 32-bit identifiers, so have a single dummy register
 
   // Class for registers that are the result of OpTypeXXX instructions
   def TYPE0 : Register<"TYPE0">;
   def TYPE : RegisterClass<"SPIRV", [i32], 32, (add TYPE0)>;
 
   // Class for every other non-type ID
   def ID0 : Register<"ID0">;
   def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
-  def fID0 : Register<"FID0">;
-  def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
-  def pID0 : Register<"pID0">;
-  def pID : RegisterClass<"SPIRV", [p0], 32, (add pID0)>;
-  def vID0 : Register<"pID0">;
-  def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>;
-  def vfID0 : Register<"pID0">;
-  def vfID : RegisterClass<"SPIRV", [v2f32], 32, (add vfID0)>;
+  def VID0 : Register<"VID0">;
 
-  def ANYID : RegisterClass<"SPIRV", [i32, f32, p0, v2i32, v2f32], 32, (add ID, fID, pID, vID, vfID)>;
+  // TODO: FID register class is only needed for constants selection,
+  //       consider redesigning the pattern to get rid of this
+  def FID0 : Register<"FID0">;
+  def FID : RegisterClass<"SPIRV", [f32], 32, (add FID0)>;
 
-  // A few instructions like OpName can take ids from both type and non-type
-  // instructions, so we need a super-class to allow for both to count as valid
-  // arguments for these instructions.
-  def ANY : RegisterClass<"SPIRV", [i32], 32, (add TYPE, ID)>;
+  // Scalar ID
+  def SID : RegisterClass<"SPIRV", [i32, f32, p0], 32, (add ID0)>;
+  // Vector ID
+  def VID : RegisterClass<"SPIRV", [v2i32, v2f32], 32, (add VID0)>;
+  def ANYID : RegisterClass<"SPIRV", [i32, f32, p0, v2i32, v2f32], 32, (add SID, VID)>;
 }