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Differential D152339

[PowerPC][NFC] add SADDO/SSUBO test case
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Authored by tingwang on Jun 6 2023, 10:24 PM.

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shchenz
nemanjai
qiucf
Group Reviewers
Restricted Project
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rG0b955fee90aa: [PowerPC][NFC] add SADDO/SSUBO test case
Summary

Add baseline test case.

Diff Detail

Event Timeline

tingwang created this revision.Jun 6 2023, 10:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 6 2023, 10:24 PM
tingwang requested review of this revision.Jun 6 2023, 10:24 PM
Herald added a subscriber: llvm-commits. · View Herald TranscriptJun 6 2023, 10:24 PM
qiucf accepted this revision as: qiucf.Jun 6 2023, 10:36 PM
qiucf added a subscriber: qiucf.

I think you can commit it directly.

This revision is now accepted and ready to land.Jun 6 2023, 10:36 PM
tingwang added a child revision: D152342: [PowerPC] calculate sadd/ssub overflow by sign bits.Jun 6 2023, 10:48 PM
Harbormaster completed remote builds in B237170: Diff 529159.Jun 6 2023, 11:39 PM
Closed by commit rG0b955fee90aa: [PowerPC][NFC] add SADDO/SSUBO test case (authored by tingwang). · Explain WhyJun 29 2023, 5:36 PM
This revision was automatically updated to reflect the committed changes.
tingwang added a commit: rG0b955fee90aa: [PowerPC][NFC] add SADDO/SSUBO test case.

Revision Contents

PathSize
llvm/
test/
CodeGen/
PowerPC/
173 lines

Diff 536067

llvm/test/CodeGen/PowerPC/saddo-ssubo.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8) nounwind readnone
declare { i16, i1 } @llvm.sadd.with.overflow.i16(i16, i16) nounwind readnone
declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
declare { i64, i1 } @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
declare { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8) nounwind readnone
declare { i16, i1 } @llvm.ssub.with.overflow.i16(i16, i16) nounwind readnone
declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
declare { i64, i1 } @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
declare { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define i1 @test_saddo_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: test_saddo_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: extsb 4, 4
; CHECK-NEXT: extsb 3, 3
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: extsb 4, 3
; CHECK-NEXT: cmpw 4, 3
; CHECK-NEXT: iseleq 3, 0, 5
; CHECK-NEXT: blr
entry:
%res = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %a, i8 %b) nounwind
%overflow = extractvalue { i8, i1 } %res, 1
ret i1 %overflow
}
define i1 @test_saddo_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: test_saddo_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: extsh 4, 4
; CHECK-NEXT: extsh 3, 3
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: extsh 4, 3
; CHECK-NEXT: cmpw 4, 3
; CHECK-NEXT: iseleq 3, 0, 5
; CHECK-NEXT: blr
entry:
%res = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 %a, i16 %b) nounwind
%overflow = extractvalue { i16, i1 } %res, 1
ret i1 %overflow
}
define i1 @test_saddo_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_saddo_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add 5, 3, 4
; CHECK-NEXT: cmpwi 1, 4, 0
; CHECK-NEXT: cmpw 5, 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: creqv 20, 4, 0
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
entry:
%res = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) nounwind
%overflow = extractvalue { i32, i1 } %res, 1
ret i1 %overflow
}
define i1 @test_saddo_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_saddo_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add 5, 3, 4
; CHECK-NEXT: cmpdi 1, 4, 0
; CHECK-NEXT: cmpd 5, 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: creqv 20, 4, 0
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
entry:
%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) nounwind
%overflow = extractvalue { i64, i1 } %res, 1
ret i1 %overflow
}
define <4 x i1> @test_saddo_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; CHECK-LABEL: test_saddo_v4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vaddsws 4, 2, 3
; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: vcmpequw 2, 2, 4
; CHECK-NEXT: xxlnor 34, 34, 34
; CHECK-NEXT: blr
entry:
%res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) nounwind
%overflow = extractvalue { <4 x i32>, <4 x i1> } %res, 1
ret <4 x i1> %overflow
}
define i1 @test_ssubo_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: test_ssubo_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: extsb 3, 3
; CHECK-NEXT: extsb 4, 4
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: sub 3, 3, 4
; CHECK-NEXT: extsb 4, 3
; CHECK-NEXT: cmpw 4, 3
; CHECK-NEXT: iseleq 3, 0, 5
; CHECK-NEXT: blr
entry:
%res = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %a, i8 %b) nounwind
%overflow = extractvalue { i8, i1 } %res, 1
ret i1 %overflow
}
define i1 @test_ssubo_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: test_ssubo_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: extsh 3, 3
; CHECK-NEXT: extsh 4, 4
; CHECK-NEXT: li 5, 1
; CHECK-NEXT: sub 3, 3, 4
; CHECK-NEXT: extsh 4, 3
; CHECK-NEXT: cmpw 4, 3
; CHECK-NEXT: iseleq 3, 0, 5
; CHECK-NEXT: blr
entry:
%res = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 %a, i16 %b) nounwind
%overflow = extractvalue { i16, i1 } %res, 1
ret i1 %overflow
}
define i1 @test_ssubo_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_ssubo_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: cmpwi 1, 4, 0
; CHECK-NEXT: cmpw 5, 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: creqv 20, 5, 0
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
entry:
%res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind
%overflow = extractvalue { i32, i1 } %res, 1
ret i1 %overflow
}
define i1 @test_ssubo_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_ssubo_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub 5, 3, 4
; CHECK-NEXT: cmpdi 1, 4, 0
; CHECK-NEXT: cmpd 5, 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: creqv 20, 5, 0
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: blr
entry:
%res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind
%overflow = extractvalue { i64, i1 } %res, 1
ret i1 %overflow
}
define <4 x i1> @test_ssubo_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; CHECK-LABEL: test_ssubo_v4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsubsws 4, 2, 3
; CHECK-NEXT: vsubuwm 2, 2, 3
; CHECK-NEXT: vcmpequw 2, 2, 4
; CHECK-NEXT: xxlnor 34, 34, 34
; CHECK-NEXT: blr
entry:
%res = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) nounwind
%overflow = extractvalue { <4 x i32>, <4 x i1> } %res, 1
ret <4 x i1> %overflow
}