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Differential D151545

[ASAN] Support memeory check for masked.gather/scatter.
ClosedPublic

Authored by fakepaper56 on May 26 2023, 2:05 AM.

Details

Reviewers
reames
MaskRay
usama54321
craig.topper
Commits
rGf2977fc45686: [ASAN] Support memeory check for masked.gather/scatter.
Summary

The patch handle masked.gather/scatter just like the way D149245 handles
vp.gather/scatter.

Diff Detail

Event Timeline

fakepaper56 created this revision.May 26 2023, 2:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 26 2023, 2:05 AM
Herald added subscribers: Enna1, hiraditya. · View Herald Transcript
fakepaper56 requested review of this revision.May 26 2023, 2:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 26 2023, 2:05 AM
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Harbormaster completed remote builds in B234803: Diff 525992.May 26 2023, 2:59 AM
fakepaper56 updated this revision to Diff 530502.Jun 12 2023, 7:31 AM

Rebase and ping.

Harbormaster completed remote builds in B238184: Diff 530502.Jun 12 2023, 8:00 AM
fakepaper56 updated this revision to Diff 533166.Jun 21 2023, 12:41 AM

Rebase and ping.

Harbormaster completed remote builds in B240179: Diff 533166.Jun 21 2023, 1:16 AM
fakepaper56 updated this revision to Diff 535038.Jun 27 2023, 10:07 AM

Rebase and ping.

Harbormaster completed remote builds in B241529: Diff 535038.Jun 27 2023, 12:11 PM
craig.topper accepted this revision.Jul 3 2023, 9:49 AM

LGTM

This revision is now accepted and ready to land.Jul 3 2023, 9:49 AM
This revision was landed with ongoing or failed builds.Jul 4 2023, 6:18 PM
Closed by commit rGf2977fc45686: [ASAN] Support memeory check for masked.gather/scatter. (authored by fakepaper56). · Explain Why
This revision was automatically updated to reflect the committed changes.
fakepaper56 added a commit: rGf2977fc45686: [ASAN] Support memeory check for masked.gather/scatter..
Herald added a subscriber: wangpc. · View Herald TranscriptJul 4 2023, 6:18 PM

Revision Contents

PathSize
llvm/
lib/
Transforms/
Instrumentation/
6 lines
test/
Instrumentation/
AddressSanitizer/
64 lines

Diff 537192

llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Show First 20 Lines • Show All 1,325 Lines • ▼ Show 20 Lines if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
if (!ClInstrumentAtomics || ignoreAccess(I, XCHG->getPointerOperand())) if (!ClInstrumentAtomics || ignoreAccess(I, XCHG->getPointerOperand()))
return; return;
Interesting.emplace_back(I, XCHG->getPointerOperandIndex(), true, Interesting.emplace_back(I, XCHG->getPointerOperandIndex(), true,
XCHG->getCompareOperand()->getType(), XCHG->getCompareOperand()->getType(),
std::nullopt); std::nullopt);
} else if (auto CI = dyn_cast<CallInst>(I)) { } else if (auto CI = dyn_cast<CallInst>(I)) {
switch (CI->getIntrinsicID()) { switch (CI->getIntrinsicID()) {
case Intrinsic::masked_load: case Intrinsic::masked_load:
case Intrinsic::masked_store: { case Intrinsic::masked_store:
bool IsWrite = CI->getIntrinsicID() == Intrinsic::masked_store; case Intrinsic::masked_gather:
case Intrinsic::masked_scatter: {
bool IsWrite = CI->getType()->isVoidTy();
// Masked store has an initial operand for the value. // Masked store has an initial operand for the value.
unsigned OpOffset = IsWrite ? 1 : 0; unsigned OpOffset = IsWrite ? 1 : 0;
if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads) if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)
return; return;
auto BasePtr = CI->getOperand(OpOffset); auto BasePtr = CI->getOperand(OpOffset);
if (ignoreAccess(I, BasePtr)) if (ignoreAccess(I, BasePtr))
return; return;
▲ Show 20 Lines • Show All 2,255 Lines • Show Last 20 Lines

llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll

Show First 20 Lines • Show All 367 Lines • ▼ Show 20 Lines
; ;
; DISABLED-LABEL: @scalable.store.nxv4f32( ; DISABLED-LABEL: @scalable.store.nxv4f32(
; DISABLED-NEXT: tail call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> [[ARG:%.*]], ptr [[P:%.*]], i32 4, <vscale x 4 x i1> [[MASK:%.*]]) ; DISABLED-NEXT: tail call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> [[ARG:%.*]], ptr [[P:%.*]], i32 4, <vscale x 4 x i1> [[MASK:%.*]])
; DISABLED-NEXT: ret void ; DISABLED-NEXT: ret void
; ;
tail call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> %arg, ptr %p, i32 4, <vscale x 4 x i1> %mask) tail call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> %arg, ptr %p, i32 4, <vscale x 4 x i1> %mask)
ret void ret void
} }
; Test masked.gather/scatter.
declare <vscale x 4 x float> @llvm.masked.gather.nxv4f32.nxv4p0(<vscale x 4 x ptr>, i32, <vscale x 4 x i1>, <vscale x 4 x float>)
declare void @llvm.masked.scatter.nxv4f32.nxv4p0(<vscale x 4 x float>, <vscale x 4 x ptr>, i32, <vscale x 4 x i1>)
define <vscale x 4 x float> @scalable.gather.nxv4f32(<vscale x 4 x ptr> %vp, <vscale x 4 x i1> %mask, i32 %evl) sanitize_address {
; CHECK-LABEL: @scalable.gather.nxv4f32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 4
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
; CHECK: .split:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP7:%.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7]]
; CHECK: 4:
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 4 x ptr> [[VP:%.*]], i64 [[IV]]
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; CHECK-NEXT: call void @__asan_load4(i64 [[TMP6]])
; CHECK-NEXT: br label [[TMP7]]
; CHECK: 7:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP2]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
; CHECK: .split.split:
; CHECK-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.masked.gather.nxv4f32.nxv4p0(<vscale x 4 x ptr> [[VP]], i32 4, <vscale x 4 x i1> [[MASK]], <vscale x 4 x float> undef)
; CHECK-NEXT: ret <vscale x 4 x float> [[RES]]
;
; DISABLED-LABEL: @scalable.gather.nxv4f32(
; DISABLED-NEXT: [[RES:%.*]] = tail call <vscale x 4 x float> @llvm.masked.gather.nxv4f32.nxv4p0(<vscale x 4 x ptr> [[VP:%.*]], i32 4, <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> undef)
; DISABLED-NEXT: ret <vscale x 4 x float> [[RES]]
;
%res = tail call <vscale x 4 x float> @llvm.masked.gather.nxv4f32.nxv4p0(<vscale x 4 x ptr> %vp, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x float> undef)
ret <vscale x 4 x float> %res
}
define void @scalable.scatter.nxv4f32(<vscale x 4 x float> %val, <vscale x 4 x ptr> %vp, <vscale x 4 x i1> %mask, i32 %evl) sanitize_address {
; CHECK-LABEL: @scalable.scatter.nxv4f32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 4
; CHECK-NEXT: br label [[DOTSPLIT:%.*]]
; CHECK: .split:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[IV_NEXT:%.*]], [[TMP7:%.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <vscale x 4 x i1> [[MASK:%.*]], i64 [[IV]]
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7]]
; CHECK: 4:
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 4 x ptr> [[VP:%.*]], i64 [[IV]]
; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64
; CHECK-NEXT: call void @__asan_store4(i64 [[TMP6]])
; CHECK-NEXT: br label [[TMP7]]
; CHECK: 7:
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP2]]
; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]
; CHECK: .split.split:
; CHECK-NEXT: tail call void @llvm.masked.scatter.nxv4f32.nxv4p0(<vscale x 4 x float> [[VAL:%.*]], <vscale x 4 x ptr> [[VP]], i32 4, <vscale x 4 x i1> [[MASK]])
; CHECK-NEXT: ret void
;
; DISABLED-LABEL: @scalable.scatter.nxv4f32(
; DISABLED-NEXT: tail call void @llvm.masked.scatter.nxv4f32.nxv4p0(<vscale x 4 x float> [[VAL:%.*]], <vscale x 4 x ptr> [[VP:%.*]], i32 4, <vscale x 4 x i1> [[MASK:%.*]])
; DISABLED-NEXT: ret void
;
tail call void @llvm.masked.scatter.nxv4f32.nxv4p0(<vscale x 4 x float> %val, <vscale x 4 x ptr> %vp, i32 4, <vscale x 4 x i1> %mask)
ret void
}