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AMDGPU: Drop FP_ROUND second value check
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Authored by arsenm on May 23 2023, 3:05 AM.

Reviewers

foad
Pierre-vh

Group Reviewers

Restricted Project

Summary

This doesn't mean what I thought it meant and is an optimization
hint flag.

	Time	Test
	60,060 ms	x64 debian > MLIR.Examples/standalone::test.toy

arsenm requested review of this revision.May 23 2023, 3:05 AM

This revision is now accepted and ready to land.May 23 2023, 3:32 AM

Path

Size

llvm/

lib/

Target/

AMDGPU/

3 lines

Show First 20 Lines • Show All 11,133 Lines • ▼ Show 20 Lines	assert(Subtarget->has16BitInsts() && !Subtarget->hasMed3_16() &&
"combine only useful on gfx8");		"combine only useful on gfx8");

SDValue TruncSrc = N->getOperand(0);		SDValue TruncSrc = N->getOperand(0);
EVT VT = N->getValueType(0);		EVT VT = N->getValueType(0);
if (VT != MVT::f16)		if (VT != MVT::f16)
return SDValue();		return SDValue();

if (TruncSrc.getOpcode() != AMDGPUISD::FMED3 \|\|		if (TruncSrc.getOpcode() != AMDGPUISD::FMED3 \|\|
TruncSrc.getValueType() != MVT::f32 \|\| !TruncSrc.hasOneUse() \|\|		TruncSrc.getValueType() != MVT::f32 \|\| !TruncSrc.hasOneUse())
!isNullConstant(N->getOperand(1)))
return SDValue();		return SDValue();

SelectionDAG &DAG = DCI.DAG;		SelectionDAG &DAG = DCI.DAG;
SDLoc SL(N);		SDLoc SL(N);

// Optimize f16 fmed3 pattern performed on f32. On gfx8 there is no f16 fmed3,		// Optimize f16 fmed3 pattern performed on f32. On gfx8 there is no f16 fmed3,
// and expanding it with min/max saves 1 instruction vs. casting to f32 and		// and expanding it with min/max saves 1 instruction vs. casting to f32 and
// casting back.		// casting back.
▲ Show 20 Lines • Show All 2,477 Lines • Show Last 20 Lines