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Differential D150949

[X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
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Authored by skan on May 19 2023, 2:54 AM.

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rG5586bc539acb: [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize…
Summary

This is follow-up of D150107.

In addition, the function X86::optimizeToFixedRegisterOrShortImmediateForm can be
shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.

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Event Timeline

skan created this revision.May 19 2023, 2:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 19 2023, 2:54 AM
Herald added subscribers: wenlei, pengfei, asbirlea and 3 others. · View Herald Transcript
skan requested review of this revision.May 19 2023, 2:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 19 2023, 2:54 AM
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skan edited the summary of this revision. (Show Details)May 19 2023, 2:57 AM
skan added a comment.May 19 2023, 3:10 AM

This change is straightforward to me. I tend to land it first to avoid more tests for ADD/AND/OR/SUB/XOR/CMP with i8 being added. The update in llvm/test/CodeGen/X86/avxvnni-combine.ll is due to the impact on machine schedule.
Opened a revision here for possible discussions.

This revision was not accepted when it landed; it landed in state Needs Review.May 19 2023, 3:22 AM
This revision was landed with ongoing or failed builds.
Closed by commit rG5586bc539acb: [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize… (authored by skan). · Explain Why
This revision was automatically updated to reflect the committed changes.
skan added a commit: rG5586bc539acb: [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize….
Harbormaster completed remote builds in B233128: Diff 523706.May 19 2023, 3:47 AM
hans added a reverting change: rGcb16b33a03af: Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during….May 19 2023, 5:43 AM

Revision Contents
Changeset List

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llvm/
lib/
Target/
X86/
MCTargetDesc/
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test/
CodeGen/
MIR/
X86/
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X86/
AMX/
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GlobalISel/
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DebugInfo/
MIR/
InstrRef/
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X86/
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X86/
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assignment-tracking/
X86/
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TableGen/
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Transforms/
SampleProfile/
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utils/
TableGen/
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Diff 523716

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llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h

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llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp

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llvm/lib/Target/X86/X86CallFrameOptimization.cpp

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llvm/lib/Target/X86/X86DynAllocaExpander.cpp

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llvm/lib/Target/X86/X86FastISel.cpp

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llvm/lib/Target/X86/X86FixupLEAs.cpp

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llvm/lib/Target/X86/X86FrameLowering.cpp

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llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

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llvm/lib/Target/X86/X86ISelLowering.cpp

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llvm/lib/Target/X86/X86InstrAVX512.td

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llvm/lib/Target/X86/X86InstrArithmetic.td

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llvm/lib/Target/X86/X86InstrCompiler.td

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llvm/lib/Target/X86/X86InstrInfo.cpp

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llvm/lib/Target/X86/X86InstructionSelector.cpp

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llvm/lib/Target/X86/X86MCInstLower.cpp

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llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir

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llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll

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llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir

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llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir

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llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir

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llvm/test/CodeGen/X86/GlobalISel/select-ext.mir

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llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir

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llvm/test/CodeGen/X86/avxvnni-combine.ll

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llvm/test/CodeGen/X86/cfi-xmm.ll

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llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll

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llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir

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llvm/test/CodeGen/X86/leaFixup32.mir

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llvm/test/CodeGen/X86/leaFixup64.mir

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llvm/test/CodeGen/X86/limit-split-cost.mir

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llvm/test/CodeGen/X86/optimize-compare.mir

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llvm/test/CodeGen/X86/pr46827.ll

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llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll

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llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll

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llvm/test/CodeGen/X86/tail-call-conditional.mir

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llvm/test/CodeGen/X86/tail-merge-after-mbp.mir

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llvm/test/CodeGen/X86/throws-cfi-fp.ll

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llvm/test/CodeGen/X86/update-terminator-debugloc.ll

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llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir

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llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir

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llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir

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llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir

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llvm/test/DebugInfo/MIR/X86/empty-inline.mir

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llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir

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llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir

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llvm/test/DebugInfo/MIR/X86/machinesink-subreg.mir

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llvm/test/DebugInfo/MIR/X86/machinesink.mir

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llvm/test/DebugInfo/MIR/X86/merge-inline-loc4.mir

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llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir

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llvm/test/DebugInfo/X86/debug-loc-asan.mir

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llvm/test/DebugInfo/X86/debug-loc-offset.mir

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llvm/test/DebugInfo/X86/location-range.mir

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llvm/test/DebugInfo/X86/machinecse-wrongdebug-hoist.ll

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llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll

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llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll

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llvm/test/TableGen/x86-fold-tables.inc

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llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll

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llvm/utils/TableGen/X86ManualFoldTables.def

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