This is an archive of the discontinued LLVM Phabricator instance.

hzq retitled this revision from [GlobalISel] Fix the erroneous transformation of BRCOND to BCC. to [GlobalISel] Fix the error transformation of BRCOND to BCC..May 20 2023, 5:04 AM

hzq edited the summary of this revision. (Show Details)

hzq edited the summary of this revision. (Show Details)May 20 2023, 5:47 AM

@paquette @kristof.beyls Could you please review these code modifications for me? Will greatly appreciate your assistance.

peixin added reviewers: dmgreen, dzhidzhoev.Jun 27 2023, 5:46 AM

I think this LGTM. Thanks

This revision is now accepted and ready to land.Jun 27 2023, 1:13 PM

Thanks @dmgreen. Will wait for one more day before landing this patch in case others have comments.

Closed by commit rGf4ba1db5bf88: [GlobalISel] Fix the error transformation of BRCOND to BCC (authored by hezuoqiang <hezuoqiang2@huawei.com>, committed by Allen). · Explain WhyJul 13 2023, 6:20 AM

This revision was automatically updated to reflect the committed changes.

Allen added a commit: rGf4ba1db5bf88: [GlobalISel] Fix the error transformation of BRCOND to BCC.

Revision Contents

Path

Size

llvm/

lib/

Target/

AArch64/

GISel/

AArch64InstructionSelector.cpp

2 lines

test/

CodeGen/

AArch64/

GlobalISel/

speculative-hardening-brcond.mir

2 lines

Diff 539991

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 1,779 Lines • ▼ Show 20 Lines	if (ProduceNonFlagSettingCondBr) {
return true;		return true;
}		}

// Can't emit TB(N)Z/CB(N)Z. Emit a tst + bcc instead.		// Can't emit TB(N)Z/CB(N)Z. Emit a tst + bcc instead.
auto TstMI =		auto TstMI =
MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1);		MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1);
constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);		constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
auto Bcc = MIB.buildInstr(AArch64::Bcc)		auto Bcc = MIB.buildInstr(AArch64::Bcc)
.addImm(AArch64CC::EQ)		.addImm(AArch64CC::NE)
.addMBB(I.getOperand(1).getMBB());		.addMBB(I.getOperand(1).getMBB());
I.eraseFromParent();		I.eraseFromParent();
return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);		return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);
}		}

/// Returns the element immediate value of a vector shift operand if found.		/// Returns the element immediate value of a vector shift operand if found.
/// This needs to detect a splat-like operation, e.g. a G_BUILD_VECTOR.		/// This needs to detect a splat-like operation, e.g. a G_BUILD_VECTOR.
static std::optional<int64_t> getVectorShiftImm(Register Reg,		static std::optional<int64_t> getVectorShiftImm(Register Reg,
▲ Show 20 Lines • Show All 5,282 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir

	Show All 15 Lines
	legalized: true			legalized: true
	regBankSelected: true			regBankSelected: true
	body: \|			body: \|
	; CHECK-LABEL: name: no_tbnz			; CHECK-LABEL: name: no_tbnz
	; CHECK: bb.0:			; CHECK: bb.0:
	; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)			; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
	; CHECK: %reg:gpr32 = COPY $w0			; CHECK: %reg:gpr32 = COPY $w0
	; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg, 1, implicit-def $nzcv			; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg, 1, implicit-def $nzcv
	; CHECK: Bcc 0, %bb.1, implicit $nzcv			; CHECK: Bcc 1, %bb.1, implicit $nzcv
	; CHECK: B %bb.0			; CHECK: B %bb.0
	; CHECK: bb.1:			; CHECK: bb.1:
	; CHECK: RET_ReallyLR			; CHECK: RET_ReallyLR
	bb.0:			bb.0:
	liveins: $w0			liveins: $w0
	successors: %bb.0, %bb.1			successors: %bb.0, %bb.1
	%reg:gpr(s32) = COPY $w0			%reg:gpr(s32) = COPY $w0
	G_BRCOND %reg, %bb.1			G_BRCOND %reg, %bb.1
	▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[GlobalISel] Fix the error transformation of BRCOND to BCC.ClosedPublic

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Diff 539991

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir

[GlobalISel] Fix the error transformation of BRCOND to BCC.
ClosedPublic