[AArch64] Add ARMv8.2-A persistent memory instruction

[olista01]

Summary

ARMv8.2-A adds the "dc cvap" instruction, which is a system instruction
that cleans caches to the point of persistence (for systems that have
persistent memory). It is a required part of ARMv8.2-A, so no additional
subtarget features are required.

[t.p.northover]

This looks fine to me.

Tim.

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

if (!Op.compare_lower("zva")) {
       // SYS #3, C7, C11, #1
       SYS_ALIAS(3, 7, 11, 1);
     } else if (!Op.compare_lower("civac")) {
       // SYS #3, C7, C14, #1
       SYS_ALIAS(3, 7, 14, 1);
     } else if (!Op.compare_lower("cisw")) {
       // SYS #0, C7, C14, #2
       SYS_ALIAS(0, 7, 14, 2);
+    } else if (!Op.compare_lower("cvap")) {
+      if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
+        // SYS #3, C7, C12, #1
+        SYS_ALIAS(3, 7, 12, 1);
+      } else {
+        return TokError("DC CVAP requires ARMv8.2a");
+      }
     } else {
       return TokError("invalid operand for DC instruction");
     }
   } else if (Mnemonic == "at") {
     if (!Op.compare_lower("s1e1r")) {
       // SYS #0, C7, C8, #0
       SYS_ALIAS(0, 7, 8, 0);
     } else if (!Op.compare_lower("s1e2r")) {

lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h

virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
                                        raw_ostream &O);
   virtual StringRef getRegName(unsigned RegNo) const {
     return getRegisterName(RegNo);
   }
   static const char *getRegisterName(unsigned RegNo,
                                      unsigned AltIdx = AArch64::NoRegAltName);
 
 protected:
-  bool printSysAlias(const MCInst *MI, raw_ostream &O);
+  bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
+                     raw_ostream &O);
   // Operand printers
   void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                     raw_ostream &O);
   void printHexImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &O);
   void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
                            raw_ostream &O);
   template <int Amount>

lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp

 void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
                                    StringRef Annot,
                                    const MCSubtargetInfo &STI) {
   // Check for special encodings and print the canonical alias instead.
 
   unsigned Opcode = MI->getOpcode();
 
   if (Opcode == AArch64::SYSxt)
-    if (printSysAlias(MI, O)) {
+    if (printSysAlias(MI, STI, O)) {
       printAnnotation(O, Annot);
       return;
     }
 
   // SBFM/UBFM should print to a nicer aliased form if possible.
   if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
       Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
     const MCOperand &Op0 = MI->getOperand(0);
if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
 
     printAnnotation(O, Annot);
     return;
   }
 
   AArch64InstPrinter::printInst(MI, O, Annot, STI);
 }
 
-bool AArch64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
+bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
+                                       const MCSubtargetInfo &STI,
+                                       raw_ostream &O) {
 #ifndef NDEBUG
   unsigned Opcode = MI->getOpcode();
   assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
 #endif
 
   const char *Asm = nullptr;
   const MCOperand &Op1 = MI->getOperand(0);
   const MCOperand &Cn = MI->getOperand(1);
case 10:
         Asm = "dc\tcvac";
       else if (Op1Val == 0 && Op2Val == 2)
         Asm = "dc\tcsw";
       break;
     case 11:
       if (Op1Val == 3 && Op2Val == 1)
         Asm = "dc\tcvau";
       break;
+    case 12:
+      if (Op1Val == 3 && Op2Val == 1 &&
+          (STI.getFeatureBits()[AArch64::HasV8_2aOps]))
+        Asm = "dc\tcvap";
+      break;
     case 14:
       if (Op1Val == 3 && Op2Val == 1)
         Asm = "dc\tcivac";
       else if (Op1Val == 0 && Op2Val == 2)
         Asm = "dc\tcisw";
       break;
 
     // AT aliases

test/MC/AArch64/armv8.2a-persistent-memory.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+  dc cvap, x7
+// CHECK: dc cvap, x7   // encoding: [0x27,0x7c,0x0b,0xd5]
+// ERROR: error: DC CVAP requires ARMv8.2a

test/MC/Disassembler/AArch64/armv8.2a-persistent-memory.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s | FileCheck --check-prefix=NO_V82 %s
+
+[0x27,0x7c,0x0b,0xd5]
+# CHECK: dc cvap, x7
+# NO_V82: sys #3, c7, c12, #1, x7