[TargetLowering] Stop passing an ISD::CondCode to isOperationLegalOrCustom.

[craig.topper]

Summary

ISD::CondCode is a separate num space from opcodes. isOperationLegalOrCustom
should take an opcode.

[barannikov88]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

6706

Should this check SETCCVT instead? SETEQ is created below with this type.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
   // That fold is only valid for positive divisors. Which effectively means,
   // it is invalid for INT_MIN divisors. So if we have such a lane,
   // we must fix-up results for said lanes.
   assert(VT.isVector() && "Can/should only get here for vectors.");
 
   // NOTE: we avoid letting illegal types through even if we're before legalize
   // ops – legalization has a hard time producing good code for the code that
   // follows.
-  if (!isOperationLegalOrCustom(ISD::SETEQ, VT) ||
+  if (!isOperationLegalOrCustom(ISD::SETCC, VT) ||
       !isOperationLegalOrCustom(ISD::AND, VT) ||
-      !isOperationLegalOrCustom(Cond, VT) ||
+      !isCondCodeLegalOrCustom(Cond, VT.getSimpleVT()) ||
       !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT))
     return SDValue();
 
   Created.push_back(Fold.getNode());
 
   SDValue IntMin = DAG.getConstant(
       APInt::getSignedMinValue(SVT.getScalarSizeInBits()), DL, VT);
   SDValue IntMax = DAG.getConstant(