[msan] Improve handling of Intrinsic::is_fpclass after c55fffe

[vitalybuka]

Summary

c55fffe replaced fcmp with fpclass.

declare i1 @llvm.is.fpclass(<fptype> <op>, i32 <test>)
declare <N x i1> @llvm.is.fpclass(<vector-fptype> <op>, i32 <test>)

Perfect fix will require checking bits of <op> corresponding to <test>
argument. For now just propagate shadow without reporting before
intrinsic. Still existing handling of fcmp is also simple OR, so it's
not making it worse.

[vitalybuka]

llvm/test/Instrumentation/MemorySanitizer/create-class-from-logic-fcmp.ll

4

Maybe better to move into original create-class-from-logic-fcmp.ll ?

[vitalybuka]

fix condition

[vitalybuka]

simplify test

[vitalybuka]

rebase

llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp

void handleAbsIntrinsic(IntrinsicInst &I) {
     assert(I.getArgOperand(0)->getType() == I.getType());
 
     // FIXME: Handle is_int_min_poison.
     IRBuilder<> IRB(&I);
     setShadow(&I, getShadow(&I, 0));
     setOrigin(&I, getOrigin(&I, 0));
   }
 
+  void handleIsFpClass(IntrinsicInst &I) {
+    IRBuilder<> IRB(&I);
+    Value *Shadow = getShadow(&I, 0);
+    setShadow(&I, IRB.CreateICmpNE(Shadow, getCleanShadow(Shadow)));
+    setOrigin(&I, getOrigin(&I, 0));
+  }
+
   void visitIntrinsicInst(IntrinsicInst &I) {
     switch (I.getIntrinsicID()) {
     case Intrinsic::abs:
       handleAbsIntrinsic(I);
       break;
+    case Intrinsic::is_fpclass:
+      handleIsFpClass(I);
+      break;
     case Intrinsic::lifetime_start:
       handleLifetimeStart(I);
       break;
     case Intrinsic::launder_invariant_group:
     case Intrinsic::strip_invariant_group:
       handleInvariantGroup(I);
       break;
     case Intrinsic::bswap:

llvm/test/Instrumentation/MemorySanitizer/create-class-from-logic-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -passes=instcombine < %s | FileCheck %s
 ; RUN: opt -S -passes=msan < %s | FileCheck %s --check-prefixes=MSAN
 ; RUN: opt -S -passes='module(instcombine),msan' < %s | FileCheck %s --check-prefixes=IC_MSAN
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; Test and/or of fcmps that could be folded to llvm.is.fpclass
 
 ; --------------------------------------------------------------------
 ; Base pattern, !isfinite(x) || x == 0.0

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @not_isfinite_or_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0:![0-9]+]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp ueq half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %x, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPINF]], [[CMPZERO]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_commute_or(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp ueq half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %x, 0xH0000
   %class = or i1 %cmpinf, %cmpzero
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_negzero(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp ueq half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %x, -0.0
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @not_isfinite_or_fabs_oeq_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp ueq half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %fabs, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or <2 x i1> [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store <2 x i1> [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret <2 x i1> [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @not_isfinite_or_zero_v2f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i16> [[TMP1]], zeroinitializer
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store <2 x i1> [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret <2 x i1> [[CLASS]]
 ;
   %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
   %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
   %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
   %class = or <2 x i1> %cmpzero, %cmpinf
   ret <2 x i1> %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or <2 x i1> [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store <2 x i1> [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret <2 x i1> [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @not_isfinite_or_zero_v2f16_pos0_neg0_vec(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i16> [[TMP1]], zeroinitializer
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store <2 x i1> [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret <2 x i1> [[CLASS]]
 ;
   %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
   %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
   %cmpzero = fcmp oeq <2 x half> %x, <half 0.0, half -0.0>
   %class = or <2 x i1> %cmpzero, %cmpinf
   ret <2 x i1> %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or <2 x i1> [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPINF]], [[CMPZERO]]
 ; MSAN-NEXT:    store <2 x i1> [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret <2 x i1> [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @not_isfinite_or_zero_v2f16_commute_or(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i16> [[TMP1]], zeroinitializer
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store <2 x i1> [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret <2 x i1> [[CLASS]]
 ;
   %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
   %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
   %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
   %class = or <2 x i1> %cmpinf, %cmpzero
   ret <2 x i1> %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @oeq_isinf_or_oeq_zero(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %x, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @ueq_inf_or_oeq_zero(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp ueq half %x, 0xH7C00
   %cmpzero = fcmp oeq half %x, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @oeq_isinf_or_fabs_oeq_zero(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %fabs, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @ueq_0_or_oeq_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp ueq half %fabs, 0xH0000
   %cmpzero = fcmp oeq half %x, 0xH7C00
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @ueq_inf_or_ueq_zero(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp ueq half %fabs, 0xH7C00
   %cmpzero = fcmp ueq half %x, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
 ; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
 ; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
 ; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
 ; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]]
+; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0:![0-9]+]]
 ; IC_MSAN:       4:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
+; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]]
 ; IC_MSAN-NEXT:    unreachable
 ; IC_MSAN:       5:
 ; IC_MSAN-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
 ; IC_MSAN-NEXT:    [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080
 ; IC_MSAN-NEXT:    [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
 ; IC_MSAN-NEXT:    store i1 [[TMP3]], ptr [[TMP8]], align 1
 ; IC_MSAN-NEXT:    store i1 [[CMPINF]], ptr [[PTR]], align 1
 ; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @olt_0_or_fabs_ueq_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp ueq half %fabs, 0xH7C00
   %cmpzero = fcmp olt half %x, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @oeq_0_or_fabs_ult_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 507)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp ult half %fabs, 0xH7C00
   %cmpzero = fcmp oeq half %x, 0xH0000
   %class = or i1 %cmpzero, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
 ; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp one half %fabs, 0xH7C00
   %cmpzero = fcmp une half %x, 0xH0000
   %not.class = and i1 %cmpzero, %cmpinf
   ret i1 %not.class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPINF]], [[CMPZERO]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
 ; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_commute_and(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp one half %fabs, 0xH7C00
   %cmpzero = fcmp une half %x, 0xH0000
   %not.class = and i1 %cmpinf, %cmpzero
   ret i1 %not.class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
 ; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_negzero(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp one half %fabs, 0xH7C00
   %cmpzero = fcmp une half %x, -0.0
   %not.class = and i1 %cmpzero, %cmpinf
   ret i1 %not.class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or <2 x i1> [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and <2 x i1> [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store <2 x i1> [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret <2 x i1> [[NOT_CLASS]]
 ;
 ; IC_MSAN-LABEL: @negated_isfinite_or_zero_v2f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i16> [[TMP1]], zeroinitializer
 ; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store <2 x i1> [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret <2 x i1> [[NOT_CLASS]]
 ;
   %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
   %cmpinf = fcmp one <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
   %cmpzero = fcmp une <2 x half> %x, zeroinitializer
   %not.class = and <2 x i1> %cmpzero, %cmpinf
   ret <2 x i1> %not.class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or <2 x i1> [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and <2 x i1> [[CMPINF]], [[CMPZERO]]
 ; MSAN-NEXT:    store <2 x i1> [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret <2 x i1> [[NOT_CLASS]]
 ;
 ; IC_MSAN-LABEL: @negated_isfinite_or_zero_v2f16_comumte(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i16> [[TMP1]], zeroinitializer
 ; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store <2 x i1> [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret <2 x i1> [[NOT_CLASS]]
 ;
   %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
   %cmpinf = fcmp one <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
   %cmpzero = fcmp une <2 x half> %x, zeroinitializer
   %not.class = and <2 x i1> %cmpinf, %cmpzero
   ret <2 x i1> %not.class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
 ; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_not_une_zero(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp one half %fabs, 0xH7C00
   %cmpzero = fcmp one half %x, 0xH0000
   %not.class = and i1 %cmpzero, %cmpinf
   ret i1 %not.class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
 ; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_swapped_constants(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 412)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpzero = fcmp one half %fabs, 0xH0000
   %cmpinf = fcmp une half %x, 0xH7C00
   %not.class = and i1 %cmpzero, %cmpinf
   ret i1 %not.class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
 ; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp une half %fabs, 0xH7C00
   %cmpzero = fcmp une half %x, 0xH0000
   %not.class = and i1 %cmpzero, %cmpinf
   ret i1 %not.class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[AND]]
 ;
 ; IC_MSAN-LABEL: @fcmp_one_0_and_fcmp_une_fabs_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[AND]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpzero = fcmp one half %x, 0.0
   %cmpinf = fcmp une half %fabs, 0xH7C00
   %and = and i1 %cmpzero, %cmpinf
   ret i1 %and
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[AND]]
 ;
 ; IC_MSAN-LABEL: @fcmp_une_0_and_fcmp_une_fabs_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[AND]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpzero = fcmp une half %x, 0.0
   %cmpinf = fcmp une half %fabs, 0xH7C00
   %and = and i1 %cmpzero, %cmpinf
   ret i1 %and
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @issubnormal_or_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
   %class = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @olt_smallest_normal_or_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 764)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %x, 0xH0400 ; missing fabs
   %class = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[NOT:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[NOT]]
 ;
 ; IC_MSAN-LABEL: @not_issubnormal_or_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[NOT:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 267)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[NOT]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp une half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
   %not = and i1 %cmp.smallest.normal, %cmpinf
   ret i1 %not
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @issubnormal_uge_or_inf(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
   %class = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[OR]]
 ;
 ; IC_MSAN-LABEL: @issubnormal_or_finite_olt(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 504)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[OR]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp olt half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
   %or = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %or
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[OR]]
 ;
 ; IC_MSAN-LABEL: @issubnormal_or_finite_uge(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 759)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[OR]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp uge half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
   %or = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %or
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[AND]]
 ;
 ; IC_MSAN-LABEL: @issubnormal_and_finite_olt(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[AND]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp olt half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
   %and = and i1 %cmp.smallest.normal, %cmpinf
   ret i1 %and
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[OR]]
 ;
 ; IC_MSAN-LABEL: @fcmp_fabs_uge_inf_or_fabs_uge_smallest_norm(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[OR]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp uge half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
   %or = or i1 %cmp.smallest.normal, %cmpinf
   ret i1 %or
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[OR:%.*]] = or i1 [[UNO]], [[IS_FINITE]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[OR]]
 ;
 ; IC_MSAN-LABEL: @is_finite_or_uno(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[OR]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %is.finite = fcmp ueq half %fabs, 0xH7C00
   %uno = fcmp uno half %x, %x
   %or = or i1 %uno, %is.finite
   ret i1 %or
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPINF]], [[UNO]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @oeq_isinf_or_uno(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %uno = fcmp uno half %x, 0xH0000
   %class = or i1 %cmpinf, %uno
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
 ; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMPINF]], [[UNO]]
 ; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[AND]]
 ;
 ; IC_MSAN-LABEL: @oeq_isinf_and_ord(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[AND]]
 ;
   %fabs = call half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp oeq half %fabs, 0xH7C00
   %uno = fcmp ord half %x, 0xH0000
   %and = and i1 %cmpinf, %uno
   ret i1 %and
 }

 ; MSAN-NEXT:    [[_MSPROP_SELECT:%.*]] = select i1 [[TMP2]], i1 [[TMP7]], i1 [[TMP4]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = select i1 [[CMPINF]], i1 true, i1 [[CMP_SMALLEST_NORMAL]]
 ; MSAN-NEXT:    store i1 [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @issubnormal_or_inf_nnan_logical_select(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call nnan half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp nnan oeq half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp nnan olt half %fabs, 0xH0400
   %class = select i1 %cmpinf, i1 true, i1 %cmp.smallest.normal
   ret i1 %class
 }

 ; MSAN-NEXT:    [[_MSPROP_SELECT:%.*]] = select i1 [[TMP2]], i1 [[TMP7]], i1 [[TMP4]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = select i1 [[CMPINF]], i1 [[CMP_SMALLEST_NORMAL]], i1 false
 ; MSAN-NEXT:    store i1 [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @issubnormal_and_ninf_nnan_logical_select(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %fabs = call nnan half @llvm.fabs.f16(half %x)
   %cmpinf = fcmp nnan one half %fabs, 0xH7C00
   %cmp.smallest.normal = fcmp nnan olt half %fabs, 0xH0400
   %class = select i1 %cmpinf, i1 %cmp.smallest.normal, i1 false
   ret i1 %class
 }

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 999)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp ueq half %x, 0xHFC00
   %cmp.oge.zero = fcmp oge half %x, 0xH0000
   %class = or i1 %cmp.oge.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 996)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp oeq half %x, 0xHFC00
   %cmp.oge.zero = fcmp oge half %x, 0xH0000
   %class = or i1 %cmp.oge.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 900)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp oeq half %x, 0xHFC00
   %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
   %class = or i1 %cmp.ogt.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 903)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp ueq half %x, 0xHFC00
   %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
   %class = or i1 %cmp.ogt.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 903)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp oeq half %x, 0xHFC00
   %cmp.ugt.zero = fcmp ugt half %x, 0xH0000
   %class = or i1 %cmp.ugt.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 639)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp ueq half %x, 0xH7C00
   %cmp.ole.zero = fcmp ole half %x, 0xH0000
   %class = or i1 %cmp.ole.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 636)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp oeq half %x, 0xH7C00
   %cmp.ole.zero = fcmp ole half %x, 0xH0000
   %class = or i1 %cmp.ole.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 540)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp oeq half %x, 0xH7C00
   %cmp.olt.zero = fcmp olt half %x, 0xH0000
   %class = or i1 %cmp.olt.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp ueq half %x, 0xH7C00
   %cmp.ult.zero = fcmp ult half %x, 0xH0000
   %class = or i1 %cmp.ult.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp oeq half %x, 0xH7C00
   %cmp.ult.zero = fcmp ult half %x, 0xH0000
   %class = or i1 %cmp.ult.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 639)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp ueq half %x, 0xH7C00
   %cmp.ule.zero = fcmp ule half %x, 0xH0000
   %class = or i1 %cmp.ule.zero, %cmpinf
   ret i1 %class
 }
 

 ; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
 ; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
 ; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
 ; MSAN-NEXT:    ret i1 [[CLASS]]
 ;
 ; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_olt_zero_f16(
 ; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
+; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; IC_MSAN-NEXT:    ret i1 [[CLASS]]
 ;
   %cmpinf = fcmp ueq half %x, 0xH7C00
   %cmp.olt.zero = fcmp olt half %x, 0xH0000
   %class = or i1 %cmp.olt.zero, %cmpinf
   ret i1 %class
 }
 
 declare half @llvm.fabs.f16(half) #0
 declare half @llvm.canonicalize.f16(half) #0
 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #0
 
 attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
 attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" }
 attributes #2 = { "denormal-fp-math"="ieee,dynamic" }