Assert statements in Verilog can optionally have an else part. We
handle them like for if statements, except that an if statement in
the else part of an assert statement doesn't get merged with the
else keyword. Like this:
assert (x) $info(); else if (y) $info(); else if (z) $info(); else $info();
foreach and repeat are now handled like for or while loops.
We used the type TT_ConditionLParen to mark the condition part so
they are handled in the same way as the condition part of an if
statement. When the code being formatted is not in Verilog, it is
only set for if statements, not loops. It's because loop conditions
are currently handled slightly differently, and existing behavior is
not supposed to change. We formatted all files ending in .cpp and
.h in the repository with and without this change. It showed that
setting the type for if statements doesn't change existing behavior.
And we noticed that we forgot to make the program print the list of
tokens when the number is not correct in TokenAnnotatorTest. It's
fixed now.
Unrelated, I'd prefer it as a single commit.