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[clang-format] Handle Verilog assertions and loops
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Authored by sstwcw on Apr 9 2023, 4:34 PM.

Details

Summary

Assert statements in Verilog can optionally have an else part. We
handle them like for if statements, except that an if statement in
the else part of an assert statement doesn't get merged with the
else keyword. Like this:

assert (x)
  $info();
else
  if (y)
    $info();
  else if (z)
    $info();
  else
    $info();

foreach and repeat are now handled like for or while loops.

We used the type TT_ConditionLParen to mark the condition part so
they are handled in the same way as the condition part of an if
statement. When the code being formatted is not in Verilog, it is
only set for if statements, not loops. It's because loop conditions
are currently handled slightly differently, and existing behavior is
not supposed to change. We formatted all files ending in .cpp and
.h in the repository with and without this change. It showed that
setting the type for if statements doesn't change existing behavior.

And we noticed that we forgot to make the program print the list of
tokens when the number is not correct in TokenAnnotatorTest. It's
fixed now.

Diff Detail

Event Timeline

sstwcw created this revision.Apr 9 2023, 4:34 PM
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sstwcw requested review of this revision.Apr 9 2023, 4:34 PM
HazardyKnusperkeks added inline comments.
clang/unittests/Format/TokenAnnotatorTest.cpp
844

Unrelated, I'd prefer it as a single commit.

This revision is now accepted and ready to land.Apr 10 2023, 12:04 PM
sstwcw added inline comments.Apr 11 2023, 7:17 AM
clang/unittests/Format/TokenAnnotatorTest.cpp
844

How should I name the separate commit?

clang/unittests/Format/TokenAnnotatorTest.cpp
844

I'd go with
[clang-format][NFC] Output tokens on test assert
or similar.

This revision was landed with ongoing or failed builds.Apr 16 2023, 3:00 PM
This revision was automatically updated to reflect the committed changes.