[InstCombine] Sink bin op into select if first or second value is simplified to constant

[nikic]

Can you please regenerate checks for these files and rebase? There are lots of spurious naming diffs that make it hard to see what actually changed.

[xbolva00]

Do not perform this optimization with bools as there are infinite instcombine loops.

[xbolva00]

In D147645#4246621, @nikic wrote:

Can you please regenerate checks for these files and rebase? There are lots of spurious naming diffs that make it hard to see what actually changed.

Yes sure

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

924

Somehow getting infinite loops here is Xor is allowed. GDB points to foldSelectOfBools..

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

Value *InstCombinerImpl::SimplifySelectsFeedingBinaryOp(BinaryOperator &I,
   BuilderTy::FastMathFlagGuard Guard(Builder);
   if (isa<FPMathOperator>(&I)) {
     FMF = I.getFastMathFlags();
     Builder.setFastMathFlags(FMF);
   }
 
   Instruction::BinaryOps Opcode = I.getOpcode();
   SimplifyQuery Q = SQ.getWithInstruction(&I);
-
+  SelectInst *InnerSelect = nullptr;
   Value *Cond, *True = nullptr, *False = nullptr;
 
   // Special-case for add/negate combination. Replace the zero in the negation
   // with the trailing add operand:
   // (Cond ? TVal : -N) + Z --> Cond ? True : (Z - N)
   // (Cond ? -N : FVal) + Z --> Cond ? (Z - N) : False
   auto foldAddNegate = [&](Value *TVal, Value *FVal, Value *Z) -> Value * {
     // We need an 'add' and exactly 1 arm of the select to have been simplified.
if (LHSIsSelect && RHSIsSelect && A == D) {
     }
   } else if (LHSIsSelect && LHS->hasOneUse()) {
     // (A ? B : C) op Y -> A ? (B op Y) : (C op Y)
     Cond = A;
     True = simplifyBinOp(Opcode, B, RHS, FMF, Q);
     False = simplifyBinOp(Opcode, C, RHS, FMF, Q);
     if (Value *NewSel = foldAddNegate(B, C, RHS))
       return NewSel;
+    if (I.getOpcode() == BinaryOperator::Xor) return nullptr;
+    if (!True && isa_and_nonnull<Constant>(False))
+      True = Builder.CreateBinOp(Opcode, B, RHS);
+    else if (!False && isa_and_nonnull<Constant>(True))
+      False = Builder.CreateBinOp(Opcode, C, RHS);
+
+    InnerSelect = cast<SelectInst>(LHS);
   } else if (RHSIsSelect && RHS->hasOneUse()) {
     // X op (D ? E : F) -> D ? (X op E) : (X op F)
     Cond = D;
     True = simplifyBinOp(Opcode, LHS, E, FMF, Q);
     False = simplifyBinOp(Opcode, LHS, F, FMF, Q);
     if (Value *NewSel = foldAddNegate(E, F, LHS))
       return NewSel;
+
+    if (!True && isa_and_nonnull<Constant>(False))
+      True = Builder.CreateBinOp(Opcode, LHS, E);
+    else if (!False && isa_and_nonnull<Constant>(True))
+      False = Builder.CreateBinOp(Opcode, LHS, F);
+
+    InnerSelect = cast<SelectInst>(RHS);
   }
 
   if (!True || !False)
     return nullptr;
 
-  Value *SI = Builder.CreateSelect(Cond, True, False);
+  auto *SI = cast<SelectInst>(Builder.CreateSelect(Cond, True, False));
   SI->takeName(&I);
+  if (InnerSelect)
+    SI->copyMetadata(*InnerSelect);
   return SI;
 }
 
 /// Freely adapt every user of V as-if V was changed to !V.
 /// WARNING: only if canFreelyInvertAllUsersOf() said this can be done.
 void InstCombinerImpl::freelyInvertAllUsersOf(Value *I, Value *IgnoredUser) {
   for (User *U : make_early_inc_range(I->users())) {
     if (U == IgnoredUser)

llvm/test/Transforms/InstCombine/and-or-icmps.ll

;
   %B = icmp ult i32 %X, 10
   %C = select i1 %A, i1 true, i1 %B
   ret i1 %C
 }
 
 define i1 @PR2330(i32 %a, i32 %b) {
 ; CHECK-LABEL: @PR2330(
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 8
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult i32 [[TMP1]], 8
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ult i32 %a, 8
   %cmp2 = icmp ult i32 %b, 8
   %and = and i1 %cmp2, %cmp1
   ret i1 %and
 }
 
 define i1 @PR2330_logical(i32 %a, i32 %b) {

 
 ; if LHSC and RHSC differ only by one bit:
 ; (X == C1 || X == C2) -> (X & ~(C1 ^ C2)) == C1 (C1 has 1 less set bit)
 ; PR14708: https://bugs.llvm.org/show_bug.cgi?id=14708
 
 define i1 @or_eq_with_one_bit_diff_constants1(i32 %x) {
 ; CHECK-LABEL: @or_eq_with_one_bit_diff_constants1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 50
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp eq i32 [[TMP1]], 50
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i32 %x, 50
   %cmp2 = icmp eq i32 %x, 51
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @or_eq_with_one_bit_diff_constants1_logical(i32 %x) {
 ; CHECK-LABEL: @or_eq_with_one_bit_diff_constants1_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 50
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp eq i32 [[TMP1]], 50
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i32 %x, 50
   %cmp2 = icmp eq i32 %x, 51
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 ; (X != C1 && X != C2) -> (X & ~(C1 ^ C2)) != C1 (C1 has 1 less set bit)
 
 define i1 @and_ne_with_one_bit_diff_constants1(i32 %x) {
 ; CHECK-LABEL: @and_ne_with_one_bit_diff_constants1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -52
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult i32 [[TMP1]], -2
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i32 %x, 51
   %cmp2 = icmp ne i32 %x, 50
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @and_ne_with_one_bit_diff_constants1_logical(i32 %x) {
 ; CHECK-LABEL: @and_ne_with_one_bit_diff_constants1_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -52
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult i32 [[TMP1]], -2
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i32 %x, 51
   %cmp2 = icmp ne i32 %x, 50
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }
 
 ; The constants are not necessarily off-by-one, just off-by-one-bit.
 
 define i1 @or_eq_with_one_bit_diff_constants2(i32 %x) {
 ; CHECK-LABEL: @or_eq_with_one_bit_diff_constants2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -33
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 65
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp eq i32 [[TMP1]], 65
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i32 %x, 97
   %cmp2 = icmp eq i32 %x, 65
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @or_eq_with_one_bit_diff_constants2_logical(i32 %x) {
 ; CHECK-LABEL: @or_eq_with_one_bit_diff_constants2_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -33
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 65
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp eq i32 [[TMP1]], 65
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i32 %x, 97
   %cmp2 = icmp eq i32 %x, 65
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 define i1 @and_ne_with_one_bit_diff_constants2(i19 %x) {
 ; CHECK-LABEL: @and_ne_with_one_bit_diff_constants2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i19 [[X:%.*]], -129
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i19 [[TMP1]], 65
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ne i19 [[TMP1]], 65
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i19 %x, 65
   %cmp2 = icmp ne i19 %x, 193
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @and_ne_with_one_bit_diff_constants2_logical(i19 %x) {
 ; CHECK-LABEL: @and_ne_with_one_bit_diff_constants2_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i19 [[X:%.*]], -129
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i19 [[TMP1]], 65
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ne i19 [[TMP1]], 65
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i19 %x, 65
   %cmp2 = icmp ne i19 %x, 193
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }
 
 ; Make sure the constants are treated as unsigned when comparing them.
 
 define i1 @or_eq_with_one_bit_diff_constants3(i8 %x) {
 ; CHECK-LABEL: @or_eq_with_one_bit_diff_constants3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], 127
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 126
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp eq i8 [[TMP1]], 126
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i8 %x, 254
   %cmp2 = icmp eq i8 %x, 126
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @or_eq_with_one_bit_diff_constants3_logical(i8 %x) {
 ; CHECK-LABEL: @or_eq_with_one_bit_diff_constants3_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], 127
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 126
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp eq i8 [[TMP1]], 126
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i8 %x, 254
   %cmp2 = icmp eq i8 %x, 126
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 define i1 @and_ne_with_one_bit_diff_constants3(i8 %x) {
 ; CHECK-LABEL: @and_ne_with_one_bit_diff_constants3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], 127
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 65
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ne i8 [[TMP1]], 65
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i8 %x, 65
   %cmp2 = icmp ne i8 %x, 193
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @and_ne_with_one_bit_diff_constants3_logical(i8 %x) {
 ; CHECK-LABEL: @and_ne_with_one_bit_diff_constants3_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], 127
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i8 [[TMP1]], 65
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ne i8 [[TMP1]], 65
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i8 %x, 65
   %cmp2 = icmp ne i8 %x, 193
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }
 
 ; Use an 'add' to eliminate an icmp if the constants are off-by-one (not off-by-one-bit).
 ; (X == 13 | X == 14) -> X-13 <u 2
 
 define i1 @or_eq_with_diff_one(i8 %x) {
 ; CHECK-LABEL: @or_eq_with_diff_one(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -13
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp ult i8 [[TMP1]], 2
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i8 %x, 13
   %cmp2 = icmp eq i8 %x, 14
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @or_eq_with_diff_one_logical(i8 %x) {
 ; CHECK-LABEL: @or_eq_with_diff_one_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -13
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp ult i8 [[TMP1]], 2
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i8 %x, 13
   %cmp2 = icmp eq i8 %x, 14
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 ; (X != 40 | X != 39) -> X-39 >u 1
 
 define i1 @and_ne_with_diff_one(i32 %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -41
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult i32 [[TMP1]], -2
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i32 %x, 40
   %cmp2 = icmp ne i32 %x, 39
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @and_ne_with_diff_one_logical(i32 %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -41
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult i32 [[TMP1]], -2
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i32 %x, 40
   %cmp2 = icmp ne i32 %x, 39
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }
 
 ; Make sure the constants are treated as signed when comparing them.
 ; PR32524: https://bugs.llvm.org/show_bug.cgi?id=32524
 
 define i1 @or_eq_with_diff_one_signed(i32 %x) {
 ; CHECK-LABEL: @or_eq_with_diff_one_signed(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp ult i32 [[TMP1]], 2
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i32 %x, 0
   %cmp2 = icmp eq i32 %x, -1
   %or = or i1 %cmp1, %cmp2
   ret i1 %or
 }
 
 define i1 @or_eq_with_diff_one_signed_logical(i32 %x) {
 ; CHECK-LABEL: @or_eq_with_diff_one_signed_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp ult i32 [[TMP1]], 2
+; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %cmp1 = icmp eq i32 %x, 0
   %cmp2 = icmp eq i32 %x, -1
   %or = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %or
 }
 
 define i1 @and_ne_with_diff_one_signed(i64 %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one_signed(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i64 [[TMP1]], -2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult i64 [[TMP1]], -2
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i64 %x, -1
   %cmp2 = icmp ne i64 %x, 0
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @and_ne_with_diff_one_signed_logical(i64 %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one_signed_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i64 [[TMP1]], -2
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult i64 [[TMP1]], -2
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp ne i64 %x, -1
   %cmp2 = icmp ne i64 %x, 0
   %and = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %and
 }
 
 ; Vectors with splat constants get the same folds.
 
 define <2 x i1> @or_eq_with_one_bit_diff_constants2_splatvec(<2 x i32> %x) {
 ; CHECK-LABEL: @or_eq_with_one_bit_diff_constants2_splatvec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 -33, i32 -33>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 65, i32 65>
-; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
+; CHECK-NEXT:    [[OR:%.*]] = icmp eq <2 x i32> [[TMP1]], <i32 65, i32 65>
+; CHECK-NEXT:    ret <2 x i1> [[OR]]
 ;
   %cmp1 = icmp eq <2 x i32> %x, <i32 97, i32 97>
   %cmp2 = icmp eq <2 x i32> %x, <i32 65, i32 65>
   %or = or <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %or
 }
 
 define <2 x i1> @and_ne_with_diff_one_splatvec(<2 x i32> %x) {
 ; CHECK-LABEL: @and_ne_with_diff_one_splatvec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 -41, i32 -41>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 -2, i32 -2>
-; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 -2, i32 -2>
+; CHECK-NEXT:    ret <2 x i1> [[AND]]
 ;
   %cmp1 = icmp ne <2 x i32> %x, <i32 40, i32 40>
   %cmp2 = icmp ne <2 x i32> %x, <i32 39, i32 39>
   %and = and <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %and
 }
 
 ; This is a fuzzer-generated test that would assert because
;
   store i16 %B33, ptr undef
   store i1 %C18, ptr undef
   store ptr %G26, ptr undef
   ret void
 }
 
 define i1 @PR42691_1(i32 %x) {
 ; CHECK-LABEL: @PR42691_1(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], 2147483646
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ugt i32 [[X:%.*]], 2147483646
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp slt i32 %x, 0
   %c2 = icmp eq i32 %x, 2147483647
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_1_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_1_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], 2147483646
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ugt i32 [[X:%.*]], 2147483646
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp slt i32 %x, 0
   %c2 = icmp eq i32 %x, 2147483647
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_2(i32 %x) {
 ; CHECK-LABEL: @PR42691_2(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -2
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = icmp sgt i32 [[X:%.*]], -2
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp ult i32 %x, 2147483648
   %c2 = icmp eq i32 %x, 4294967295
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_2_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_2_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], -2
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = icmp sgt i32 [[X:%.*]], -2
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp ult i32 %x, 2147483648
   %c2 = icmp eq i32 %x, 4294967295
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_3(i32 %x) {
 ; CHECK-LABEL: @PR42691_3(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], -2147483647
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[X:%.*]], -2147483647
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp sge i32 %x, 0
   %c2 = icmp eq i32 %x, -2147483648
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_3_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_3_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], -2147483647
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[X:%.*]], -2147483647
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp sge i32 %x, 0
   %c2 = icmp eq i32 %x, -2147483648
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_4(i32 %x) {
 ; CHECK-LABEL: @PR42691_4(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp uge i32 %x, 2147483648
   %c2 = icmp eq i32 %x, 0
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_4_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_4_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = icmp slt i32 [[X:%.*]], 1
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp uge i32 %x, 2147483648
   %c2 = icmp eq i32 %x, 0
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_5(i32 %x) {
 ; CHECK-LABEL: @PR42691_5(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -2147483647
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp slt i32 %x, 1
   %c2 = icmp eq i32 %x, 2147483647
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_5_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_5_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -2147483647
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp slt i32 %x, 1
   %c2 = icmp eq i32 %x, 2147483647
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_6(i32 %x) {
 ; CHECK-LABEL: @PR42691_6(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp ult i32 %x, 2147483649
   %c2 = icmp eq i32 %x, 4294967295
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_6_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_6_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483646
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483646
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp ult i32 %x, 2147483649
   %c2 = icmp eq i32 %x, 4294967295
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_7(i32 %x) {
 ; CHECK-LABEL: @PR42691_7(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp uge i32 %x, 2147483649
   %c2 = icmp eq i32 %x, 0
   %c = or i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_7_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_7_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp uge i32 %x, 2147483649
   %c2 = icmp eq i32 %x, 0
   %c = select i1 %c1, i1 true, i1 %c2
   ret i1 %c
 }
 
 define i1 @PR42691_8(i32 %x) {
 ; CHECK-LABEL: @PR42691_8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483635
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483635
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp slt i32 %x, 14
   %c2 = icmp ne i32 %x, -2147483648
   %c = and i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_8_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_8_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -2147483635
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], -2147483635
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp slt i32 %x, 14
   %c2 = icmp ne i32 %x, -2147483648
   %c = select i1 %c1, i1 %c2, i1 false
   ret i1 %c
 }
 
 define i1 @PR42691_9(i32 %x) {
 ; CHECK-LABEL: @PR42691_9(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2147483633
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], 2147483633
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp sgt i32 %x, 13
   %c2 = icmp ne i32 %x, 2147483647
   %c = and i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_9_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_9_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 2147483633
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], 2147483633
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp sgt i32 %x, 13
   %c2 = icmp ne i32 %x, 2147483647
   %c = select i1 %c1, i1 %c2, i1 false
   ret i1 %c
 }
 
 define i1 @PR42691_10(i32 %x) {
 ; CHECK-LABEL: @PR42691_10(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -15
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], -15
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp ugt i32 %x, 13
   %c2 = icmp ne i32 %x, 4294967295
   %c = and i1 %c1, %c2
   ret i1 %c
 }
 
 define i1 @PR42691_10_logical(i32 %x) {
 ; CHECK-LABEL: @PR42691_10_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -14
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], -15
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C:%.*]] = icmp ult i32 [[TMP1]], -15
+; CHECK-NEXT:    ret i1 [[C]]
 ;
   %c1 = icmp ugt i32 %x, 13
   %c2 = icmp ne i32 %x, 4294967295
   %c = select i1 %c1, i1 %c2, i1 false
   ret i1 %c
 }
 
 define i1 @substitute_constant_and_eq_eq(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_eq(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   %c2 = icmp eq i8 %x, %y
   %r = and i1 %c1, %c2
   ret i1 %r
 }
 
 define i1 @substitute_constant_and_eq_eq_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_eq_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   %c2 = icmp eq i8 %x, %y
   %r = select i1 %c1, i1 %c2, i1 false
   ret i1 %r
 }
 
 define i1 @substitute_constant_and_eq_eq_commute(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_eq_commute(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   %c2 = icmp eq i8 %x, %y
   %r = and i1 %c2, %c1
   ret i1 %r
 }
 
 define i1 @substitute_constant_and_eq_eq_commute_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_eq_commute_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   %c2 = icmp eq i8 %x, %y
   %r = select i1 %c2, i1 %c1, i1 false
   ret i1 %r
 }
 
 define i1 @substitute_constant_and_eq_ugt_swap(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_ugt_swap(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   %c2 = icmp ugt i8 %y, %x
   %r = and i1 %c2, %c1
   ret i1 %r
 }
 
 define i1 @substitute_constant_and_eq_ugt_swap_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_ugt_swap_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   %c2 = icmp ugt i8 %y, %x
   %r = select i1 %c2, i1 %c1, i1 false
   ret i1 %r
 }
 
 define <2 x i1> @substitute_constant_and_eq_ne_vec(<2 x i8> %x, <2 x i8> %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_ne_vec(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 42, i8 97>
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <2 x i8> [[Y:%.*]], <i8 42, i8 97>
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i1> [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i1> [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret <2 x i1> [[R]]
 ;
   %c1 = icmp eq <2 x i8> %x, <i8 42, i8 97>
   %c2 = icmp ne <2 x i8> %x, %y
   %r = and <2 x i1> %c1, %c2
   ret <2 x i1> %r
 }
 
 define <2 x i1> @substitute_constant_and_eq_ne_vec_logical(<2 x i8> %x, <2 x i8> %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_ne_vec_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 42, i8 97>
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <2 x i8> [[Y:%.*]], <i8 42, i8 97>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[C1]], <2 x i1> [[TMP1]], <2 x i1> zeroinitializer
-; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[C1]], <2 x i1> [[TMP1]], <2 x i1> zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[R]]
 ;
   %c1 = icmp eq <2 x i8> %x, <i8 42, i8 97>
   %c2 = icmp ne <2 x i8> %x, %y
   %r = select <2 x i1> %c1, <2 x i1> %c2, <2 x i1> zeroinitializer
   ret <2 x i1> %r
 }
 
 define i1 @substitute_constant_and_eq_sgt_use(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_sgt_use(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    call void @use(i1 [[C1]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   call void @use(i1 %c1)
   %c2 = icmp sgt i8 %x, %y
   %r = and i1 %c2, %c1
   ret i1 %r
 }
 
 define i1 @substitute_constant_and_eq_sgt_use_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_and_eq_sgt_use_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[X:%.*]], 42
 ; CHECK-NEXT:    call void @use(i1 [[C1]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 42
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp eq i8 %x, 42
   call void @use(i1 %c1)
   %c2 = icmp sgt i8 %x, %y
   %r = select i1 %c2, i1 %c1, i1 false
   ret i1 %r
 }
 
;
   %r = select i1 %c2, i1 %c1, i1 false
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_ne_swap_sle(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_or_ne_swap_sle(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp ne i8 %x, 42
   %c2 = icmp sle i8 %y, %x
   %r = or i1 %c1, %c2
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_ne_swap_sle_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_or_ne_swap_sle_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp ne i8 %x, 42
   %c2 = icmp sle i8 %y, %x
   %r = select i1 %c1, i1 true, i1 %c2
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_ne_uge_commute(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_or_ne_uge_commute(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[Y:%.*]], 43
-; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp ne i8 %x, 42
   %c2 = icmp uge i8 %x, %y
   %r = or i1 %c2, %c1
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_ne_uge_commute_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_or_ne_uge_commute_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[Y:%.*]], 43
-; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp ne i8 %x, 42
   %c2 = icmp uge i8 %x, %y
   %r = select i1 %c2, i1 true, i1 %c1
   ret i1 %r
 }
 
 ; Negative test - not safe to substitute vector constant with undef element
;
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_ne_sge_use(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_or_ne_sge_use(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
 ; CHECK-NEXT:    call void @use(i1 [[C1]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp ne i8 %x, 42
   call void @use(i1 %c1)
   %c2 = icmp sge i8 %x, %y
   %r = or i1 %c2, %c1
   ret i1 %r
 }
 
 define i1 @substitute_constant_or_ne_sge_use_logical(i8 %x, i8 %y) {
 ; CHECK-LABEL: @substitute_constant_or_ne_sge_use_logical(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ne i8 [[X:%.*]], 42
 ; CHECK-NEXT:    call void @use(i1 [[C1]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], 43
-; CHECK-NEXT:    [[TMP2:%.*]] = or i1 [[C1]], [[TMP1]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = or i1 [[C1]], [[TMP1]]
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %c1 = icmp ne i8 %x, 42
   call void @use(i1 %c1)
   %c2 = icmp sge i8 %x, %y
   %r = select i1 %c2, i1 true, i1 %c1
   ret i1 %r
 }
 
;
   call void @use(i1 %c2)
   %r = select i1 %c2, i1 true, i1 %c1
   ret i1 %r
 }
 
 define i1 @or_ranges_overlap(i8 %x) {
 ; CHECK-LABEL: @or_ranges_overlap(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -5
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 16
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C7:%.*]] = icmp ult i8 [[TMP1]], 16
+; CHECK-NEXT:    ret i1 [[C7]]
 ;
   %c1 = icmp uge i8 %x, 5
   %c2 = icmp ule i8 %x, 10
   %c3 = and i1 %c1, %c2
   %c4 = icmp uge i8 %x, 10
   %c5 = icmp ule i8 %x, 20
   %c6 = and i1 %c4, %c5
   %c7 = or i1 %c3, %c6
   ret i1 %c7
 }
 
 define i1 @or_ranges_adjacent(i8 %x) {
 ; CHECK-LABEL: @or_ranges_adjacent(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -5
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 16
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C7:%.*]] = icmp ult i8 [[TMP1]], 16
+; CHECK-NEXT:    ret i1 [[C7]]
 ;
   %c1 = icmp uge i8 %x, 5
   %c2 = icmp ule i8 %x, 10
   %c3 = and i1 %c1, %c2
   %c4 = icmp uge i8 %x, 11
   %c5 = icmp ule i8 %x, 20
   %c6 = and i1 %c4, %c5
   %c7 = or i1 %c3, %c6
   ret i1 %c7
 }
 
 define i1 @or_ranges_separated(i8 %x) {
 ; CHECK-LABEL: @or_ranges_separated(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -5
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 6
-; CHECK-NEXT:    [[TMP3:%.*]] = add i8 [[X]], -12
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ult i8 [[TMP3]], 9
-; CHECK-NEXT:    [[C7:%.*]] = or i1 [[TMP2]], [[TMP4]]
+; CHECK-NEXT:    [[C3:%.*]] = icmp ult i8 [[TMP1]], 6
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[X]], -12
+; CHECK-NEXT:    [[C6:%.*]] = icmp ult i8 [[TMP2]], 9
+; CHECK-NEXT:    [[C7:%.*]] = or i1 [[C3]], [[C6]]
 ; CHECK-NEXT:    ret i1 [[C7]]
 ;
   %c1 = icmp uge i8 %x, 5
   %c2 = icmp ule i8 %x, 10
   %c3 = and i1 %c1, %c2
   %c4 = icmp uge i8 %x, 12
   %c5 = icmp ule i8 %x, 20
   %c6 = and i1 %c4, %c5
   %c7 = or i1 %c3, %c6
   ret i1 %c7
 }
 
 define i1 @or_ranges_single_elem_right(i8 %x) {
 ; CHECK-LABEL: @or_ranges_single_elem_right(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -5
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 7
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C6:%.*]] = icmp ult i8 [[TMP1]], 7
+; CHECK-NEXT:    ret i1 [[C6]]
 ;
   %c1 = icmp uge i8 %x, 5
   %c2 = icmp ule i8 %x, 10
   %c3 = and i1 %c1, %c2
   %c4 = icmp eq i8 %x, 11
   %c6 = or i1 %c3, %c4
   ret i1 %c6
 }
 
 define i1 @or_ranges_single_elem_left(i8 %x) {
 ; CHECK-LABEL: @or_ranges_single_elem_left(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -4
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 7
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C6:%.*]] = icmp ult i8 [[TMP1]], 7
+; CHECK-NEXT:    ret i1 [[C6]]
 ;
   %c1 = icmp uge i8 %x, 5
   %c2 = icmp ule i8 %x, 10
   %c3 = and i1 %c1, %c2
   %c4 = icmp eq i8 %x, 4
   %c6 = or i1 %c3, %c4
   ret i1 %c6
 }
 
 define i1 @and_ranges_overlap(i8 %x) {
 ; CHECK-LABEL: @and_ranges_overlap(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -7
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i8 [[TMP1]], 4
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[C7:%.*]] = icmp ult i8 [[TMP1]], 4
+; CHECK-NEXT:    ret i1 [[C7]]
 ;
   %c1 = icmp uge i8 %x, 5
   %c2 = icmp ule i8 %x, 10
   %c3 = and i1 %c1, %c2
   %c4 = icmp uge i8 %x, 7
   %c5 = icmp ule i8 %x, 20
   %c6 = and i1 %c4, %c5
   %c7 = and i1 %c3, %c6
   ret i1 %c7
 }
 
 define i1 @and_ranges_overlap_single(i8 %x) {
 ; CHECK-LABEL: @and_ranges_overlap_single(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 [[X:%.*]], 10
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[C7:%.*]] = icmp eq i8 [[X:%.*]], 10
+; CHECK-NEXT:    ret i1 [[C7]]
 ;
   %c1 = icmp uge i8 %x, 5
   %c2 = icmp ule i8 %x, 10
   %c3 = and i1 %c1, %c2
   %c4 = icmp uge i8 %x, 10
   %c5 = icmp ule i8 %x, 20
   %c6 = and i1 %c4, %c5
   %c7 = and i1 %c3, %c6
;
   %c6 = and i1 %c4, %c5
   %c7 = and i1 %c3, %c6
   ret i1 %c7
 }
 
 define i1 @and_ranges_signed_pred(i64 %x) {
 ; CHECK-LABEL: @and_ranges_signed_pred(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[X:%.*]], -9223372036854775681
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i64 [[TMP1]], -9223372036854775553
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[T5:%.*]] = icmp ult i64 [[TMP1]], -9223372036854775553
+; CHECK-NEXT:    ret i1 [[T5]]
 ;
   %t1 = add i64 %x, 127
   %t2 = icmp slt i64 %t1, 1024
   %t3 = add i64 %x, 128
   %t4 = icmp slt i64 %t3, 256
   %t5 = and i1 %t2, %t4
   ret i1 %t5
 }
 
 define i1 @and_two_ranges_to_mask_and_range(i8 %c)  {
 ; CHECK-LABEL: @and_two_ranges_to_mask_and_range(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[C:%.*]], -33
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[TMP1]], -91
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ult i8 [[TMP2]], -26
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ult i8 [[TMP2]], -26
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %c.off = add i8 %c, -97
   %cmp1 = icmp ugt i8 %c.off, 25
   %c.off2 = add i8 %c, -65
   %cmp2 = icmp ugt i8 %c.off2, 25
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
;
   %cmp2 = icmp ugt i8 %c.off2, 24
   %and = and i1 %cmp1, %cmp2
   ret i1 %and
 }
 
 define i1 @and_two_ranges_to_mask_and_range_no_add_on_one_range(i16 %x) {
 ; CHECK-LABEL: @and_two_ranges_to_mask_and_range_no_add_on_one_range(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i16 [[X:%.*]], -20
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ugt i16 [[TMP1]], 11
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND:%.*]] = icmp ugt i16 [[TMP1]], 11
+; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %cmp1 = icmp uge i16 %x, 12
   %cmp2 = icmp ult i16 %x, 16
   %cmp3 = icmp uge i16 %x, 28
   %or = or i1 %cmp2, %cmp3
   %and = and i1 %cmp1, %or
   ret i1 %and
 }
 
 ; This tests an "is_alpha" style check for the combination of logical or
 ; and nowrap flags on the adds. In this case, the logical or will not be
 ; converted into a bitwise or.
 define i1 @is_ascii_alphabetic(i32 %char) {
 ; CHECK-LABEL: @is_ascii_alphabetic(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[CHAR:%.*]], -33
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP1]], -65
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ult i32 [[TMP2]], 26
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[LOGICAL:%.*]] = icmp ult i32 [[TMP2]], 26
+; CHECK-NEXT:    ret i1 [[LOGICAL]]
 ;
   %add1 = add nsw i32 %char, -65
   %cmp1 = icmp ult i32 %add1, 26
   %add2 = add nsw i32 %char, -97
   %cmp2 = icmp ult i32 %add2, 26
   %logical = select i1 %cmp1, i1 true, i1 %cmp2
   ret i1 %logical
 }
 
 define i1 @is_ascii_alphabetic_inverted(i32 %char) {
 ; CHECK-LABEL: @is_ascii_alphabetic_inverted(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[CHAR:%.*]], -33
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP1]], -91
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ult i32 [[TMP2]], -26
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[LOGICAL:%.*]] = icmp ult i32 [[TMP2]], -26
+; CHECK-NEXT:    ret i1 [[LOGICAL]]
 ;
   %add1 = add nsw i32 %char, -91
   %cmp1 = icmp ult i32 %add1, -26
   %add2 = add nsw i32 %char, -123
   %cmp2 = icmp ult i32 %add2, -26
   %logical = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %logical
 }
 
 define i1 @bitwise_and_bitwise_and_icmps(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_and_bitwise_and_icmps(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = and i1 [[C1]], [[TMP3]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[C1]], [[TMP3]]
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp ne i8 %x.m1, 0
   %c3 = icmp ne i8 %x.m2, 0
   %and1 = and i1 %c1, %c2
   %and2 = and i1 %and1, %c3
   ret i1 %and2
 }
 
 define i1 @bitwise_and_bitwise_and_icmps_comm1(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_and_bitwise_and_icmps_comm1(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = and i1 [[C1]], [[TMP3]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[C1]], [[TMP3]]
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp ne i8 %x.m1, 0
   %c3 = icmp ne i8 %x.m2, 0
   %and1 = and i1 %c1, %c2
   %and2 = and i1 %c3, %and1
   ret i1 %and2
 }
 
 define i1 @bitwise_and_bitwise_and_icmps_comm2(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_and_bitwise_and_icmps_comm2(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[C1]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[TMP3]], [[C1]]
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp ne i8 %x.m1, 0
   %c3 = icmp ne i8 %x.m2, 0
   %and1 = and i1 %c2, %c1
   %and2 = and i1 %and1, %c3
   ret i1 %and2
 }
 
 define i1 @bitwise_and_bitwise_and_icmps_comm3(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_and_bitwise_and_icmps_comm3(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[C1]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[TMP3]], [[C1]]
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp ne i8 %x.m1, 0
   %c3 = icmp ne i8 %x.m2, 0
   %and1 = and i1 %c2, %c1
   %and2 = and i1 %c3, %and1
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_icmps(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_and_logical_and_icmps(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[C1]], i1 [[TMP3]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP3]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp ne i8 %x.m1, 0
   %c3 = icmp ne i8 %x.m2, 0
   %and1 = select i1 %c1, i1 %c2, i1 false
   %and2 = and i1 %and1, %c3
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_icmps_comm1(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_and_logical_and_icmps_comm1(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[C1]], i1 [[TMP3]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP3]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp ne i8 %x.m1, 0
   %c3 = icmp ne i8 %x.m2, 0
   %and1 = select i1 %c1, i1 %c2, i1 false
   %and2 = and i1 %c3, %and1
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_icmps_comm2(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_and_logical_and_icmps_comm2(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
+; CHECK-NEXT:    [[X_M1:%.*]] = and i8 [[X:%.*]], 1
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = freeze i8 [[Z_SHIFT]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or i8 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], [[X:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i8 [[TMP3]], [[TMP2]]
-; CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP4]], i1 [[C1]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP5]]
+; CHECK-NEXT:    [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]]
+; CHECK-NEXT:    [[C2:%.*]] = icmp ne i8 [[X_M1]], 0
+; CHECK-NEXT:    [[C3:%.*]] = icmp ne i8 [[X_M2]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C1]], [[C3]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C2]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp ne i8 %x.m1, 0
   %c3 = icmp ne i8 %x.m2, 0
   %and1 = select i1 %c2, i1 %c1, i1 false
   %and2 = and i1 %and1, %c3
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_icmps_comm3(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_and_logical_and_icmps_comm3(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
+; CHECK-NEXT:    [[X_M1:%.*]] = and i8 [[X:%.*]], 1
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i1 [[C1]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]]
+; CHECK-NEXT:    [[C2:%.*]] = icmp ne i8 [[X_M1]], 0
+; CHECK-NEXT:    [[C3:%.*]] = icmp ne i8 [[X_M2]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C3]], [[C1]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C2]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp ne i8 %x.m1, 0
   %c3 = icmp ne i8 %x.m2, 0
   %and1 = select i1 %c2, i1 %c1, i1 false

 
 define i1 @bitwise_or_bitwise_or_icmps(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_or_bitwise_or_icmps(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = or i1 [[C1]], [[TMP3]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[OR2:%.*]] = or i1 [[C1]], [[TMP3]]
+; CHECK-NEXT:    ret i1 [[OR2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp eq i8 %x.m1, 0
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = or i1 %c1, %c2
   %or2 = or i1 %or1, %c3
   ret i1 %or2
 }
 
 define i1 @bitwise_or_bitwise_or_icmps_comm1(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_or_bitwise_or_icmps_comm1(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = or i1 [[C1]], [[TMP3]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[OR2:%.*]] = or i1 [[C1]], [[TMP3]]
+; CHECK-NEXT:    ret i1 [[OR2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp eq i8 %x.m1, 0
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = or i1 %c1, %c2
   %or2 = or i1 %c3, %or1
   ret i1 %or2
 }
 
 define i1 @bitwise_or_bitwise_or_icmps_comm2(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_or_bitwise_or_icmps_comm2(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[C1]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[OR2:%.*]] = or i1 [[TMP3]], [[C1]]
+; CHECK-NEXT:    ret i1 [[OR2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp eq i8 %x.m1, 0
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = or i1 %c2, %c1
   %or2 = or i1 %or1, %c3
   ret i1 %or2
 }
 
 define i1 @bitwise_or_bitwise_or_icmps_comm3(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_or_bitwise_or_icmps_comm3(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[C1]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[OR2:%.*]] = or i1 [[TMP3]], [[C1]]
+; CHECK-NEXT:    ret i1 [[OR2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp eq i8 %x.m1, 0
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = or i1 %c2, %c1
   %or2 = or i1 %c3, %or1
   ret i1 %or2
 }
 
 define i1 @bitwise_or_logical_or_icmps(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_or_logical_or_icmps(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP3]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[OR2:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP3]]
+; CHECK-NEXT:    ret i1 [[OR2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp eq i8 %x.m1, 0
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = select i1 %c1, i1 true, i1 %c2
   %or2 = or i1 %or1, %c3
   ret i1 %or2
 }
 
 define i1 @bitwise_or_logical_or_icmps_comm1(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_or_logical_or_icmps_comm1(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP3]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[OR2:%.*]] = select i1 [[C1]], i1 true, i1 [[TMP3]]
+; CHECK-NEXT:    ret i1 [[OR2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp eq i8 %x.m1, 0
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = select i1 %c1, i1 true, i1 %c2
   %or2 = or i1 %c3, %or1
   ret i1 %or2
 }
 
 define i1 @bitwise_or_logical_or_icmps_comm2(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_or_logical_or_icmps_comm2(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
+; CHECK-NEXT:    [[X_M1:%.*]] = and i8 [[X:%.*]], 1
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = freeze i8 [[Z_SHIFT]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or i8 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = and i8 [[TMP2]], [[X:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i8 [[TMP3]], [[TMP2]]
-; CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP4]], i1 true, i1 [[C1]]
-; CHECK-NEXT:    ret i1 [[TMP5]]
+; CHECK-NEXT:    [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]]
+; CHECK-NEXT:    [[C2:%.*]] = icmp eq i8 [[X_M1]], 0
+; CHECK-NEXT:    [[C3:%.*]] = icmp eq i8 [[X_M2]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[C1]], [[C3]]
+; CHECK-NEXT:    [[OR2:%.*]] = select i1 [[C2]], i1 true, i1 [[TMP1]]
+; CHECK-NEXT:    ret i1 [[OR2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp eq i8 %x.m1, 0
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = select i1 %c2, i1 true, i1 %c1
   %or2 = or i1 %or1, %c3
   ret i1 %or2
 }
 
 define i1 @bitwise_or_logical_or_icmps_comm3(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @bitwise_or_logical_or_icmps_comm3(
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42
+; CHECK-NEXT:    [[X_M1:%.*]] = and i8 [[X:%.*]], 1
 ; CHECK-NEXT:    [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1
-; CHECK-NEXT:    [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i1 true, i1 [[C1]]
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]]
+; CHECK-NEXT:    [[C2:%.*]] = icmp eq i8 [[X_M1]], 0
+; CHECK-NEXT:    [[C3:%.*]] = icmp eq i8 [[X_M2]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[C3]], [[C1]]
+; CHECK-NEXT:    [[OR2:%.*]] = select i1 [[C2]], i1 true, i1 [[TMP1]]
+; CHECK-NEXT:    ret i1 [[OR2]]
 ;
   %c1 = icmp eq i8 %y, 42
   %x.m1 = and i8 %x, 1
   %z.shift = shl i8 1, %z
   %x.m2 = and i8 %x, %z.shift
   %c2 = icmp eq i8 %x.m1, 0
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = select i1 %c2, i1 true, i1 %c1
;
   %c3 = icmp eq i8 %x.m2, 0
   %or1 = select i1 %c2, i1 true, i1 %c1
   %or2 = select i1 %c3, i1 true, i1 %or1
   ret i1 %or2
 }
 
 define i1 @bitwise_and_logical_and_masked_icmp_asymmetric(i1 %c, i32 %x) {
 ; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_asymmetric(
-; CHECK-NEXT:    [[X_M2:%.*]] = and i32 [[X:%.*]], 11
+; CHECK-NEXT:    [[X_M1:%.*]] = and i32 [[X:%.*]], 255
+; CHECK-NEXT:    [[C1:%.*]] = icmp ne i32 [[X_M1]], 0
+; CHECK-NEXT:    [[X_M2:%.*]] = and i32 [[X]], 11
 ; CHECK-NEXT:    [[C2:%.*]] = icmp eq i32 [[X_M2]], 11
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C2]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C2]], [[C:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %x.m1 = and i32 %x, 255
   %c1 = icmp ne i32 %x.m1, 0
   %and1 = select i1 %c1, i1 %c, i1 false
   %x.m2 = and i32 %x, 11
   %c2 = icmp eq i32 %x.m2, 11
   %and2 = and i1 %and1, %c2
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_masked_icmp_allzeros(i1 %c, i32 %x) {
 ; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_allzeros(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[X_M1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT:    [[C1:%.*]] = icmp eq i32 [[X_M1]], 0
+; CHECK-NEXT:    [[X_M2:%.*]] = and i32 [[X]], 7
+; CHECK-NEXT:    [[C2:%.*]] = icmp eq i32 [[X_M2]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C2]], [[C:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %x.m1 = and i32 %x, 8
   %c1 = icmp eq i32 %x.m1, 0
   %and1 = select i1 %c1, i1 %c, i1 false
   %x.m2 = and i32 %x, 7
   %c2 = icmp eq i32 %x.m2, 0
   %and2 = and i1 %and1, %c2
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_masked_icmp_allzeros_poison1(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_allzeros_poison1(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[Y:%.*]], 7
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[X_M1:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[C1:%.*]] = icmp eq i32 [[X_M1]], 0
+; CHECK-NEXT:    [[X_M2:%.*]] = and i32 [[X]], 7
+; CHECK-NEXT:    [[C2:%.*]] = icmp eq i32 [[X_M2]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C2]], [[C:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %x.m1 = and i32 %x, %y
   %c1 = icmp eq i32 %x.m1, 0
   %and1 = select i1 %c1, i1 %c, i1 false
   %x.m2 = and i32 %x, 7
   %c2 = icmp eq i32 %x.m2, 0
   %and2 = and i1 %and1, %c2
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_masked_icmp_allzeros_poison2(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_allzeros_poison2(
 ; CHECK-NEXT:    [[X_M1:%.*]] = and i32 [[X:%.*]], 8
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i32 [[X_M1]], 0
-; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[C1]], i1 [[C:%.*]], i1 false
 ; CHECK-NEXT:    [[X_M2:%.*]] = and i32 [[X]], [[Y:%.*]]
 ; CHECK-NEXT:    [[C2:%.*]] = icmp eq i32 [[X_M2]], 0
-; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[AND1]], [[C2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C2]], [[C:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %x.m1 = and i32 %x, 8
   %c1 = icmp eq i32 %x.m1, 0
   %and1 = select i1 %c1, i1 %c, i1 false
   %x.m2 = and i32 %x, %y
   %c2 = icmp eq i32 %x.m2, 0
   %and2 = and i1 %and1, %c2
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_masked_icmp_allones(i1 %c, i32 %x) {
 ; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_allones(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 15
-; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP3]]
+; CHECK-NEXT:    [[X_M1:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT:    [[C1:%.*]] = icmp ne i32 [[X_M1]], 0
+; CHECK-NEXT:    [[X_M2:%.*]] = and i32 [[X]], 7
+; CHECK-NEXT:    [[C2:%.*]] = icmp eq i32 [[X_M2]], 7
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C2]], [[C:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %x.m1 = and i32 %x, 8
   %c1 = icmp eq i32 %x.m1, 8
   %and1 = select i1 %c1, i1 %c, i1 false
   %x.m2 = and i32 %x, 7
   %c2 = icmp eq i32 %x.m2, 7
   %and2 = and i1 %and1, %c2
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_masked_icmp_allones_poison1(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_allones_poison1(
-; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[Y:%.*]], 7
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i1 [[C:%.*]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP4]]
+; CHECK-NEXT:    [[X_M1:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[C1:%.*]] = icmp eq i32 [[X_M1]], [[Y]]
+; CHECK-NEXT:    [[X_M2:%.*]] = and i32 [[X]], 7
+; CHECK-NEXT:    [[C2:%.*]] = icmp eq i32 [[X_M2]], 7
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C2]], [[C:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %x.m1 = and i32 %x, %y
   %c1 = icmp eq i32 %x.m1, %y
   %and1 = select i1 %c1, i1 %c, i1 false
   %x.m2 = and i32 %x, 7
   %c2 = icmp eq i32 %x.m2, 7
   %and2 = and i1 %and1, %c2
   ret i1 %and2
 }
 
 define i1 @bitwise_and_logical_and_masked_icmp_allones_poison2(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @bitwise_and_logical_and_masked_icmp_allones_poison2(
 ; CHECK-NEXT:    [[X_M1:%.*]] = and i32 [[X:%.*]], 8
 ; CHECK-NEXT:    [[C1:%.*]] = icmp ne i32 [[X_M1]], 0
-; CHECK-NEXT:    [[AND1:%.*]] = select i1 [[C1]], i1 [[C:%.*]], i1 false
 ; CHECK-NEXT:    [[X_M2:%.*]] = and i32 [[X]], [[Y:%.*]]
 ; CHECK-NEXT:    [[C2:%.*]] = icmp eq i32 [[X_M2]], [[Y]]
-; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[AND1]], [[C2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[C2]], [[C:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[C1]], i1 [[TMP1]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %x.m1 = and i32 %x, 8
   %c1 = icmp eq i32 %x.m1, 8
   %and1 = select i1 %c1, i1 %c, i1 false
   %x.m2 = and i32 %x, %y
   %c2 = icmp eq i32 %x.m2, %y
   %and2 = and i1 %and1, %c2
   ret i1 %and2
 }
 
 define i1 @samesign(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %lt = icmp slt i32 %a, 0
   %o = or i32 %x, %y
   %gt = icmp sgt i32 %o, -1
   %r = or i1 %lt, %gt
   ret i1 %r
 }
 
 define <2 x i1> @samesign_different_sign_bittest1(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @samesign_different_sign_bittest1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <2 x i32> [[TMP1]], <i32 -1, i32 -1>
-; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt <2 x i32> [[TMP1]], <i32 -1, i32 -1>
+; CHECK-NEXT:    ret <2 x i1> [[R]]
 ;
   %a = and <2 x i32> %x, %y
   %lt = icmp sle <2 x i32> %a, <i32 -1, i32 -1>
   %o = or <2 x i32> %x, %y
   %gt = icmp sgt <2 x i32> %o, <i32 -1, i32 -1>
   %r = or <2 x i1> %lt, %gt
   ret <2 x i1> %r
 }
 
 define i1 @samesign_different_sign_bittest2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_different_sign_bittest2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %lt = icmp slt i32 %a, 0
   %o = or i32 %x, %y
   %gt = icmp sge i32 %o, 0
   %r = or i1 %lt, %gt
   ret i1 %r
 }
 
 define i1 @samesign_commute1(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_commute1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %lt = icmp slt i32 %a, 0
   %o = or i32 %x, %y
   %gt = icmp sgt i32 %o, -1
   %r = or i1 %gt, %lt ; compares swapped
   ret i1 %r
 }
 
 define i1 @samesign_commute2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_commute2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %lt = icmp slt i32 %a, 0
   %o = or i32 %y, %x ; inputs commuted
   %gt = icmp sgt i32 %o, -1
   %r = or i1 %lt, %gt
   ret i1 %r
 }
 
 define i1 @samesign_commute3(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_commute3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %lt = icmp slt i32 %a, 0
   %o = or i32 %y, %x ; inputs commuted
   %gt = icmp sgt i32 %o, -1
   %r = or i1 %gt, %lt ; compares swapped
   ret i1 %r
 }

 
 define i1 @samesign_mult_use(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_mult_use(
 ; CHECK-NEXT:    [[A:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    call void @use32(i32 [[A]])
 ; CHECK-NEXT:    [[O:%.*]] = or i32 [[X]], [[Y]]
 ; CHECK-NEXT:    call void @use32(i32 [[O]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   call void @use32(i32 %a)
   %lt = icmp slt i32 %a, 0
   %o = or i32 %x, %y
   call void @use32(i32 %o)
   %gt = icmp sgt i32 %o, -1
   %r = or i1 %lt, %gt
   ret i1 %r
 }
 
 define i1 @samesign_mult_use2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_mult_use2(
 ; CHECK-NEXT:    [[O:%.*]] = or i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[GT:%.*]] = icmp sgt i32 [[O]], -1
 ; CHECK-NEXT:    call void @use(i1 [[GT]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp sgt i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %lt = icmp slt i32 %a, 0
   %o = or i32 %x, %y
   %gt = icmp sgt i32 %o, -1
   call void @use(i1 %gt)
   %r = or i1 %lt, %gt
   ret i1 %r
;
   %gt = icmp sgt i32 %o, -1
   %r = and i1 %lt, %gt
   ret i1 %r
 }
 
 define i1 @samesign_inverted(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_inverted(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %gt = icmp sgt i32 %a, -1
   %o = or i32 %x, %y
   %lt = icmp slt i32 %o, 0
   %r = and i1 %gt, %lt
   ret i1 %r
 }
 
 define i1 @samesign_inverted_different_sign_bittest1(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_inverted_different_sign_bittest1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %gt = icmp sge i32 %a, 0
   %o = or i32 %x, %y
   %lt = icmp slt i32 %o, 0
   %r = and i1 %gt, %lt
   ret i1 %r
 }
 
 define i1 @samesign_inverted_different_sign_bittest2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_inverted_different_sign_bittest2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %gt = icmp sgt i32 %a, -1
   %o = or i32 %x, %y
   %lt = icmp sle i32 %o, -1
   %r = and i1 %gt, %lt
   ret i1 %r
 }
 
 define i1 @samesign_inverted_commute1(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_inverted_commute1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %gt = icmp sgt i32 %a, -1
   %o = or i32 %x, %y
   %lt = icmp slt i32 %o, 0
   %r = and i1 %lt, %gt ; compares swapped
   ret i1 %r
 }
 
 define i1 @samesign_inverted_commute2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_inverted_commute2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %gt = icmp sgt i32 %a, -1
   %o = or i32 %y, %x ; source values are commuted
   %lt = icmp slt i32 %o, 0
   %r = and i1 %gt, %lt
   ret i1 %r
 }
 
 define i1 @samesign_inverted_commute3(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_inverted_commute3(
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   %gt = icmp sgt i32 %a, -1
   %o = or i32 %y, %x ; source values commuted
   %lt = icmp slt i32 %o, 0
   %r = and i1 %lt, %gt ; compares swapped
   ret i1 %r
 }

 
 define i1 @samesign_inverted_mult_use(i32 %x, i32 %y) {
 ; CHECK-LABEL: @samesign_inverted_mult_use(
 ; CHECK-NEXT:    [[A:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    call void @use32(i32 [[A]])
 ; CHECK-NEXT:    [[O:%.*]] = or i32 [[X]], [[Y]]
 ; CHECK-NEXT:    call void @use32(i32 [[O]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[TMP1]], 0
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[R:%.*]] = icmp slt i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[R]]
 ;
   %a = and i32 %x, %y
   call void @use32(i32 %a)
   %gt = icmp sgt i32 %a, -1
   %o = or i32 %x, %y
   call void @use32(i32 %o)
   %lt = icmp slt i32 %o, 0
   %r = and i1 %gt, %lt

llvm/test/Transforms/InstCombine/and2.ll

;
   %a = and i32 %X, %Y
   %b = and i32 %Y, %a
   ret i32 %b
 }
 
 define i1 @test7(i32 %i, i1 %b) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = and i1 [[TMP1]], [[B:%.*]]
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[AND2:%.*]] = and i1 [[TMP1]], [[B:%.*]]
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %cmp1 = icmp slt i32 %i, 1
   %cmp2 = icmp sgt i32 %i, -1
   %and1 = and i1 %cmp1, %b
   %and2 = and i1 %and1, %cmp2
   ret i1 %and2
 }
 
 define i1 @test7_logical(i32 %i, i1 %b) {
 ; CHECK-LABEL: @test7_logical(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[I:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[I:%.*]], 1
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[I]], -1
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[CMP2]], [[B:%.*]]
+; CHECK-NEXT:    [[AND2:%.*]] = select i1 [[CMP1]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    ret i1 [[AND2]]
 ;
   %cmp1 = icmp slt i32 %i, 1
   %cmp2 = icmp sgt i32 %i, -1
   %and1 = select i1 %cmp1, i1 %b, i1 false
   %and2 = select i1 %and1, i1 %cmp2, i1 false
   ret i1 %and2
 }
 
 define i1 @test8(i32 %i) {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[I:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 13
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[TMP1]], 13
+; CHECK-NEXT:    ret i1 [[COND]]
 ;
   %cmp1 = icmp ne i32 %i, 0
   %cmp2 = icmp ult i32 %i, 14
   %cond = and i1 %cmp1, %cmp2
   ret i1 %cond
 }
 
 define i1 @test8_logical(i32 %i) {
 ; CHECK-LABEL: @test8_logical(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[I:%.*]], -1
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 13
-; CHECK-NEXT:    ret i1 [[TMP2]]
+; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[TMP1]], 13
+; CHECK-NEXT:    ret i1 [[COND]]
 ;
   %cmp1 = icmp ne i32 %i, 0
   %cmp2 = icmp ult i32 %i, 14
   %cond = select i1 %cmp1, i1 %cmp2, i1 false
   ret i1 %cond
 }
 
 define <2 x i1> @test8vec(<2 x i32> %i) {
 ; CHECK-LABEL: @test8vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[I:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 13, i32 13>
-; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
+; CHECK-NEXT:    [[COND:%.*]] = icmp ult <2 x i32> [[TMP1]], <i32 13, i32 13>
+; CHECK-NEXT:    ret <2 x i1> [[COND]]
 ;
   %cmp1 = icmp ne <2 x i32> %i, zeroinitializer
   %cmp2 = icmp ult <2 x i32> %i, <i32 14, i32 14>
   %cond = and <2 x i1> %cmp1, %cmp2
   ret <2 x i1> %cond
 }
 
 ; combine -x & 1 into x & 1

llvm/test/Transforms/InstCombine/binop-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
 declare void @use(i32)
 declare void @use_f32(float)
 declare void @use_v2f16(<2 x half>)
 declare void @use_v2i8(<2 x i8>)
 
 define i32 @test1(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 [[Y:%.*]]
-; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[COND]], [[X]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[C:%.*]], i32 0, i32 [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %sub = sub i32 0, %x
   %cond = select i1 %c, i32 %sub, i32 %y
   %add = add i32 %cond, %x
   ret i32 %add
 }
 
 define i32 @test2(i1 %c, i32 %x, i32 %y) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 0, [[X:%.*]]
-; CHECK-NEXT:    [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 [[X]]
-; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[COND]], [[X]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[C:%.*]], i32 0, i32 [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %sub = sub i32 0, %x
   %cond = select i1 %c, i32 %sub, i32 %x
   %add = add i32 %cond, %x
   ret i32 %add
 }
 

llvm/test/Transforms/InstCombine/icmp-add.ll

 ; In the following 4 tests, we could push the inc/dec
 ; through the min/max, but we should not break up the
 ; min/max idiom by using different icmp and select
 ; operands.
 
 define i32 @increment_max(i32 %x) {
 ; CHECK-LABEL: @increment_max(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 -1)
-; CHECK-NEXT:    [[TMP2:%.*]] = add nsw i32 [[TMP1]], 1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[TMP1]], 1
+; CHECK-NEXT:    ret i32 [[S]]
 ;
   %a = add nsw i32 %x, 1
   %c = icmp sgt i32 %a, 0
   %s = select i1 %c, i32 %a, i32 0
   ret i32 %s
 }
 
 define i32 @decrement_max(i32 %x) {
 ; CHECK-LABEL: @decrement_max(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[X:%.*]], i32 1)
-; CHECK-NEXT:    [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i32 [[S]]
 ;
   %a = add nsw i32 %x, -1
   %c = icmp sgt i32 %a, 0
   %s = select i1 %c, i32 %a, i32 0
   ret i32 %s
 }
 
 define i32 @increment_min(i32 %x) {
 ; CHECK-LABEL: @increment_min(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 -1)
-; CHECK-NEXT:    [[TMP2:%.*]] = add nsw i32 [[TMP1]], 1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[TMP1]], 1
+; CHECK-NEXT:    ret i32 [[S]]
 ;
   %a = add nsw i32 %x, 1
   %c = icmp slt i32 %a, 0
   %s = select i1 %c, i32 %a, i32 0
   ret i32 %s
 }
 
 define i32 @decrement_min(i32 %x) {
 ; CHECK-LABEL: @decrement_min(
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 1)
-; CHECK-NEXT:    [[TMP2:%.*]] = add nsw i32 [[TMP1]], -1
-; CHECK-NEXT:    ret i32 [[TMP2]]
+; CHECK-NEXT:    [[S:%.*]] = add nsw i32 [[TMP1]], -1
+; CHECK-NEXT:    ret i32 [[S]]
 ;
   %a = add nsw i32 %x, -1
   %c = icmp slt i32 %a, 0
   %s = select i1 %c, i32 %a, i32 0
   ret i32 %s
 }
 
 define i1 @icmp_add_add_C(i32 %a, i32 %b) {

llvm/test/Transforms/InstCombine/max_known_bits.ll

;
   %t6 = and i16 %t5, 255
   ret i16 %t6
 }
 
 ; This contains a min/max pair to clamp a value to 12 bits.
 ; By analyzing the clamp pattern, we can tell the add doesn't have signed overflow.
 define i16 @min_max_clamp(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 -2048)
-; CHECK-NEXT:    [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 2047)
-; CHECK-NEXT:    [[E:%.*]] = add nsw i16 [[TMP2]], 1
+; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 -2048)
+; CHECK-NEXT:    [[D:%.*]] = call i16 @llvm.smin.i16(i16 [[B]], i16 2047)
+; CHECK-NEXT:    [[E:%.*]] = add nsw i16 [[D]], 1
 ; CHECK-NEXT:    ret i16 [[E]]
 ;
   %a = icmp sgt i16 %x, -2048
   %b = select i1 %a, i16 %x, i16 -2048
   %c = icmp slt i16 %b, 2047
   %d = select i1 %c, i16 %b, i16 2047
   %e = add i16 %d, 1
   ret i16 %e
 }
 
 ; Same as above with min/max reversed.
 define i16 @min_max_clamp_2(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_2(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
-; CHECK-NEXT:    [[TMP2:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP1]], i16 -2048)
-; CHECK-NEXT:    [[E:%.*]] = add nsw i16 [[TMP2]], 1
+; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
+; CHECK-NEXT:    [[D:%.*]] = call i16 @llvm.smax.i16(i16 [[B]], i16 -2048)
+; CHECK-NEXT:    [[E:%.*]] = add nsw i16 [[D]], 1
 ; CHECK-NEXT:    ret i16 [[E]]
 ;
   %a = icmp slt i16 %x, 2047
   %b = select i1 %a, i16 %x, i16 2047
   %c = icmp sgt i16 %b, -2048
   %d = select i1 %c, i16 %b, i16 -2048
   %e = add i16 %d, 1
   ret i16 %e
 }
 
 ; This contains a min/max pair to clamp a value to 12 bits.
 ; By analyzing the clamp pattern, we can tell that the second add doesn't
 ; overflow the original type and can be moved before the extend.
 define i32 @min_max_clamp_3(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_3(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 -2048)
-; CHECK-NEXT:    [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 2047)
-; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP2]] to i32
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smax.i16(i16 [[X:%.*]], i16 -2048)
+; CHECK-NEXT:    [[D:%.*]] = call i16 @llvm.smin.i16(i16 [[B]], i16 2047)
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[D]] to i32
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %a = icmp sgt i16 %x, -2048
   %b = select i1 %a, i16 %x, i16 -2048
   %c = icmp slt i16 %b, 2047
   %d = select i1 %c, i16 %b, i16 2047
   %e = add i16 %d, 1
   %f = sext i16 %e to i32
   %g = add i32 %f, -1
   ret i32 %g
 }
 
 ; Same as above with min/max order reversed
 define i32 @min_max_clamp_4(i16 %x) {
 ; CHECK-LABEL: @min_max_clamp_4(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
-; CHECK-NEXT:    [[TMP2:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP1]], i16 -2048)
-; CHECK-NEXT:    [[TMP3:%.*]] = sext i16 [[TMP2]] to i32
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[B:%.*]] = call i16 @llvm.smin.i16(i16 [[X:%.*]], i16 2047)
+; CHECK-NEXT:    [[D:%.*]] = call i16 @llvm.smax.i16(i16 [[B]], i16 -2048)
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[D]] to i32
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %a = icmp slt i16 %x, 2047
   %b = select i1 %a, i16 %x, i16 2047
   %c = icmp sgt i16 %b, -2048
   %d = select i1 %c, i16 %b, i16 -2048
   %e = add i16 %d, 1
   %f = sext i16 %e to i32
   %g = add i32 %f, -1

llvm/test/Transforms/InstCombine/minmax-demandbits.ll

;
   %l0 = icmp ugt i32 12, %A
   %l1 = select i1 %l0, i32 12, i32 %A
   %x = and i32 %l1, -32
   ret i32 %x
 }
 
 define i32 @and_umax_more(i32 %A) {
 ; CHECK-LABEL: @and_umax_more(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 32)
-; CHECK-NEXT:    [[X:%.*]] = and i32 [[TMP1]], -32
+; CHECK-NEXT:    [[L1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 32)
+; CHECK-NEXT:    [[X:%.*]] = and i32 [[L1]], -32
 ; CHECK-NEXT:    ret i32 [[X]]
 ;
   %l0 = icmp ugt i32 32, %A
   %l1 = select i1 %l0, i32 32, i32 %A
   %x = and i32 %l1, -32
   ret i32 %x
 }
 
;
   %l2 = icmp ugt i8 %A, 2
   %l1 = select i1 %l2, i8 %A, i8 2
   %x = or i8 %l1, 63
   ret i8 %x
 }
 
 define i8 @f_1_1(i8 %A) {
 ; CHECK-LABEL: @f_1_1(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 1)
-; CHECK-NEXT:    [[X:%.*]] = and i8 [[TMP1]], 1
+; CHECK-NEXT:    [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 1)
+; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], 1
 ; CHECK-NEXT:    ret i8 [[X]]
 ;
   %l2 = icmp ugt i8 %A, 1
   %l1 = select i1 %l2, i8 %A, i8 1
   %x = and i8 %l1, 1
   ret i8 %x
 }
 
 define i8 @f_32_32(i8 %A) {
 ; CHECK-LABEL: @f_32_32(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 32)
-; CHECK-NEXT:    [[X:%.*]] = and i8 [[TMP1]], -32
+; CHECK-NEXT:    [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 32)
+; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], -32
 ; CHECK-NEXT:    ret i8 [[X]]
 ;
   %l2 = icmp ugt i8 %A, 32
   %l1 = select i1 %l2, i8 %A, i8 32
   %x = and i8 %l1, -32
   ret i8 %x
 }
 
 define i8 @f_191_192(i8 %A) {
 ; CHECK-LABEL: @f_191_192(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 -65)
-; CHECK-NEXT:    [[X:%.*]] = and i8 [[TMP1]], -64
+; CHECK-NEXT:    [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 -65)
+; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], -64
 ; CHECK-NEXT:    ret i8 [[X]]
 ;
   %l2 = icmp ugt i8 %A, 191
   %l1 = select i1 %l2, i8 %A, i8 191
   %x = and i8 %l1, 192
   ret i8 %x
 }
 
 define i8 @f_10_1(i8 %A) {
 ; CHECK-LABEL: @f_10_1(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 10)
-; CHECK-NEXT:    [[X:%.*]] = and i8 [[TMP1]], 1
+; CHECK-NEXT:    [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 10)
+; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], 1
 ; CHECK-NEXT:    ret i8 [[X]]
 ;
   %l2 = icmp ugt i8 %A, 10
   %l1 = select i1 %l2, i8 %A, i8 10
   %x = and i8 %l1, 1
   ret i8 %x
 }
 
;
   %l2 = icmp ult i8 %A, -8
   %min = select i1 %l2, i8 %A, i8 -8
   %r = and i8 %min, -8
   ret i8 %r
 }
 
 define i8 @and_min_7_9(i8 %A) {
 ; CHECK-LABEL: @and_min_7_9(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[A:%.*]], i8 -9)
-; CHECK-NEXT:    [[R:%.*]] = and i8 [[TMP1]], -8
+; CHECK-NEXT:    [[MIN:%.*]] = call i8 @llvm.umin.i8(i8 [[A:%.*]], i8 -9)
+; CHECK-NEXT:    [[R:%.*]] = and i8 [[MIN]], -8
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %l2 = icmp ult i8 %A, -9
   %min = select i1 %l2, i8 %A, i8 -9
   %r = and i8 %min, -8
   ret i8 %r
 }
 

llvm/test/Transforms/InstCombine/not.ll

;
   %notx = xor <2 x i1> %x, <i1 true, i1 true>
   %and = select <2 x i1> %notx, <2 x i1> %y, <2 x i1> zeroinitializer
   %notand = xor <2 x i1> %and, <i1 true, i1 true>
   ret <2 x i1> %notand
 }
 
 define i1 @not_logicalAnd_not_op1(i1 %x, i1 %y) {
 ; CHECK-LABEL: @not_logicalAnd_not_op1(
-; CHECK-NEXT:    [[NOT_X:%.*]] = xor i1 [[X:%.*]], true
-; CHECK-NEXT:    [[NOTAND:%.*]] = select i1 [[NOT_X]], i1 true, i1 [[Y:%.*]]
+; CHECK-NEXT:    [[NOTY:%.*]] = xor i1 [[Y:%.*]], true
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[X:%.*]], i1 [[NOTY]], i1 false
+; CHECK-NEXT:    [[NOTAND:%.*]] = xor i1 [[AND]], true
 ; CHECK-NEXT:    ret i1 [[NOTAND]]
 ;
   %noty = xor i1 %y, true
   %and = select i1 %x, i1 %noty, i1 false
   %notand = xor i1 %and, true
   ret i1 %notand
 }
 
;
   %notx = xor <2 x i1> %x, <i1 true, i1 true>
   %or = select <2 x i1> %notx, <2 x i1> <i1 true, i1 true>, <2 x i1> %y
   %notor = xor <2 x i1> %or, <i1 true, i1 true>
   ret <2 x i1> %notor
 }
 
 define i1 @not_logicalOr_not_op1(i1 %x, i1 %y) {
 ; CHECK-LABEL: @not_logicalOr_not_op1(
-; CHECK-NEXT:    [[NOT_X:%.*]] = xor i1 [[X:%.*]], true
-; CHECK-NEXT:    [[NOTOR:%.*]] = select i1 [[NOT_X]], i1 [[Y:%.*]], i1 false
+; CHECK-NEXT:    [[NOTY:%.*]] = xor i1 [[Y:%.*]], true
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[X:%.*]], i1 true, i1 [[NOTY]]
+; CHECK-NEXT:    [[NOTOR:%.*]] = xor i1 [[OR]], true
 ; CHECK-NEXT:    ret i1 [[NOTOR]]
 ;
   %noty = xor i1 %y, true
   %or = select i1 %x, i1 true, i1 %noty
   %notor = xor i1 %or, true
   ret i1 %notor
 }
 

llvm/test/Transforms/InstCombine/rem.ll

 ;
   %B = srem <2 x i32> %A, <i32 -8, i32 -8>
   %C = icmp ne <2 x i32> %B, zeroinitializer
   ret <2 x i1> %C
 }
 
 define i32 @test4(i32 %X, i1 %C) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    [[TMP1:%.*]] = select i1 [[C:%.*]], i32 0, i32 7
-; CHECK-NEXT:    [[R:%.*]] = and i32 [[TMP1]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 7
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i32 0, i32 [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %V = select i1 %C, i32 1, i32 8
   %R = urem i32 %X, %V
   ret i32 %R
 }
 
 define i32 @test5(i32 %X, i8 %B) {

llvm/test/Transforms/InstCombine/select-2.ll

;
   %t2 = and i32 %x, 18
   %t3 = select i1 %t1, i32 %t2, i32 %x
   ret i32 %t3
 }
 
 define float @t3(float %x, float %y) {
 ; CHECK-LABEL: @t3(
 ; CHECK-NEXT:    [[T1:%.*]] = fcmp ogt float [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    [[X_OP:%.*]] = fadd fast float [[X]], 1.000000e+00
-; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T1]], float [[X_OP]], float 2.000000e+00
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd fast float [[X]], 1.000000e+00
+; CHECK-NEXT:    [[T3:%.*]] = select i1 [[T1]], float [[TMP1]], float 2.000000e+00
 ; CHECK-NEXT:    ret float [[T3]]
 ;
   %t1 = fcmp ogt float %x, %y
   %t2 = select i1 %t1, float %x, float 1.0
   %t3 = fadd fast float %t2, 1.0
   ret float %t3
 }
 
 define i8 @ashr_exact_poison_constant_fold(i1 %b, i8 %x) {
 ; CHECK-LABEL: @ashr_exact_poison_constant_fold(
-; CHECK-NEXT:    [[X_OP:%.*]] = ashr exact i8 [[X:%.*]], 3
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 [[X_OP]], i8 5
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr exact i8 [[X:%.*]], 3
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 5
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s = select i1 %b, i8 %x, i8 42
   %r = ashr exact i8 %s, 3
   ret i8 %r
 }
 
 define i8 @ashr_exact(i1 %b, i8 %x) {
 ; CHECK-LABEL: @ashr_exact(
-; CHECK-NEXT:    [[X_OP:%.*]] = ashr exact i8 [[X:%.*]], 3
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 [[X_OP]], i8 2
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr exact i8 [[X:%.*]], 3
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 2
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s = select i1 %b, i8 %x, i8 16
   %r = ashr exact i8 %s, 3
   ret i8 %r
 }
 
 define i8 @shl_nsw_nuw_poison_constant_fold(i1 %b, i8 %x) {
 ; CHECK-LABEL: @shl_nsw_nuw_poison_constant_fold(
-; CHECK-NEXT:    [[X_OP:%.*]] = shl nuw nsw i8 16, [[X:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 -128, i8 [[X_OP]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i8 16, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 -128, i8 [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s = select i1 %b, i8 3, i8 %x
   %r = shl nsw nuw i8 16, %s
   ret i8 %r
 }
 
 define i8 @shl_nsw_nuw(i1 %b, i8 %x) {
 ; CHECK-LABEL: @shl_nsw_nuw(
-; CHECK-NEXT:    [[X_OP:%.*]] = shl nuw nsw i8 7, [[X:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 56, i8 [[X_OP]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i8 7, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 56, i8 [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s = select i1 %b, i8 3, i8 %x
   %r = shl nsw nuw i8 7, %s
   ret i8 %r
 }
 
 define i8 @add_nsw_poison_constant_fold(i1 %b, i8 %x) {
 ; CHECK-LABEL: @add_nsw_poison_constant_fold(
-; CHECK-NEXT:    [[X_OP:%.*]] = add nsw i8 [[X:%.*]], 64
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 [[X_OP]], i8 -127
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], 64
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 -127
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s = select i1 %b, i8 %x, i8 65
   %r = add nsw i8 %s, 64
   ret i8 %r
 }
 
 define i8 @add_nsw(i1 %b, i8 %x) {
 ; CHECK-LABEL: @add_nsw(
-; CHECK-NEXT:    [[X_OP:%.*]] = add nsw i8 [[X:%.*]], 64
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 [[X_OP]], i8 71
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], 64
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[B:%.*]], i8 [[TMP1]], i8 71
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %s = select i1 %b, i8 %x, i8 7
   %r = add nsw i8 %s, 64
   ret i8 %r
 }

llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -passes=instcombine %s -S -o - | FileCheck %s
 
 ; Clamp positive to allOnes:
 ; E.g., clamp255 implemented in a shifty way, could be optimized as v > 255 ? 255 : v, where sub hasNoSignedWrap.
 ; int32 clamp255(int32 v) {
 ;   return (((255 - (v)) >> 31) | (v)) & 255;
 ; }
 ;
 
 ; Scalar Types
 
 define i32 @clamp255_i32(i32 %x) {
 ; CHECK-LABEL: @clamp255_i32(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[TMP1]], 255
+; CHECK-NEXT:    [[OR:%.*]] = call i32 @llvm.smin.i32(i32 [[X:%.*]], i32 255)
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[OR]], 255
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nsw i32 255, %x
   %shr = ashr i32 %sub, 31
   %or = or i32 %shr, %x
   %and = and i32 %or, 255
   ret i32 %and
 }

llvm/test/Transforms/InstCombine/subtract-from-one-hand-of-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S < %s -passes=instcombine | FileCheck %s
 
 ; Fold
 ;   sub %Op0, (select %Cond, %TrueVal, %FalseVal)
 ; to
 ;   select %Cond, (sub %Op0, %TrueVal), (sub %Op0, %FalseVal)
 
 ; https://bugs.llvm.org/show_bug.cgi?id=44426
 
 ; Base tests
 
 define i8 @t0_sub_from_trueval(i1 %c, i8 %Op0, i8 %FalseVal) {
 ; CHECK-LABEL: @t0_sub_from_trueval(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[FALSEVAL:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i8 0, i8 [[TMP1]], !prof !0
-; CHECK-NEXT:    ret i8 [[R]]
+; CHECK-NEXT:    [[R1:%.*]] = select i1 [[C:%.*]], i8 0, i8 [[TMP1]]
+; CHECK-NEXT:    ret i8 [[R1]]
 ;
   %o = select i1 %c, i8 %Op0, i8 %FalseVal, !prof !0 ; while there, ensure preservation of prof md
   %r = sub i8 %Op0, %o
   ret i8 %r
 }
 define i8 @t1_sub_from_falseval(i1 %c, i8 %TrueVal, i8 %Op0) {
 ; CHECK-LABEL: @t1_sub_from_falseval(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i8 [[OP0:%.*]], [[TRUEVAL:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i8 [[TMP1]], i8 0, !prof !0
-; CHECK-NEXT:    ret i8 [[R]]
+; CHECK-NEXT:    [[R1:%.*]] = select i1 [[C:%.*]], i8 [[TMP1]], i8 0
+; CHECK-NEXT:    ret i8 [[R1]]
 ;
   %o = select i1 %c, i8 %TrueVal, i8 %Op0, !prof !0 ; while there, ensure preservation of prof md
   %r = sub i8 %Op0, %o
   ret i8 %r
 }
 
 ; Vectors
 
 define <2 x i8> @t2_vec(i1 %c, <2 x i8> %Op0, <2 x i8> %FalseVal) {
 ; CHECK-LABEL: @t2_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i8> [[OP0:%.*]], [[FALSEVAL:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], <2 x i8> zeroinitializer, <2 x i8> [[TMP1]]
-; CHECK-NEXT:    ret <2 x i8> [[R]]
+; CHECK-NEXT:    [[R1:%.*]] = select i1 [[C:%.*]], <2 x i8> zeroinitializer, <2 x i8> [[TMP1]]
+; CHECK-NEXT:    ret <2 x i8> [[R1]]
 ;
   %o = select i1 %c, <2 x i8> %Op0, <2 x i8> %FalseVal
   %r = sub <2 x i8> %Op0, %o
   ret <2 x i8> %r
 }
 
 ; Extra use
 

llvm/test/Transforms/InstCombine/subtract-of-one-hand-of-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S < %s -passes=instcombine | FileCheck %s
 
 ; Fold
 ;   sub (select %Cond, %TrueVal, %FalseVal), %Op1
 ; to
 ;   select %Cond, (sub %TrueVal, %Op1), (sub %FalseVal, %Op1)
 
 ; https://bugs.llvm.org/show_bug.cgi?id=44426
 
 ; Base tests
 
 define i8 @t0_sub_of_trueval(i1 %c, i8 %Op1, i8 %FalseVal) {
 ; CHECK-LABEL: @t0_sub_of_trueval(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i8 [[FALSEVAL:%.*]], [[OP1:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i8 0, i8 [[TMP1]], !prof !0
-; CHECK-NEXT:    ret i8 [[R]]
+; CHECK-NEXT:    [[R1:%.*]] = select i1 [[C:%.*]], i8 0, i8 [[TMP1]]
+; CHECK-NEXT:    ret i8 [[R1]]
 ;
   %o = select i1 %c, i8 %Op1, i8 %FalseVal, !prof !0 ; while there, ensure preservation of prof md
   %r = sub i8 %o, %Op1
   ret i8 %r
 }
 define i8 @t1_sub_of_falseval(i1 %c, i8 %TrueVal, i8 %Op1) {
 ; CHECK-LABEL: @t1_sub_of_falseval(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i8 [[TRUEVAL:%.*]], [[OP1:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], i8 [[TMP1]], i8 0, !prof !0
-; CHECK-NEXT:    ret i8 [[R]]
+; CHECK-NEXT:    [[R1:%.*]] = select i1 [[C:%.*]], i8 [[TMP1]], i8 0
+; CHECK-NEXT:    ret i8 [[R1]]
 ;
   %o = select i1 %c, i8 %TrueVal, i8 %Op1, !prof !0 ; while there, ensure preservation of prof md
   %r = sub i8 %o, %Op1
   ret i8 %r
 }
 
 ; Vectors
 
 define <2 x i8> @t2_vec(i1 %c, <2 x i8> %Op1, <2 x i8> %FalseVal) {
 ; CHECK-LABEL: @t2_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i8> [[FALSEVAL:%.*]], [[OP1:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[C:%.*]], <2 x i8> zeroinitializer, <2 x i8> [[TMP1]]
-; CHECK-NEXT:    ret <2 x i8> [[R]]
+; CHECK-NEXT:    [[R1:%.*]] = select i1 [[C:%.*]], <2 x i8> zeroinitializer, <2 x i8> [[TMP1]]
+; CHECK-NEXT:    ret <2 x i8> [[R1]]
 ;
   %o = select i1 %c, <2 x i8> %Op1, <2 x i8> %FalseVal
   %r = sub <2 x i8> %o, %Op1
   ret <2 x i8> %r
 }
 
 ; Extra use
 

llvm/test/Transforms/InstCombine/widenable-conditions.ll

;
   %rhs = and i1 %wc, %c
   %and = and i1 %lhs, %rhs
   ret i1 %and
 }
 
 define i1 @test4_logical(i1 %a, i1 %b, i1 %c) {
 ; CHECK-LABEL: @test4_logical(
 ; CHECK-NEXT:    [[WC:%.*]] = call i1 @llvm.experimental.widenable.condition()
-; CHECK-NEXT:    [[LHS:%.*]] = select i1 [[A:%.*]], i1 [[B:%.*]], i1 false
-; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[LHS]], [[WC]]
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i1 [[C:%.*]], i1 false
+; CHECK-NEXT:    [[TMP1:%.*]] = and i1 [[WC]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[A:%.*]], i1 [[TMP1]], i1 false
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP2]], i1 [[C:%.*]], i1 false
 ; CHECK-NEXT:    ret i1 [[AND]]
 ;
   %wc = call i1 @llvm.experimental.widenable.condition()
   %lhs = select i1 %a, i1 %b, i1 false
   %rhs = select i1 %wc, i1 %c, i1 false
   %and = select i1 %lhs, i1 %rhs, i1 false
   ret i1 %and
 }

llvm/test/Transforms/InstCombine/with_overflow.ll

;
   %a = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 42, i32 %x)
   ret { i32, i1 } %a
 }
 
 ; Always overflow tests
 
 define { i8, i1 } @uadd_always_overflow(i8 %x) nounwind {
 ; CHECK-LABEL: @uadd_always_overflow(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], 63
-; CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[TMP1]], 0
-; CHECK-NEXT:    ret { i8, i1 } [[TMP2]]
+; CHECK-NEXT:    [[A:%.*]] = and i8 [[X:%.*]], 63
+; CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
+; CHECK-NEXT:    ret { i8, i1 } [[TMP1]]
 ;
   %y = or i8 %x, 192
   %a = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 %y, i8 64)
   ret { i8, i1 } %a
 }
 
 define { i8, i1 } @usub_always_overflow(i8 %x) nounwind {
 ; CHECK-LABEL: @usub_always_overflow(

 ;
   %y = or i8 %x, 128
   %a = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %y, i8 2)
   ret { i8, i1 } %a
 }
 
 define { i8, i1 } @sadd_always_overflow(i8 %x) nounwind {
 ; CHECK-LABEL: @sadd_always_overflow(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 100)
-; CHECK-NEXT:    [[A:%.*]] = add nuw i8 [[TMP1]], 28
-; CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
-; CHECK-NEXT:    ret { i8, i1 } [[TMP2]]
+; CHECK-NEXT:    [[Y:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 100)
+; CHECK-NEXT:    [[A:%.*]] = add nuw i8 [[Y]], 28
+; CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
+; CHECK-NEXT:    ret { i8, i1 } [[TMP1]]
 ;
   %c = icmp sgt i8 %x, 100
   %y = select i1 %c, i8 %x, i8 100
   %a = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %y, i8 28)
   ret { i8, i1 } %a
 }
 
 define { i8, i1 } @ssub_always_overflow(i8 %x) nounwind {
 ; CHECK-LABEL: @ssub_always_overflow(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 29)
-; CHECK-NEXT:    [[A:%.*]] = sub nuw i8 -100, [[TMP1]]
-; CHECK-NEXT:    [[TMP2:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
-; CHECK-NEXT:    ret { i8, i1 } [[TMP2]]
+; CHECK-NEXT:    [[Y:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 29)
+; CHECK-NEXT:    [[A:%.*]] = sub nuw i8 -100, [[Y]]
+; CHECK-NEXT:    [[TMP1:%.*]] = insertvalue { i8, i1 } { i8 poison, i1 true }, i8 [[A]], 0
+; CHECK-NEXT:    ret { i8, i1 } [[TMP1]]
 ;
   %c = icmp sgt i8 %x, 29
   %y = select i1 %c, i8 %x, i8 29
   %a = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 -100, i8 %y)
   ret { i8, i1 } %a
 }
 
 define { i8, i1 } @smul_always_overflow(i8 %x) nounwind {
 ; CHECK-LABEL: @smul_always_overflow(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 100)
-; CHECK-NEXT:    [[A:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[TMP1]], i8 2)
+; CHECK-NEXT:    [[Y:%.*]] = call i8 @llvm.smax.i8(i8 [[X:%.*]], i8 100)
+; CHECK-NEXT:    [[A:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[Y]], i8 2)
 ; CHECK-NEXT:    ret { i8, i1 } [[A]]
 ;
   %c = icmp sgt i8 %x, 100
   %y = select i1 %c, i8 %x, i8 100
   %a = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %y, i8 2)
   ret { i8, i1 } %a
 }