[PowerPC] Update `incr` after resetting the register in MI

[lkail]

Summary

After performing signed extension, we update the register in MI. We should also update incr register which is tracking the register in MI.

Fixes https://github.com/llvm/llvm-project/issues/61882.

[shchenz]

LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
   bool IsSignExtended =
       incr.isVirtual() && isSignExtended(*RegInfo.getVRegDef(incr), TII);
 
   if (CmpOpcode == PPC::CMPW && !IsSignExtended) {
     Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
     BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg)
         .addReg(MI.getOperand(3).getReg());
     MI.getOperand(3).setReg(ValueReg);
+    incr = ValueReg;
   }
   // If we support part-word atomic mnemonics, just use them
   if (Subtarget.hasPartwordAtomics())
     return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode, CmpOpcode,
                             CmpPred);
 
   // In 64 bit mode we have to use 64 bits for addresses, even though the
   // lwarx/stwcx are 32 bits.  With the 32-bit atomics we can use address

llvm/test/CodeGen/PowerPC/all-atomics.ll

 ; CHECK-NEXT:    li 3, 55
 ; CHECK-NEXT:    li 4, 66
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    isel 3, 4, 3, 5
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: atommax2:
 ; AIX32:       # %bb.0: # %entry
-; AIX32-NEXT:    li 6, 0
+; AIX32-NEXT:    li 7, 0
 ; AIX32-NEXT:    rlwinm 5, 3, 3, 27, 27
+; AIX32-NEXT:    extsh 6, 4
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    xori 5, 5, 16
-; AIX32-NEXT:    ori 6, 6, 65535
-; AIX32-NEXT:    slw 7, 4, 5
-; AIX32-NEXT:    slw 6, 6, 5
+; AIX32-NEXT:    ori 7, 7, 65535
+; AIX32-NEXT:    slw 8, 6, 5
+; AIX32-NEXT:    slw 7, 7, 5
 ; AIX32-NEXT:    rlwinm 3, 3, 0, 0, 29
-; AIX32-NEXT:    and 7, 7, 6
+; AIX32-NEXT:    and 8, 8, 7
 ; AIX32-NEXT:  L..BB9_1: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 8, 0, 3
-; AIX32-NEXT:    and 9, 8, 6
-; AIX32-NEXT:    srw 9, 9, 5
-; AIX32-NEXT:    extsh 9, 9
-; AIX32-NEXT:    cmpw 9, 4
+; AIX32-NEXT:    lwarx 9, 0, 3
+; AIX32-NEXT:    and 10, 9, 7
+; AIX32-NEXT:    srw 10, 10, 5
+; AIX32-NEXT:    extsh 10, 10
+; AIX32-NEXT:    cmpw 10, 6
 ; AIX32-NEXT:    bgt 0, L..BB9_3
 ; AIX32-NEXT:  # %bb.2: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    andc 9, 8, 6
-; AIX32-NEXT:    or 9, 7, 9
-; AIX32-NEXT:    stwcx. 9, 0, 3
+; AIX32-NEXT:    andc 10, 9, 7
+; AIX32-NEXT:    or 10, 8, 10
+; AIX32-NEXT:    stwcx. 10, 0, 3
 ; AIX32-NEXT:    bne 0, L..BB9_1
 ; AIX32-NEXT:  L..BB9_3: # %entry
-; AIX32-NEXT:    srw 3, 8, 5
+; AIX32-NEXT:    srw 3, 9, 5
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    clrlwi 3, 3, 16
 ; AIX32-NEXT:    extsh 3, 3
 ; AIX32-NEXT:    cmpw 3, 4
 ; AIX32-NEXT:    li 3, 55
 ; AIX32-NEXT:    li 4, 66
 ; AIX32-NEXT:    iselgt 3, 4, 3
 ; AIX32-NEXT:    blr

llvm/test/CodeGen/PowerPC/atomic-minmax.ll

 
 }
 
 define void @ae16min(ptr nocapture dereferenceable(4) %minimum, i16 %val) #0 {
 ; CHECK-LABEL: ae16min:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 5, 0
 ; CHECK-NEXT:    rlwinm 6, 3, 3, 27, 27
+; CHECK-NEXT:    extsh 4, 4
 ; CHECK-NEXT:    ori 7, 5, 65535
 ; CHECK-NEXT:    xori 5, 6, 16
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
 ; CHECK-NEXT:    slw 8, 4, 5
 ; CHECK-NEXT:    slw 6, 7, 5
-; CHECK-NEXT:    rldicr 3, 3, 0, 61
 ; CHECK-NEXT:    and 7, 8, 6
 ; CHECK-NEXT:  .LBB16_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 8, 0, 3
 ; CHECK-NEXT:    and 9, 8, 6
 ; CHECK-NEXT:    srw 9, 9, 5
 ; CHECK-NEXT:    extsh 9, 9
 ; CHECK-NEXT:    cmpw 9, 4

 
 }
 
 define void @ae16max(ptr nocapture dereferenceable(4) %minimum, i16 %val) #0 {
 ; CHECK-LABEL: ae16max:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 5, 0
 ; CHECK-NEXT:    rlwinm 6, 3, 3, 27, 27
+; CHECK-NEXT:    extsh 4, 4
 ; CHECK-NEXT:    ori 7, 5, 65535
 ; CHECK-NEXT:    xori 5, 6, 16
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
 ; CHECK-NEXT:    slw 8, 4, 5
 ; CHECK-NEXT:    slw 6, 7, 5
-; CHECK-NEXT:    rldicr 3, 3, 0, 61
 ; CHECK-NEXT:    and 7, 8, 6
 ; CHECK-NEXT:  .LBB17_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 8, 0, 3
 ; CHECK-NEXT:    and 9, 8, 6
 ; CHECK-NEXT:    srw 9, 9, 5
 ; CHECK-NEXT:    extsh 9, 9
 ; CHECK-NEXT:    cmpw 9, 4

 
 }
 
 define void @ae8min(ptr nocapture dereferenceable(4) %minimum, i8 %val) #0 {
 ; CHECK-LABEL: ae8min:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rlwinm 5, 3, 3, 27, 28
 ; CHECK-NEXT:    li 6, 255
+; CHECK-NEXT:    extsb 4, 4
 ; CHECK-NEXT:    xori 5, 5, 24
-; CHECK-NEXT:    rldicr 3, 3, 0, 61
 ; CHECK-NEXT:    slw 7, 4, 5
 ; CHECK-NEXT:    slw 6, 6, 5
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
 ; CHECK-NEXT:    and 7, 7, 6
 ; CHECK-NEXT:  .LBB20_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 8, 0, 3
 ; CHECK-NEXT:    and 9, 8, 6
 ; CHECK-NEXT:    srw 9, 9, 5
 ; CHECK-NEXT:    extsb 9, 9
 ; CHECK-NEXT:    cmpw 9, 4

 
 }
 
 define void @ae8max(ptr nocapture dereferenceable(4) %minimum, i8 %val) #0 {
 ; CHECK-LABEL: ae8max:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    rlwinm 5, 3, 3, 27, 28
 ; CHECK-NEXT:    li 6, 255
+; CHECK-NEXT:    extsb 4, 4
 ; CHECK-NEXT:    xori 5, 5, 24
-; CHECK-NEXT:    rldicr 3, 3, 0, 61
 ; CHECK-NEXT:    slw 7, 4, 5
 ; CHECK-NEXT:    slw 6, 6, 5
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
 ; CHECK-NEXT:    and 7, 7, 6
 ; CHECK-NEXT:  .LBB21_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 8, 0, 3
 ; CHECK-NEXT:    and 9, 8, 6
 ; CHECK-NEXT:    srw 9, 9, 5
 ; CHECK-NEXT:    extsb 9, 9
 ; CHECK-NEXT:    cmpw 9, 4

llvm/test/CodeGen/PowerPC/pr61882.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mtriple=powerpc \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mtriple=powerpc \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=PWR8
 
 define void @foo(ptr %a, i32 %x) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rlwinm r5, r3, 3, 27, 28
 ; CHECK-NEXT:    li r6, 255
+; CHECK-NEXT:    extsb r4, r4
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:    xori r5, r5, 24
 ; CHECK-NEXT:    rlwinm r3, r3, 0, 0, 29
 ; CHECK-NEXT:    slw r7, r4, r5
 ; CHECK-NEXT:    slw r6, r6, r5
 ; CHECK-NEXT:    and r7, r7, r6
 ; CHECK-NEXT:  .LBB0_1:
 ; CHECK-NEXT:    lwarx r8, 0, r3