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Differential D147409

Add baseline tests for D147404
ClosedPublic

Authored by junaire on Apr 2 2023, 2:36 AM.

Details

Reviewers
RKSimon
pengfei
dmgreen
Commits
rG2b9330e41f54: Add baseline tests for D147404
Summary

Signed-off-by: Jun Zhang <jun@junz.org>

Diff Detail

Event Timeline

junaire created this revision.Apr 2 2023, 2:36 AM
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junaire requested review of this revision.Apr 2 2023, 2:36 AM
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junaire added a child revision: D147404: [DAGCombiner] Fold avg(x, x) --> x.Apr 2 2023, 2:37 AM
Harbormaster completed remote builds in B223237: Diff 510327.Apr 2 2023, 3:23 AM
dmgreen added a comment.Apr 2 2023, 3:48 AM

Sounds good. Can you add these to the existing hadd-combine.ll file instead, and add aarch64.neon.shadd/uhadd/urhadd variants too? AArch64 uses hadd/rhadd names, as opposed to avg like X86.

llvm/test/CodeGen/AArch64/avg.ll
22 ↗(On Diff #510327)

v2i16 -> v2i32

junaire updated this revision to Diff 510337.Apr 2 2023, 4:59 AM

Add all rest variants

Harbormaster completed remote builds in B223246: Diff 510337.Apr 2 2023, 5:48 AM
dmgreen added a comment.Apr 3 2023, 1:11 AM

Thanks for adding the extra tests. Do you mind moving them to llvm/test/CodeGen/AArch64/hadd-combine.ll, so that they are with the other combine tests we have.

junaire updated this revision to Diff 510427.Apr 3 2023, 1:54 AM

Address @dmgreen's comments, thanks!

dmgreen accepted this revision.Apr 3 2023, 1:56 AM

Thanks. LGTM

This revision is now accepted and ready to land.Apr 3 2023, 1:56 AM
This revision was landed with ongoing or failed builds.Apr 3 2023, 1:58 AM
Closed by commit rG2b9330e41f54: Add baseline tests for D147404 (authored by junaire). · Explain Why
This revision was automatically updated to reflect the committed changes.
junaire added a commit: rG2b9330e41f54: Add baseline tests for D147404.
Harbormaster completed remote builds in B223308: Diff 510427.Apr 3 2023, 2:41 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
AArch64/
245 lines

Diff 510431

llvm/test/CodeGen/AArch64/hadd-combine.ll

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%result = trunc <8 x i32> %resulti16 to <8 x i16> %result = trunc <8 x i32> %resulti16 to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @hadds_const_bothhigh() { define <8 x i16> @hadds_const_bothhigh() {
; CHECK-LABEL: hadds_const_bothhigh: ; CHECK-LABEL: hadds_const_bothhigh:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32766 ; CHECK-NEXT: mov w8, #32766 // =0x7ffe
; CHECK-NEXT: dup v0.8h, w8 ; CHECK-NEXT: dup v0.8h, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ext1 = sext <8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766> to <8 x i32> %ext1 = sext <8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766> to <8 x i32>
%ext2 = sext <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767> to <8 x i32> %ext2 = sext <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767> to <8 x i32>
%add = add <8 x i32> %ext1, %ext2 %add = add <8 x i32> %ext1, %ext2
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%result = trunc <8 x i32> %resulti16 to <8 x i16> %result = trunc <8 x i32> %resulti16 to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>) %result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @hadds_i_const_bothhigh() { define <8 x i16> @hadds_i_const_bothhigh() {
; CHECK-LABEL: hadds_i_const_bothhigh: ; CHECK-LABEL: hadds_i_const_bothhigh:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32766 ; CHECK-NEXT: mov w8, #32766 // =0x7ffe
; CHECK-NEXT: dup v0.8h, w8 ; CHECK-NEXT: dup v0.8h, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>) %result = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>)
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @hadds_i_undef(<8 x i16> %t, <8 x i16> %src1) { define <8 x i16> @hadds_i_undef(<8 x i16> %t, <8 x i16> %src1) {
; CHECK-LABEL: hadds_i_undef: ; CHECK-LABEL: hadds_i_undef:
▲ Show 20 Lines • Show All 337 Lines • ▼ Show 20 Lines
; CHECK-LABEL: rhadds_i_undef: ; CHECK-LABEL: rhadds_i_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> undef, <8 x i16> %src1) %result = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> undef, <8 x i16> %src1)
ret <8 x i16> %result ret <8 x i16> %result
} }
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
define <8 x i8> @shadd_v8i8(<8 x i8> %x) {
; CHECK-LABEL: shadd_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: shadd v0.8b, v0.8b, v0.8b
; CHECK-NEXT: ret
%r = tail call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %x, <8 x i8> %x)
ret <8 x i8> %r
}
define <4 x i16> @shadd_v4i16(<4 x i16> %x) {
; CHECK-LABEL: shadd_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: shadd v0.4h, v0.4h, v0.4h
; CHECK-NEXT: ret
%r = tail call <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16> %x, <4 x i16> %x)
ret <4 x i16> %r
}
define <2 x i32> @shadd_v2i32(<2 x i32> %x) {
; CHECK-LABEL: shadd_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: shadd v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%r = tail call <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32> %x, <2 x i32> %x)
ret <2 x i32> %r
}
define <16 x i8> @shadd_v16i8(<16 x i8> %x) {
; CHECK-LABEL: shadd_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: shadd v0.16b, v0.16b, v0.16b
; CHECK-NEXT: ret
%r = tail call <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8> %x, <16 x i8> %x)
ret <16 x i8> %r
}
define <8 x i16> @shadd_v8i16(<8 x i16> %x) {
; CHECK-LABEL: shadd_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: shadd v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ret
%r = tail call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x, <8 x i16> %x)
ret <8 x i16> %r
}
define <4 x i32> @shadd_v4i32(<4 x i32> %x) {
; CHECK-LABEL: shadd_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: shadd v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ret
%r = tail call <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32> %x, <4 x i32> %x)
ret <4 x i32> %r
}
define <8 x i8> @uhadd_v8i8(<8 x i8> %x) {
; CHECK-LABEL: uhadd_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: uhadd v0.8b, v0.8b, v0.8b
; CHECK-NEXT: ret
%r = tail call <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
ret <8 x i8> %r
}
define <4 x i16> @uhadd_v4i16(<4 x i16> %x) {
; CHECK-LABEL: uhadd_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: uhadd v0.4h, v0.4h, v0.4h
; CHECK-NEXT: ret
%r = tail call <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
ret <4 x i16> %r
}
define <2 x i32> @uhadd_v2i32(<2 x i32> %x) {
; CHECK-LABEL: uhadd_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: uhadd v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%r = tail call <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
ret <2 x i32> %r
}
define <16 x i8> @uhadd_v16i8(<16 x i8> %x) {
; CHECK-LABEL: uhadd_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: uhadd v0.16b, v0.16b, v0.16b
; CHECK-NEXT: ret
%r = tail call <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
ret <16 x i8> %r
}
define <8 x i16> @uhadd_v8i16(<8 x i16> %x) {
; CHECK-LABEL: uhadd_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: uhadd v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ret
%r = tail call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
ret <8 x i16> %r
}
define <4 x i32> @uhadd_v4i32(<4 x i32> %x) {
; CHECK-LABEL: uhadd_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: uhadd v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ret
%r = tail call <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
ret <4 x i32> %r
}
define <8 x i8> @srhadd_v8i8(<8 x i8> %x) {
; CHECK-LABEL: srhadd_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: srhadd v0.8b, v0.8b, v0.8b
; CHECK-NEXT: ret
%r = tail call <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
ret <8 x i8> %r
}
define <4 x i16> @srhadd_v4i16(<4 x i16> %x) {
; CHECK-LABEL: srhadd_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: srhadd v0.4h, v0.4h, v0.4h
; CHECK-NEXT: ret
%r = tail call <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
ret <4 x i16> %r
}
define <2 x i32> @srhadd_v2i32(<2 x i32> %x) {
; CHECK-LABEL: srhadd_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: srhadd v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%r = tail call <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
ret <2 x i32> %r
}
define <16 x i8> @srhadd_v16i8(<16 x i8> %x) {
; CHECK-LABEL: srhadd_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: srhadd v0.16b, v0.16b, v0.16b
; CHECK-NEXT: ret
%r = tail call <16 x i8> @llvm.aarch64.neon.srhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
ret <16 x i8> %r
}
define <8 x i16> @srhadd_v8i16(<8 x i16> %x) {
; CHECK-LABEL: srhadd_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: srhadd v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ret
%r = tail call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
ret <8 x i16> %r
}
define <4 x i32> @srhadd_v4i32(<4 x i32> %x) {
; CHECK-LABEL: srhadd_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: srhadd v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ret
%r = tail call <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
ret <4 x i32> %r
}
define <8 x i8> @urhadd_v8i8(<8 x i8> %x) {
; CHECK-LABEL: urhadd_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: urhadd v0.8b, v0.8b, v0.8b
; CHECK-NEXT: ret
%r = tail call <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
ret <8 x i8> %r
}
define <4 x i16> @urhadd_v4i16(<4 x i16> %x) {
; CHECK-LABEL: urhadd_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: urhadd v0.4h, v0.4h, v0.4h
; CHECK-NEXT: ret
%r = tail call <4 x i16> @llvm.aarch64.neon.urhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
ret <4 x i16> %r
}
define <2 x i32> @urhadd_v2i32(<2 x i32> %x) {
; CHECK-LABEL: urhadd_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: urhadd v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%r = tail call <2 x i32> @llvm.aarch64.neon.urhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
ret <2 x i32> %r
}
define <16 x i8> @urhadd_v16i8(<16 x i8> %x) {
; CHECK-LABEL: urhadd_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: urhadd v0.16b, v0.16b, v0.16b
; CHECK-NEXT: ret
%r = tail call <16 x i8> @llvm.aarch64.neon.urhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
ret <16 x i8> %r
}
define <8 x i16> @urhadd_v8i16(<8 x i16> %x) {
; CHECK-LABEL: urhadd_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: urhadd v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ret
%r = tail call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
ret <8 x i16> %r
}
define <4 x i32> @urhadd_v4i32(<4 x i32> %x) {
; CHECK-LABEL: urhadd_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: urhadd v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ret
%r = tail call <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
ret <4 x i32> %r
}
declare <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8>, <8 x i8>)
declare <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16>, <4 x i16>)
declare <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32>, <2 x i32>)
declare <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8>, <8 x i8>)
declare <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16>, <4 x i16>)
declare <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32>, <2 x i32>)
declare <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8>, <16 x i8>)
declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)
declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>) declare <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32>, <4 x i32>)
declare <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8>, <16 x i8>)
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
declare <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32>, <4 x i32>)
declare <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>)
declare <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16>, <4 x i16>)
declare <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32>, <2 x i32>)
declare <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8>, <8 x i8>)
declare <4 x i16> @llvm.aarch64.neon.urhadd.v4i16(<4 x i16>, <4 x i16>)
declare <2 x i32> @llvm.aarch64.neon.urhadd.v2i32(<2 x i32>, <2 x i32>)
declare <16 x i8> @llvm.aarch64.neon.srhadd.v16i8(<16 x i8>, <16 x i8>)
declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)
declare <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32>, <4 x i32>)
declare <16 x i8> @llvm.aarch64.neon.urhadd.v16i8(<16 x i8>, <16 x i8>)
declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)
declare <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32>, <4 x i32>)