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Differential D147398

[LoongArch][NFC] Add tests of multiplication with immediates (for D147400)
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Authored by benshi001 on Apr 1 2023, 9:37 PM.

Details

Reviewers
SixWeining
XiaodongLoong
xen0n
wangleiat
Commits
rG6d0e9c269c83: [LoongArch][NFC] Add tests of multiplication with immediates

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Event Timeline

benshi001 created this revision.Apr 1 2023, 9:37 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 1 2023, 9:37 PM
benshi001 requested review of this revision.Apr 1 2023, 9:37 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 1 2023, 9:37 PM
Herald added subscribers: llvm-commits, jacquesguan. · View Herald Transcript
benshi001 updated this revision to Diff 510299.Apr 1 2023, 10:17 PM
benshi001 added a child revision: D147400: [LoongArch] Optimize multiplication with immediates.Apr 1 2023, 10:19 PM
benshi001 retitled this revision from [LoongArch][NFC] Add tests of multiplication with immediates to [LoongArch][NFC] Add tests of multiplication with immediates (for D147400).Apr 1 2023, 10:23 PM
Harbormaster completed remote builds in B223213: Diff 510299.Apr 1 2023, 11:02 PM
xen0n accepted this revision.Apr 2 2023, 12:51 AM

Thanks!

This revision is now accepted and ready to land.Apr 2 2023, 12:51 AM
benshi001 added a child revision: D147405: [LoongArch][NFC] Add tests of multiplication with immediates (for D147406).Apr 2 2023, 1:12 AM
SixWeining accepted this revision.Apr 2 2023, 6:07 AM
This revision was landed with ongoing or failed builds.Apr 2 2023, 7:13 AM
Closed by commit rG6d0e9c269c83: [LoongArch][NFC] Add tests of multiplication with immediates (authored by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG6d0e9c269c83: [LoongArch][NFC] Add tests of multiplication with immediates.

Revision Contents

PathSize
llvm/
test/
CodeGen/
LoongArch/
ir-instruction/
253 lines

Diff 510295

llvm/test/CodeGen/LoongArch/ir-instruction/mul.ll

Show First 20 Lines • Show All 359 Lines • ▼ Show 20 Lines
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.w $a1, $a0, $a0, 1 ; LA64-NEXT: alsl.w $a1, $a0, $a0, 1
; LA64-NEXT: alsl.w $a0, $a1, $a0, 3 ; LA64-NEXT: alsl.w $a0, $a1, $a0, 3
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i32 %a, 25 %b = mul i32 %a, 25
ret i32 %b ret i32 %b
} }
define signext i32 @mul_i32_27(i32 %a) {
; LA32-LABEL: mul_i32_27:
; LA32: # %bb.0:
; LA32-NEXT: ori $a1, $zero, 27
; LA32-NEXT: mul.w $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i32_27:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 27
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: ret
%b = mul i32 %a, 27
ret i32 %b
}
define signext i32 @mul_i32_33(i32 %a) {
; LA32-LABEL: mul_i32_33:
; LA32: # %bb.0:
; LA32-NEXT: slli.w $a1, $a0, 5
; LA32-NEXT: add.w $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i32_33:
; LA64: # %bb.0:
; LA64-NEXT: slli.d $a1, $a0, 5
; LA64-NEXT: add.w $a0, $a1, $a0
; LA64-NEXT: ret
%b = mul i32 %a, 33
ret i32 %b
}
define signext i32 @mul_i32_35(i32 %a) { define signext i32 @mul_i32_35(i32 %a) {
; LA32-LABEL: mul_i32_35: ; LA32-LABEL: mul_i32_35:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: alsl.w $a1, $a0, $a0, 4 ; LA32-NEXT: alsl.w $a1, $a0, $a0, 4
; LA32-NEXT: alsl.w $a0, $a1, $a0, 1 ; LA32-NEXT: alsl.w $a0, $a1, $a0, 1
; LA32-NEXT: ret ; LA32-NEXT: ret
; ;
; LA64-LABEL: mul_i32_35: ; LA64-LABEL: mul_i32_35:
Show All 32 Lines
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.w $a1, $a0, $a0, 2 ; LA64-NEXT: alsl.w $a1, $a0, $a0, 2
; LA64-NEXT: alsl.w $a0, $a1, $a0, 3 ; LA64-NEXT: alsl.w $a0, $a1, $a0, 3
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i32 %a, 41 %b = mul i32 %a, 41
ret i32 %b ret i32 %b
} }
define signext i32 @mul_i32_45(i32 %a) {
; LA32-LABEL: mul_i32_45:
; LA32: # %bb.0:
; LA32-NEXT: ori $a1, $zero, 45
; LA32-NEXT: mul.w $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i32_45:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 45
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: ret
%b = mul i32 %a, 45
ret i32 %b
}
define signext i32 @mul_i32_49(i32 %a) { define signext i32 @mul_i32_49(i32 %a) {
; LA32-LABEL: mul_i32_49: ; LA32-LABEL: mul_i32_49:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: alsl.w $a1, $a0, $a0, 1 ; LA32-NEXT: alsl.w $a1, $a0, $a0, 1
; LA32-NEXT: alsl.w $a0, $a1, $a0, 4 ; LA32-NEXT: alsl.w $a0, $a1, $a0, 4
; LA32-NEXT: ret ; LA32-NEXT: ret
; ;
; LA64-LABEL: mul_i32_49: ; LA64-LABEL: mul_i32_49:
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.w $a1, $a0, $a0, 1 ; LA64-NEXT: alsl.w $a1, $a0, $a0, 1
; LA64-NEXT: alsl.w $a0, $a1, $a0, 4 ; LA64-NEXT: alsl.w $a0, $a1, $a0, 4
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i32 %a, 49 %b = mul i32 %a, 49
ret i32 %b ret i32 %b
} }
define signext i32 @mul_i32_51(i32 %a) {
; LA32-LABEL: mul_i32_51:
; LA32: # %bb.0:
; LA32-NEXT: ori $a1, $zero, 51
; LA32-NEXT: mul.w $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i32_51:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 51
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: ret
%b = mul i32 %a, 51
ret i32 %b
}
define signext i32 @mul_i32_69(i32 %a) { define signext i32 @mul_i32_69(i32 %a) {
; LA32-LABEL: mul_i32_69: ; LA32-LABEL: mul_i32_69:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: alsl.w $a1, $a0, $a0, 4 ; LA32-NEXT: alsl.w $a1, $a0, $a0, 4
; LA32-NEXT: alsl.w $a0, $a1, $a0, 2 ; LA32-NEXT: alsl.w $a0, $a1, $a0, 2
; LA32-NEXT: ret ; LA32-NEXT: ret
; ;
; LA64-LABEL: mul_i32_69: ; LA64-LABEL: mul_i32_69:
Show All 32 Lines
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.w $a1, $a0, $a0, 2 ; LA64-NEXT: alsl.w $a1, $a0, $a0, 2
; LA64-NEXT: alsl.w $a0, $a1, $a0, 4 ; LA64-NEXT: alsl.w $a0, $a1, $a0, 4
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i32 %a, 81 %b = mul i32 %a, 81
ret i32 %b ret i32 %b
} }
define signext i32 @mul_i32_85(i32 %a) {
; LA32-LABEL: mul_i32_85:
; LA32: # %bb.0:
; LA32-NEXT: ori $a1, $zero, 85
; LA32-NEXT: mul.w $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i32_85:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 85
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: ret
%b = mul i32 %a, 85
ret i32 %b
}
define signext i32 @mul_i32_137(i32 %a) { define signext i32 @mul_i32_137(i32 %a) {
; LA32-LABEL: mul_i32_137: ; LA32-LABEL: mul_i32_137:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: alsl.w $a1, $a0, $a0, 4 ; LA32-NEXT: alsl.w $a1, $a0, $a0, 4
; LA32-NEXT: alsl.w $a0, $a1, $a0, 3 ; LA32-NEXT: alsl.w $a0, $a1, $a0, 3
; LA32-NEXT: ret ; LA32-NEXT: ret
; ;
; LA64-LABEL: mul_i32_137: ; LA64-LABEL: mul_i32_137:
Show All 16 Lines
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.w $a1, $a0, $a0, 3 ; LA64-NEXT: alsl.w $a1, $a0, $a0, 3
; LA64-NEXT: alsl.w $a0, $a1, $a0, 4 ; LA64-NEXT: alsl.w $a0, $a1, $a0, 4
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i32 %a, 145 %b = mul i32 %a, 145
ret i32 %b ret i32 %b
} }
define signext i32 @mul_i32_153(i32 %a) {
; LA32-LABEL: mul_i32_153:
; LA32: # %bb.0:
; LA32-NEXT: ori $a1, $zero, 153
; LA32-NEXT: mul.w $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i32_153:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 153
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: ret
%b = mul i32 %a, 153
ret i32 %b
}
define signext i32 @mul_i32_273(i32 %a) { define signext i32 @mul_i32_273(i32 %a) {
; LA32-LABEL: mul_i32_273: ; LA32-LABEL: mul_i32_273:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: alsl.w $a1, $a0, $a0, 4 ; LA32-NEXT: alsl.w $a1, $a0, $a0, 4
; LA32-NEXT: alsl.w $a0, $a1, $a0, 4 ; LA32-NEXT: alsl.w $a0, $a1, $a0, 4
; LA32-NEXT: ret ; LA32-NEXT: ret
; ;
; LA64-LABEL: mul_i32_273: ; LA64-LABEL: mul_i32_273:
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.w $a1, $a0, $a0, 4 ; LA64-NEXT: alsl.w $a1, $a0, $a0, 4
; LA64-NEXT: alsl.w $a0, $a1, $a0, 4 ; LA64-NEXT: alsl.w $a0, $a1, $a0, 4
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i32 %a, 273 %b = mul i32 %a, 273
ret i32 %b ret i32 %b
} }
define signext i32 @mul_i32_289(i32 %a) {
; LA32-LABEL: mul_i32_289:
; LA32: # %bb.0:
; LA32-NEXT: ori $a1, $zero, 289
; LA32-NEXT: mul.w $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i32_289:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 289
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: addi.w $a0, $a0, 0
; LA64-NEXT: ret
%b = mul i32 %a, 289
ret i32 %b
}
define i64 @mul_i64_11(i64 %a) { define i64 @mul_i64_11(i64 %a) {
; LA32-LABEL: mul_i64_11: ; LA32-LABEL: mul_i64_11:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 11 ; LA32-NEXT: ori $a2, $zero, 11
; LA32-NEXT: mul.w $a1, $a1, $a2 ; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2 ; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1 ; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2 ; LA32-NEXT: mul.w $a0, $a0, $a2
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.d $a1, $a0, $a0, 1 ; LA64-NEXT: alsl.d $a1, $a0, $a0, 1
; LA64-NEXT: alsl.d $a0, $a1, $a0, 3 ; LA64-NEXT: alsl.d $a0, $a1, $a0, 3
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i64 %a, 25 %b = mul i64 %a, 25
ret i64 %b ret i64 %b
} }
define i64 @mul_i64_27(i64 %a) {
; LA32-LABEL: mul_i64_27:
; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 27
; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i64_27:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 27
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: ret
%b = mul i64 %a, 27
ret i64 %b
}
define i64 @mul_i64_33(i64 %a) {
; LA32-LABEL: mul_i64_33:
; LA32: # %bb.0:
; LA32-NEXT: slli.w $a2, $a1, 5
; LA32-NEXT: add.w $a1, $a2, $a1
; LA32-NEXT: ori $a2, $zero, 33
; LA32-NEXT: mulh.wu $a2, $a0, $a2
; LA32-NEXT: add.w $a1, $a2, $a1
; LA32-NEXT: slli.w $a2, $a0, 5
; LA32-NEXT: add.w $a0, $a2, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i64_33:
; LA64: # %bb.0:
; LA64-NEXT: slli.d $a1, $a0, 5
; LA64-NEXT: add.d $a0, $a1, $a0
; LA64-NEXT: ret
%b = mul i64 %a, 33
ret i64 %b
}
define i64 @mul_i64_35(i64 %a) { define i64 @mul_i64_35(i64 %a) {
; LA32-LABEL: mul_i64_35: ; LA32-LABEL: mul_i64_35:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 35 ; LA32-NEXT: ori $a2, $zero, 35
; LA32-NEXT: mul.w $a1, $a1, $a2 ; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2 ; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1 ; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2 ; LA32-NEXT: mul.w $a0, $a0, $a2
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.d $a1, $a0, $a0, 2 ; LA64-NEXT: alsl.d $a1, $a0, $a0, 2
; LA64-NEXT: alsl.d $a0, $a1, $a0, 3 ; LA64-NEXT: alsl.d $a0, $a1, $a0, 3
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i64 %a, 41 %b = mul i64 %a, 41
ret i64 %b ret i64 %b
} }
define i64 @mul_i64_45(i64 %a) {
; LA32-LABEL: mul_i64_45:
; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 45
; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i64_45:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 45
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: ret
%b = mul i64 %a, 45
ret i64 %b
}
define i64 @mul_i64_49(i64 %a) { define i64 @mul_i64_49(i64 %a) {
; LA32-LABEL: mul_i64_49: ; LA32-LABEL: mul_i64_49:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 49 ; LA32-NEXT: ori $a2, $zero, 49
; LA32-NEXT: mul.w $a1, $a1, $a2 ; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2 ; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1 ; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2 ; LA32-NEXT: mul.w $a0, $a0, $a2
; LA32-NEXT: ret ; LA32-NEXT: ret
; ;
; LA64-LABEL: mul_i64_49: ; LA64-LABEL: mul_i64_49:
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.d $a1, $a0, $a0, 1 ; LA64-NEXT: alsl.d $a1, $a0, $a0, 1
; LA64-NEXT: alsl.d $a0, $a1, $a0, 4 ; LA64-NEXT: alsl.d $a0, $a1, $a0, 4
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i64 %a, 49 %b = mul i64 %a, 49
ret i64 %b ret i64 %b
} }
define i64 @mul_i64_51(i64 %a) {
; LA32-LABEL: mul_i64_51:
; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 51
; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i64_51:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 51
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: ret
%b = mul i64 %a, 51
ret i64 %b
}
define i64 @mul_i64_69(i64 %a) { define i64 @mul_i64_69(i64 %a) {
; LA32-LABEL: mul_i64_69: ; LA32-LABEL: mul_i64_69:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 69 ; LA32-NEXT: ori $a2, $zero, 69
; LA32-NEXT: mul.w $a1, $a1, $a2 ; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2 ; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1 ; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2 ; LA32-NEXT: mul.w $a0, $a0, $a2
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.d $a1, $a0, $a0, 2 ; LA64-NEXT: alsl.d $a1, $a0, $a0, 2
; LA64-NEXT: alsl.d $a0, $a1, $a0, 4 ; LA64-NEXT: alsl.d $a0, $a1, $a0, 4
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i64 %a, 81 %b = mul i64 %a, 81
ret i64 %b ret i64 %b
} }
define i64 @mul_i64_85(i64 %a) {
; LA32-LABEL: mul_i64_85:
; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 85
; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i64_85:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 85
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: ret
%b = mul i64 %a, 85
ret i64 %b
}
define i64 @mul_i64_137(i64 %a) { define i64 @mul_i64_137(i64 %a) {
; LA32-LABEL: mul_i64_137: ; LA32-LABEL: mul_i64_137:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 137 ; LA32-NEXT: ori $a2, $zero, 137
; LA32-NEXT: mul.w $a1, $a1, $a2 ; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2 ; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1 ; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2 ; LA32-NEXT: mul.w $a0, $a0, $a2
Show All 22 Lines
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.d $a1, $a0, $a0, 3 ; LA64-NEXT: alsl.d $a1, $a0, $a0, 3
; LA64-NEXT: alsl.d $a0, $a1, $a0, 4 ; LA64-NEXT: alsl.d $a0, $a1, $a0, 4
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i64 %a, 145 %b = mul i64 %a, 145
ret i64 %b ret i64 %b
} }
define i64 @mul_i64_153(i64 %a) {
; LA32-LABEL: mul_i64_153:
; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 153
; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i64_153:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 153
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: ret
%b = mul i64 %a, 153
ret i64 %b
}
define i64 @mul_i64_273(i64 %a) { define i64 @mul_i64_273(i64 %a) {
; LA32-LABEL: mul_i64_273: ; LA32-LABEL: mul_i64_273:
; LA32: # %bb.0: ; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 273 ; LA32-NEXT: ori $a2, $zero, 273
; LA32-NEXT: mul.w $a1, $a1, $a2 ; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2 ; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1 ; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2 ; LA32-NEXT: mul.w $a0, $a0, $a2
; LA32-NEXT: ret ; LA32-NEXT: ret
; ;
; LA64-LABEL: mul_i64_273: ; LA64-LABEL: mul_i64_273:
; LA64: # %bb.0: ; LA64: # %bb.0:
; LA64-NEXT: alsl.d $a1, $a0, $a0, 4 ; LA64-NEXT: alsl.d $a1, $a0, $a0, 4
; LA64-NEXT: alsl.d $a0, $a1, $a0, 4 ; LA64-NEXT: alsl.d $a0, $a1, $a0, 4
; LA64-NEXT: ret ; LA64-NEXT: ret
%b = mul i64 %a, 273 %b = mul i64 %a, 273
ret i64 %b ret i64 %b
} }
define i64 @mul_i64_289(i64 %a) {
; LA32-LABEL: mul_i64_289:
; LA32: # %bb.0:
; LA32-NEXT: ori $a2, $zero, 289
; LA32-NEXT: mul.w $a1, $a1, $a2
; LA32-NEXT: mulh.wu $a3, $a0, $a2
; LA32-NEXT: add.w $a1, $a3, $a1
; LA32-NEXT: mul.w $a0, $a0, $a2
; LA32-NEXT: ret
;
; LA64-LABEL: mul_i64_289:
; LA64: # %bb.0:
; LA64-NEXT: ori $a1, $zero, 289
; LA64-NEXT: mul.d $a0, $a0, $a1
; LA64-NEXT: ret
%b = mul i64 %a, 289
ret i64 %b
}