[LoongArch] Optimize additions with immediates

[benshi001]

llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll

125–126

This is also a win, since one register is saved.

[xen0n]

Typo in title: "immediates".

Otherwise LGTM, thanks!

[SixWeining]

LGTM. Thanks for the improvements.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

 def AddrConstant : ComplexPattern<iPTR, 2, "SelectAddrConstant">;
 def NonFIBaseAddr : ComplexPattern<iPTR, 1, "selectNonFIBaseAddr">;
 
 def fma_nsz : PatFrag<(ops node:$fj, node:$fk, node:$fa),
                       (fma node:$fj, node:$fk, node:$fa), [{
   return N->getFlags().hasNoSignedZeros();
 }]>;
 
+// Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
+// in which imm = imm0 + imm1, and both imm0 & imm1 are simm12.
+def AddiPair : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  // The immediate operand must be in range [-4096,-2049] or [2048,4094].
+  int64_t Imm = N->getSExtValue();
+  return (-4096 <= Imm && Imm <= -2049) || (2048 <= Imm && Imm <= 4094);
+}]>;
+
+// Return -2048 if immediate is negative or 2047 if positive.
+def AddiPairImmLarge : SDNodeXForm<imm, [{
+  int64_t Imm = N->getSExtValue() < 0 ? -2048 : 2047;
+  return CurDAG->getTargetConstant(Imm, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+// Return imm - (imm < 0 ? -2048 : 2047).
+def AddiPairImmSmall : SDNodeXForm<imm, [{
+  int64_t Imm = N->getSExtValue();
+  int64_t Adj = Imm < 0 ? -2048 : 2047;
+  return CurDAG->getTargetConstant(Imm - Adj, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
 include "LoongArchInstrFormats.td"
 include "LoongArchFloatInstrFormats.td"
 
 //===----------------------------------------------------------------------===//
def : Pat<(add GPR:$rj, simm16_lsl16:$imm),
           (ADDU16I_D GPR:$rj, (HI16 $imm))>;
 def : Pat<(add GPR:$rj, simm32_hi16_lo12:$imm),
           (ADDI_D (ADDU16I_D GPR:$rj, (HI16ForAddu16idAddiPair $imm)),
                   (LO12 $imm))>;
 def : Pat<(sext_inreg (add GPR:$rj, simm32_hi16_lo12:$imm), i32),
           (ADDI_W (ADDU16I_D GPR:$rj, (HI16ForAddu16idAddiPair $imm)),
                   (LO12 $imm))>;
 
+let Predicates = [IsLA32] in {
+def : Pat<(add GPR:$rj, (AddiPair:$im)),
+          (ADDI_W (ADDI_W GPR:$rj, (AddiPairImmLarge AddiPair:$im)),
+                  (AddiPairImmSmall AddiPair:$im))>;
+} // Predicates = [IsLA32]
+
+let Predicates = [IsLA64] in {
+def : Pat<(add GPR:$rj, (AddiPair:$im)),
+          (ADDI_D (ADDI_D GPR:$rj, (AddiPairImmLarge AddiPair:$im)),
+                  (AddiPairImmSmall AddiPair:$im))>;
+def : Pat<(sext_inreg (add GPR:$rj, (AddiPair:$im)), i32),
+          (ADDI_W (ADDI_W GPR:$rj, (AddiPairImmLarge AddiPair:$im)),
+                  (AddiPairImmSmall AddiPair:$im))>;
+} // Predicates = [IsLA64]
+
 foreach Idx = 1...7 in {
   defvar ShamtA = !mul(8, Idx);
   defvar ShamtB = !mul(8, !sub(8, Idx));
   def : Pat<(or (shl GPR:$rk, (i64 ShamtA)), (srl GPR:$rj, (i64 ShamtB))),
             (BYTEPICK_D GPR:$rj, GPR:$rk, Idx)>;
 }
 
 foreach Idx = 1...3 in {

llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
 
 define i32 @m_offset_neg_2049(ptr %p) nounwind {
 ; LA32-LABEL: m_offset_neg_2049:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a1, -1
-; LA32-NEXT:    ori $a1, $a1, 2047
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, -2048
+; LA32-NEXT:    addi.w $a0, $a0, -1
 ; LA32-NEXT:    #APP
 ; LA32-NEXT:    ld.w $a0, $a0, 0
 ; LA32-NEXT:    #NO_APP
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: m_offset_neg_2049:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -1
-; LA64-NEXT:    ori $a1, $a1, 2047
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addi.d $a0, $a0, -2048
+; LA64-NEXT:    addi.d $a0, $a0, -1
 ; LA64-NEXT:    #APP
 ; LA64-NEXT:    ld.w $a0, $a0, 0
 ; LA64-NEXT:    #NO_APP
 ; LA64-NEXT:    ret
   %1 = getelementptr inbounds i8, ptr %p, i32 -2049
   %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
   ret i32 %2
 }
; LA64-NEXT:    ret
   %1 = getelementptr inbounds i8, ptr %p, i32 2047
   %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
   ret i32 %2
 }
 
 define i32 @m_offset_2048(ptr %p) nounwind {
 ; LA32-LABEL: m_offset_2048:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a1, $zero, 2048
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, 2047
+; LA32-NEXT:    addi.w $a0, $a0, 1
 ; LA32-NEXT:    #APP
 ; LA32-NEXT:    ld.w $a0, $a0, 0
 ; LA32-NEXT:    #NO_APP
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: m_offset_2048:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a1, $zero, 2048
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addi.d $a0, $a0, 2047
+; LA64-NEXT:    addi.d $a0, $a0, 1
 ; LA64-NEXT:    #APP
 ; LA64-NEXT:    ld.w $a0, $a0, 0
 ; LA64-NEXT:    #NO_APP
 ; LA64-NEXT:    ret
   %1 = getelementptr inbounds i8, ptr %p, i32 2048
   %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
   ret i32 %2
 }

llvm/test/CodeGen/LoongArch/ir-instruction/add.ll

 ; LA64-NEXT:    ret
   %add = add i32 %x, -2147485696
   ret i32 %add
 }
 
 define signext i32 @add_i32_4080(i32 %x) {
 ; LA32-LABEL: add_i32_4080:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a1, $zero, 4080
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, 2047
+; LA32-NEXT:    addi.w $a0, $a0, 2033
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_4080:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a1, $zero, 4080
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addi.w $a0, $a0, 2047
+; LA64-NEXT:    addi.w $a0, $a0, 2033
 ; LA64-NEXT:    ret
   %add = add i32 %x, 4080
   ret i32 %add
 }
 
 define signext i32 @add_i32_minus_4080(i32 %x) {
 ; LA32-LABEL: add_i32_minus_4080:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a1, -1
-; LA32-NEXT:    ori $a1, $a1, 16
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, -2048
+; LA32-NEXT:    addi.w $a0, $a0, -2032
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_4080:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -1
-; LA64-NEXT:    ori $a1, $a1, 16
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addi.w $a0, $a0, -2048
+; LA64-NEXT:    addi.w $a0, $a0, -2032
 ; LA64-NEXT:    ret
   %add = add i32 %x, -4080
   ret i32 %add
 }
 
 define signext i32 @add_i32_2048(i32 %x) {
 ; LA32-LABEL: add_i32_2048:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a1, $zero, 2048
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, 2047
+; LA32-NEXT:    addi.w $a0, $a0, 1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_2048:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a1, $zero, 2048
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addi.w $a0, $a0, 2047
+; LA64-NEXT:    addi.w $a0, $a0, 1
 ; LA64-NEXT:    ret
   %add = add i32 %x, 2048
   ret i32 %add
 }
 
 define signext i32 @add_i32_4094(i32 %x) {
 ; LA32-LABEL: add_i32_4094:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a1, $zero, 4094
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, 2047
+; LA32-NEXT:    addi.w $a0, $a0, 2047
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_4094:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a1, $zero, 4094
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addi.w $a0, $a0, 2047
+; LA64-NEXT:    addi.w $a0, $a0, 2047
 ; LA64-NEXT:    ret
   %add = add i32 %x, 4094
   ret i32 %add
 }
 
 define signext i32 @add_i32_minus_2049(i32 %x) {
 ; LA32-LABEL: add_i32_minus_2049:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a1, -1
-; LA32-NEXT:    ori $a1, $a1, 2047
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, -2048
+; LA32-NEXT:    addi.w $a0, $a0, -1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_2049:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -1
-; LA64-NEXT:    ori $a1, $a1, 2047
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addi.w $a0, $a0, -2048
+; LA64-NEXT:    addi.w $a0, $a0, -1
 ; LA64-NEXT:    ret
   %add = add i32 %x, -2049
   ret i32 %add
 }
 
 define signext i32 @add_i32_minus_4096(i32 %x) {
 ; LA32-LABEL: add_i32_minus_4096:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a1, -1
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, -2048
+; LA32-NEXT:    addi.w $a0, $a0, -2048
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i32_minus_4096:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -1
-; LA64-NEXT:    add.w $a0, $a0, $a1
+; LA64-NEXT:    addi.w $a0, $a0, -2048
+; LA64-NEXT:    addi.w $a0, $a0, -2048
 ; LA64-NEXT:    ret
   %add = add i32 %x, -4096
   ret i32 %add
 }
 
 define i64 @add_i64_4080(i64 %x) {
 ; LA32-LABEL: add_i64_4080:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a2, $zero, 4080
-; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    addi.w $a2, $a0, 2047
+; LA32-NEXT:    addi.w $a2, $a2, 2033
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_4080:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a1, $zero, 4080
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addi.d $a0, $a0, 2047
+; LA64-NEXT:    addi.d $a0, $a0, 2033
 ; LA64-NEXT:    ret
   %add = add i64 %x, 4080
   ret i64 %add
 }
 
 define i64 @add_i64_minus_4080(i64 %x) {
 ; LA32-LABEL: add_i64_minus_4080:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a2, -1
-; LA32-NEXT:    ori $a2, $a2, 16
-; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    addi.w $a2, $a0, -2048
+; LA32-NEXT:    addi.w $a2, $a2, -2032
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    addi.w $a1, $a0, -1
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_minus_4080:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -1
-; LA64-NEXT:    ori $a1, $a1, 16
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addi.d $a0, $a0, -2048
+; LA64-NEXT:    addi.d $a0, $a0, -2032
 ; LA64-NEXT:    ret
   %add = add i64 %x, -4080
   ret i64 %add
 }
 
 define i64 @add_i64_2048(i64 %x) {
 ; LA32-LABEL: add_i64_2048:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a2, $zero, 2048
-; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    addi.w $a2, $a0, 2047
+; LA32-NEXT:    addi.w $a2, $a2, 1
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_2048:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a1, $zero, 2048
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addi.d $a0, $a0, 2047
+; LA64-NEXT:    addi.d $a0, $a0, 1
 ; LA64-NEXT:    ret
   %add = add i64 %x, 2048
   ret i64 %add
 }
 
 define i64 @add_i64_4094(i64 %x) {
 ; LA32-LABEL: add_i64_4094:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a2, $zero, 4094
-; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    addi.w $a2, $a0, 2047
+; LA32-NEXT:    addi.w $a2, $a2, 2047
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a1, $a1, $a0
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_4094:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ori $a1, $zero, 4094
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addi.d $a0, $a0, 2047
+; LA64-NEXT:    addi.d $a0, $a0, 2047
 ; LA64-NEXT:    ret
   %add = add i64 %x, 4094
   ret i64 %add
 }
 
 define i64 @add_i64_minus_2049(i64 %x) {
 ; LA32-LABEL: add_i64_minus_2049:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a2, -1
-; LA32-NEXT:    ori $a2, $a2, 2047
-; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    addi.w $a2, $a0, -2048
+; LA32-NEXT:    addi.w $a2, $a2, -1
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    addi.w $a1, $a0, -1
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_minus_2049:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -1
-; LA64-NEXT:    ori $a1, $a1, 2047
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addi.d $a0, $a0, -2048
+; LA64-NEXT:    addi.d $a0, $a0, -1
 ; LA64-NEXT:    ret
   %add = add i64 %x, -2049
   ret i64 %add
 }
 
 define i64 @add_i64_minus_4096(i64 %x) {
 ; LA32-LABEL: add_i64_minus_4096:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    lu12i.w $a2, -1
-; LA32-NEXT:    add.w $a2, $a0, $a2
+; LA32-NEXT:    addi.w $a2, $a0, -2048
+; LA32-NEXT:    addi.w $a2, $a2, -2048
 ; LA32-NEXT:    sltu $a0, $a2, $a0
 ; LA32-NEXT:    add.w $a0, $a1, $a0
 ; LA32-NEXT:    addi.w $a1, $a0, -1
 ; LA32-NEXT:    move $a0, $a2
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: add_i64_minus_4096:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    lu12i.w $a1, -1
-; LA64-NEXT:    add.d $a0, $a0, $a1
+; LA64-NEXT:    addi.d $a0, $a0, -2048
+; LA64-NEXT:    addi.d $a0, $a0, -2048
 ; LA64-NEXT:    ret
   %add = add i64 %x, -4096
   ret i64 %add
 }

llvm/test/CodeGen/LoongArch/ldptr.ll

entry:
   %val = load i32, ptr %addr, align 4
   ret i32 %val
 }
 
 ;; Check that ldptr.w is emitted for applicable offsets.
 define signext i32 @ldptr_w(ptr %p) nounwind {
 ; LA32-LABEL: ldptr_w:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a1, $zero, 2048
-; LA32-NEXT:    add.w $a0, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, 2047
+; LA32-NEXT:    addi.w $a0, $a0, 1
 ; LA32-NEXT:    ld.w $a0, $a0, 0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldptr_w:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ldptr.w $a0, $a0, 2048
 ; LA64-NEXT:    ret
 entry:
entry:
   %val = load i64, ptr %addr, align 8
   ret i64 %val
 }
 
 ;; Check that ldptr.d is emitted for applicable offsets.
 define i64 @ldptr_d(ptr %p) nounwind {
 ; LA32-LABEL: ldptr_d:
 ; LA32:       # %bb.0: # %entry
-; LA32-NEXT:    ori $a1, $zero, 2048
-; LA32-NEXT:    add.w $a1, $a0, $a1
+; LA32-NEXT:    addi.w $a0, $a0, 2047
+; LA32-NEXT:    addi.w $a1, $a0, 1
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:    ld.w $a1, $a1, 4
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: ldptr_d:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    ldptr.d $a0, $a0, 2048
 ; LA64-NEXT:    ret

llvm/test/CodeGen/LoongArch/stptr.ll

; LA64-NEXT:    ret
   store i32 %val, ptr %addr, align 4
   ret void
 }
 
 ;; Check that stptr.w is emitted for applicable offsets.
 define void @stptr_w(ptr %p, i32 signext %val) nounwind {
 ; LA32-LABEL: stptr_w:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a2, $zero, 2048
-; LA32-NEXT:    add.w $a0, $a0, $a2
+; LA32-NEXT:    addi.w $a0, $a0, 2047
+; LA32-NEXT:    addi.w $a0, $a0, 1
 ; LA32-NEXT:    st.w $a1, $a0, 0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: stptr_w:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    stptr.w $a1, $a0, 2048
 ; LA64-NEXT:    ret
   %addr = getelementptr inbounds i32, ptr %p, i64 512
; LA64-NEXT:    ret
   store i64 %val, ptr %addr, align 8
   ret void
 }
 
 ;; Check that stptr.d is emitted for applicable offsets.
 define void @stptr_d(ptr %p, i64 %val) nounwind {
 ; LA32-LABEL: stptr_d:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    ori $a3, $zero, 2048
-; LA32-NEXT:    add.w $a0, $a0, $a3
+; LA32-NEXT:    addi.w $a0, $a0, 2047
+; LA32-NEXT:    addi.w $a0, $a0, 1
 ; LA32-NEXT:    st.w $a2, $a0, 4
 ; LA32-NEXT:    st.w $a1, $a0, 0
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: stptr_d:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    stptr.d $a1, $a0, 2048
 ; LA64-NEXT:    ret